Control Bits - Analog Devices AD9833 Manual

AD9833
Control Register
The AD9833 contains a 16-bit control register that sets up the
AD9833 as the user wants to operate it. All control bits, except
MODE, are sampled on the internal negative edge of MCLK.
Table II describes the individual bits of the control register.
The different functions and the various output options from
the AD9833 are described in more detail in the section
following Table II.
SLEEP12
SLEEP1
RESET
MODE + OPBITEN
DIV2
OPBITEN
DB15 DB14 DB13 DB12
0
Bit Name Function
D13 B28 Two write operations are required to load a complete word into either of the frequency registers.
B28 = 1 allows a complete word to be loaded into a frequency register in two consecutive writes. The first write
contains the 14 LSBs of the frequency word, and the next write will contain the 14 MSBs. The first two bits of
each 16-bit word define the frequency register to which the word is loaded and should, therefore, be the same
for both of the consecutive writes. Refer to Table IV for the appropriate addresses. The write to the frequency
register occurs after both words have been loaded, so the register never holds an intermediate value. An example
of a complete 28-bit write is shown in Table V.
When B28 = 0, the 28-bit frequency register operates as two 14-bit registers, one containing the 14 MSBs and
the other containing the 14 LSBs. This means that the 14 MSBs of the frequency word can be altered independent
of the 14 LSBs, and vice versa. To alter the 14 MSBs or the 14 LSBs, a single write is made to the appropriate
frequency address. The control bit D12 (HLB) informs the AD9833 whether the bits to be altered are the
14 MSBs or 14 LSBs.
D12 HLB This control bit allows the user to continuously load the MSBs or LSBs of a frequency register while ignoring
the remaining 14 bits. This is useful if the complete 28-bit resolution is not required. HLB is used in conjunction
with D13 (B28). This control bit indicates whether the 14 bits being loaded are being transferred to the 14 MSBs
or 14 LSBs of the addressed frequency register. D13 (B28) must be set to 0 to be able to change the MSBs and
LSBs of a frequency word separately. When D13 (B28) = 1, this control bit is ignored.
HLB = 1 allows a write to the 14 MSBs of the addressed frequency register.
HLB = 0 allows a write to the 14 LSBs of the addressed frequency register.
D11 FSELECT The FSELECT bit defines whether the FREQ0 register or the FREQ1 register is used in the phase accumulator.
D10 PSELECT The PSELECT bit defines whether the PHASE0 register or the PHASE1 register data is added to the output of
the phase accumulator.
D9 Reserved This bit should be set to 0.
D8 RESET RESET = 1 resets internal registers to 0, which corresponds to an analog output of midscale.
RESET = 0 disables RESET. This function is explained further in Table IX.
D7 SLEEP1 When SLEEP1 = 1, the internal MCLK clock is disabled, the DAC output will remain at its present value as
the NCO is no longer accumulating.
When SLEEP1 = 0, MCLK is enabled. This function is explained further in Table X.
SIN
ROM
PHASE
ACCUMULATOR
(28-BIT)
DB11 DB10
0 B28 HLB FSELECT PSELECT
Figure 5. Function of Control Bits
Table II. Description of Bits in the Control Register
To inform the AD9833 that the contents of the control register
will be altered, D15 and D14 must be set to 0 as shown below.
D15 D14
0 0
(LOW POWER)
0
10-BIT DAC
MUX
1
1
MUX
DIVIDE
0
BY 2
DB9 DB8 DB7 DB6 DB5
0 RESET SLEEP1 SLEEP12 OPBITEN
–10–
Table I. Control Register
D13

CONTROL BITS

AD9833
DIGITAL
VOUT
OUTPUT
(ENABLE)
DB4 DB3 DB2 DB1 DB0
0 DIV2 0 MODE 0
D0
REV. A