Analog Devices AD9833 Manual page 11

Bit Name Function
D6 SLEEP12 SLEEP12 = 1 powers down the on-chip DAC. This is useful when the AD9833 is used to output the MSB of
the DAC data.
SLEEP12 = 0 implies that the DAC is active. This function is explained further in Table X.
D5 OPBITEN The function of this bit, in association with D1 (MODE), is to control what is output at the VOUT pin. This is
explained further in Table XI.
When OPBITEN = 1, the output of the DAC is no longer available at the VOUT pin. Instead, the MSB (or
MSB/2) of the DAC data is connected to the VOUT pin. This is useful as a coarse clock source. The bit DIV2
controls whether it is the MSB or MSB/2 that is output.
When OPBITEN = 0, the DAC is connected to VOUT. The MODE bit determines whether it is a sinusoidal
or a ramp output that is available.
D4 Reserved This bit must be set to 0.
D3 DIV2 DIV2 is used in association with D5 (OPBITEN). This is explained further in Table XI.
When DIV2 = 1, the MSB of the DAC data is passed directly to the VOUT pin.
When DIV2 = 0, the MSB/2 of the DAC data is output at the VOUT pin.
D2 Reserved This bit must be set to 0.
D1 MODE This bit is used in association with OPBITEN (D5). The function of this bit is to control what is output at
the VOUT pin when the on-chip DAC is connected to VOUT. This bit should be set to 0 if the control bit
OPBITEN = 1. This is explained further in Table XI.
When MODE = 1, the SIN ROM is bypassed, resulting in a triangle output from the DAC.
When MODE = 0, the SIN ROM is used to convert the phase information into amplitude information, which
results in a sinusoidal signal at the output.
D0 Reserved This bit must be set to 0.
Frequency and Phase Registers
The AD9833 contains two frequency registers and two phase
registers, which are described in Table III.
Table III. Frequency/Phase Registers
Register Size Description
FREQ0 28 Bits Frequency Register 0. When the FSELECT
bit = 0, this register defines the output fre-
quency as a fraction of the MCLK frequency.
FREQ1 28 Bits Frequency Register 1. When the FSELECT
bit = 1, this register defines the output fre-
quency as a fraction of the MCLK frequency.
PHASE0 12 Bits Phase Offset Register 0. When the PSELECT
bit = 0, the contents of this register are added
to the output of the phase accumulator.
PHASE1 12 Bits Phase Offset Register 1. When the PSELECT
bit = 1, the contents of this register are added
to the output of the phase accumulator.
REV. A
Table II. Description of Bits in the Control Register (continued)
The analog output from the AD9833 is
f
MCLK
where FREQREG is the value loaded into the selected frequency
register. This signal will be phase shifted by
2 p/4096 ¥ PHASEREG
where PHASEREG is the value contained in the selected
phase register. Consideration must be given to the relationship of
the selected output frequency and the reference clock frequency
to avoid unwanted output anomalies.
The flow chart in Figure 9 shows the routine for writing to the
frequency and phase registers of the AD9833.
Writing to a Frequency Register
When writing to a frequency register, Bits D15 and D14 give
the address of the frequency register.
Table IV. Frequency Register Bits
D15 D14 D13
0 1 MSB
1 0 MSB
–11–
AD9833
28
/2 ¥ FREQREG
14 FREQ0 REG Bits
14 FREQ1 REG Bits
D0
LSB
LSB