Reset Bit - Analog Devices AD9833 Manual

AD9833
If the user wants to change the entire contents of a frequency regis-
ter, two consecutive writes to the same address must be performed
since the frequency registers are 28 bits wide. The first write will
contain the 14 LSBs, while the second write will contain the 14 MSBs. the phase, frequency, or control registers. When the AD9833 is
For this mode of operation, the control bit B28 (D13) should
be set to 1. An example of a 28-bit write is shown in Table V.
Table V. Writing 00FC00 to FREQ0 REG
SDATA Input Result of Input Word
0010 0000 0000 0000 Control Word Write (D15, D14 = 00),
B28 (D13) = 1, HLB (D12) = X
0100 0000 0000 0000 FREQ0 REG Write (D15, D14 = 01),
14 LSBs = 0000
0100 0000 0011 1111 FREQ0 REG Write (D15, D14 = 01),
14 MSBs = 003F
In some applications, the user does not need to alter all 28 bits
of the frequency register. With coarse tuning, only the 14 MSBs
are altered, while with fine tuning, only the 14 LSBs are altered.
By setting the control bit B28 (D13) to 0, the 28-bit frequency
register operates as two, 14-bit registers, one containing the
14 MSBs and the other containing the 14 LSBs. This means that
the 14 MSBs of the frequency word can be altered independent
of the 14 LSBs, and vice versa. Bit HLB (D12) in the control
register identifies which 14 bits are being altered. Examples of
this are shown in Tables VI and VII.
Table VI. Writing 3FFF to the 14 LSBs of FREQ1 REG
SDATA Input Result of Input Word
0000 0000 0000 0000 Control Word Write (D15, D14 = 00),
B28 (D13) = 0; HLB (D12) = 0,
i.e. LSBs
1011 1111 1111 1111 FREQ1 REG Write (D15, D14 = 10),
14 LSBs = 3FFF
Table VII. Writing 00FF to the 14 MSBs of FREQ0 REG
SDATA Input Result of Input Word
0001 0000 0000 0000 Control Word Write (D15, D14 = 00),
B28 (D13) = 0, HLB (D12) = 1,
i.e., MSBs
0100 0000 1111 1111 FREQ0 REG Write (D15, D14 = 01),
14 MSBs = 00FF
Writing to a Phase Register
When writing to a phase register, Bits D15 and D14 are set to 11.
Bit D13 identifies which phase register is being loaded.
Table VIII. Phase Register Bits
D15 D14 D13 D12
1 1 0 X
1 1 1 X
D11
MSB 12 PHASE0 Bits
MSB 12 PHASE1 Bits
RESET Function
The RESET function resets appropriate internal registers to 0
to provide an analog output of midscale. RESET does not reset
powered up, the part should be reset. To reset the AD9833, set
the RESET bit to 1. To take the part out of reset, set the bit to 0.
A signal will appear at the DAC to output eight MCLK cycles
after RESET is set to 0.

RESET Bit

0
1
SLEEP Function
Sections of the AD9833 that are not in use can be powered
down to minimize power consumption. This is done using the
SLEEP function. The parts of the chip that can be powered
down are the internal clock and the DAC. The bits required for
the SLEEP function are outlined in Table X.
Table X. Applying the SLEEP Function
SLEEP1 Bit SLEEP12 Bit Result
0 0
0 1
1 0
1 1
DAC Powered Down
This is useful when the AD9833 is used to output the MSB of
the DAC data only. In this case, the DAC is not required so it
can be powered down to reduce power consumption.
Internal Clock Disabled
When the internal clock of the AD9833 is disabled, the DAC
output will remain at its present value as the NCO is no longer
accumulating. New frequency, phase, and control words can be
written to the part when the SLEEP1 control bit is active. The
synchronizing clock is still active, which means that the selected
frequency and phase registers can also be changed using the
control bits. Setting the SLEEP1 bit to 0 enables the MCLK.
Any changes made to the registers while SLEEP1 was active will
be seen at the output after a certain latency.
VOUT Pin
The AD9833 offers a variety of outputs from the chip, all of which
are available from the VOUT pin. The choice of outputs are the
MSB of the DAC data, a sinusoidal output, or a triangle output.
The OPBITEN (D5) and MODE (D1) bits in the control
register are used to decide which output is available from the
AD9833. This is explained further below and also in Table XI.
D0
MSB of the DAC Data
LSB
The MSB of the DAC data can be output from the AD9833. By
LSB
setting the OPBITEN (D5) control bit to 1, the MSB of the DAC
data is available at the VOUT pin. This is useful as a coarse
clock source. This square wave can also be divided by two before
being output. The DIV2 (D3) bit in the control register controls
the frequency of this output from the VOUT pin.
–12–
Table IX. Applying RESET
Result
No Reset Applied
Internal Registers Reset
No Power-Down
DAC Powered Down
Internal Clock Disabled
Both the DAC Powered Down
and the Internal Clock Disabled
REV. A