Analog Devices AD9833 Manual page 2

AD9833–SPECIFICATIONS
Parameter
SIGNAL DAC SPECIFICATIONS
Resolution
Update Rate
V Max
OUT
V Min
OUT
V TC
OUT
DC Accuracy
Integral Nonlinearity
Differential Nonlinearity
DDS SPECIFICATIONS
Dynamic Specifications
Signal-to-Noise Ratio
Total Harmonic Distortion
Spurious-Free Dynamic Range (SFDR)
Wideband (0 to Nyquist)
Narrow Band (±200 kHz)
Clock Feedthrough
Wake-Up Time
LOGIC INPUTS
V , Input High Voltage
INH
V , Input Low Voltage
INL
I /I , Input Current
INH INL
C , Input Capacitance
IN
POWER SUPPLIES
VDD
I
DD
Low Power Sleep Mode
*Operating temperature range is as follows: B Version: –40∞C to +105∞C; typical specifications are at 25∞C.
Specifications subject to change without notice.
(VDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, T = T
*
VOUT, unless otherwise noted.)
Min Typ
10
0.65
38
200
±1.0
±0.5
55 60
–66
–60
–78
–60
1
1.7
2.0
2.8
3
2.3
4.5
0.5
100nF
CAP/2.5V
REGULATOR
12
AD9833
Figure 1. Test Circuit Used to Test Specifications
Max Unit
Bits
25 MSPS
V
mV
ppm/∞C
LSB
LSB
dB
–56 dBc
dBc
dBc
dBc
ms
V
V
V
0.5 V
0.7 V
0.8 V
10 mA
pF
5.5 V
5.5 mA
mA
VDD
10nF
COMP
VOUT
SIN
10-BIT DAC
ROM
–2–
to T , R = 6.8 k for
A MIN MAX SET
Test Conditions/Comments
f = 25 MHz, f = f
MCLK OUT
f = 25 MHz, f = f
MCLK OUT
f = 25 MHz, f = f
MCLK OUT
f = 25 MHz, f = f
MCLK OUT
2.3 V to 2.7 V Power Supply
2.7 V to 3.6 V Power Supply
4.5 V to 5.5 V Power Supply
2.3 V to 2.7 V Power Supply
2.7 V to 3.6 V Power Supply
4.5 V to 5.5 V Power Supply
f = 25 MHz, f = f
MCLK OUT
I Code Dependent. See TPC 2.
DD
DAC Powered Down,
MCLK Running
20pF
/4096
MCLK
/4096
MCLK
/50
MCLK
/50
MCLK
/4096
MCLK
REV. A