Holtek HT45F8550 Manual page 105

HT45F8550
BMS Flash MCU
Register
Name
7
STMC0 STPAU
STMC1 STM1
STMDL D7
STMDH D15
STMAL D7
STMAH D15
STMRP STRP7
• STMC0 Register
Bit 7
Name STPAU
R/W R/W
POR 0
Bit 7 STPAU: STM counter pause control
0: Run
1: Pause
The counter can be paused by setting this bit high. Clearing the bit to zero restores
normal counter operation. When in a Pause condition the STM will remain powered up
and continue to consume power. The counter will retain its residual value when this bit
changes from low to high and resume counting from this value when the bit changes to
a low value again.
STCK2~STCK0: STM counter clock selection
Bit 6~4
000: f
001: f
010: f
011: f
100: f
101: f
110: STCK rising edge clock
111: STCK falling edge clock
These three bits are used to select the clock source for the STM. The external pin clock
source can be chosen to be active on the rising or falling edge. The clock source f
the system clock, while f
be found in the oscillator section.
STON: STM counter on/off control
Bit 3
0: Off
1: On
This bit controls the overall on/off function of the STM. Setting the bit high enables
the counter to run while clearing the bit disables the STM. Clearing this bit to zero
will stop the counter from counting and turn off the STM which will reduce its power
consumption. When the bit changes state from low to high the internal counter value
will be reset to zero, however when the bit changes from high to low, the internal
counter will retain its residual value until the bit returns high again.
If the STM is in the Compare Match Output Mode or PWM output Mode or Single
Pulse Output Mode, then the STM output pin will be reset to its initial condition, as
specified by the STOC bit, when the STON bit changes from low to high.
Bit 2~0 Unimplemented, read as "0"
Rev. 1.70
6 5 4
STCK2 STCK1 STCK0
STM0 STIO1 STIO0
D6 D5 D4
D14 D13 D12
D6 D5 D4
D14 D13 D12
STRP6 STRP5 STRP4
16-bit Standard TM Register List
6 5 4
STCK2 STCK1 STCK0
R/W R/W R/W
0 0 0
/4
SYS
SYS
/16
H
/64
H
SUB
SUB
and f are other internal clocks, the details of which can
H SUB
105
Bit
3 2 1
STON — —
STOC STPOL STDPX
D3 D2 D1
D11 D10 D9
D3 D2 D1
D11 D10 D9
STRP3 STRP2 STRP1
3 2 1
STON — —
R/W — —
0 — —
January 31, 2024
0
—
STCCLR
D0
D8
D0
D8
STRP0
0
—
—
—
is
SYS