Related Manuals for Texas Instruments Muxlt
Summary of Contents for Texas Instruments Muxlt
- Page 1 MuxIt Evaluation Module (EVM) User’s Guide January 2001 AAP HPL SLLU023 This datasheet has been downloaded from http://www.digchip.com at this page...
- Page 2 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability.
- Page 3 The following documents describe the MuxIt and related support tools. To obtain a copy of any of these TI documents call the Texas Instruments Litera- ture Response Center at (800) 477–8924. When ordering, please identify the book by its title and literature number.
- Page 4 7) LVDS Multidrop Connections Literature No. SLLA054 8) Measuring Crosstalk In LVDS Systems Literature No. SLLA064 9) Performance Of LVDS With Different Cables Literature No. SLLA053 10) Slew Rate Control Of LVDS Circuits Literature No. SLLA034A Trademarks MuxIt is a trademark of Texas Instruments.
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Page 5: Table Of Contents
Running Title—Attribute Reference Contents Introduction ..............What is MuxIt? . - Page 6 Running Title—Attribute Reference Figures 2–1 Serializer Board Simplified Block Diagram ........2–2 Serializer Board .
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Page 7: Introduction
Chapter 1 Introduction This chapter provides a basic introduction to MuxIt and the EVM. Topic Page What is MuxIt? ..........Introduction... -
Page 8: What Is Muxit
What is MuxIt? 1.1 What is MuxIt? MuxIt is a family of general-purpose building blocks designed to serialize and deserialize parallel data. This family includes three types of devices support- ing simplex communications: A PLL frequency multiplier (SN65LVDS150), a serializer-transmitter (SN65LVDS151), and a receiver-deserializer (SN65LVDS152). -
Page 9: Evm Hardware Contents
Chapter 2 EVM Hardware Contents This chapter describes the EVM hardware. The MuxIt EVM kit allows system designers to become familiar with the operation and features of MuxIt quickly and easily. This kit consists of the following items: Serializer board with jumpers Deserializer board with jumpers Adapter header Topic... -
Page 10: Serializer Board
Serializer Board 2.1 Serializer Board The serializer board (P/N 6422795A) uses three SN65LVDS151 MuxIt serializer-transmitter devices (U2–U4) and an SN65LVDS150 phase-locked loop (PLL) frequency multiplier (U1) to convert parallel single-ended inputs to a serialized LVDS link containing one or two data pairs and a clock pair. The serializer board will be referred to as A1 and the deserializer board will be referred to as A2 throughout this document to identify jumper, connector, test point, and device references with the appropriate board. -
Page 11: Serializer Board Jumpers
Serializer Board other can be remotely powered through the J2 connector. The GND connection between the two boards can be established by installing A1:JMP-11 and A2:JMP-3 on the deserializer. The VCC connection between the two can be established by installing A1:JMP-12 and A2:JMP-2 on the deserializer. -
Page 12: Serializer Board Simplified Block Diagram
Serializer Board Figure 2–1. Serializer Board Simplified Block Diagram Input Clock J3/J4 Multiplexed Multiplier Select Clock (LVDS) PLL/Multiplier SN65LVDS150 (U1) Band Select Link Clock(LVDS) Cascade Data (LVDS) Serializer SN65LVDS151 (U2) DI-9 DI-9 10 Bits DI-0 DI-0 Cascade Link Clock Enable Output Enable JMP-7 Serializer... -
Page 13: Deserializer Board
Deserializer Board Figure 2–2. Serializer Board 2.2 Deserializer Board The deserializer board (P/N 6422796A) uses three SN65LVDS152 receiver-deserializers (A2:U2–U4) and a SN65LVDS150 PLL frequency multiplier (A2:U1) to accept the serialized data and clock signals and convert this serialized data stream back to the original parallel single-ended outputs. A block diagram and photograph of the deserializer board is provided in Figures 2–3 and 2–4, respectively. -
Page 14: Operations Supported By The Deserializer Board
Deserializer Board Table 2–2. Deserializer Board Jumpers Jumper Number Jumper Type As Shipped Description A2:JMP–2 One position Installed When installed Remote VCC, A2:J2 pin 1, is connected to the deser- ializer board VCC plane. A2:JMP–3 One position Installed When installed remote ground, A2:J2 pin 2, is connected to the des- erializer board GND plane. -
Page 15: Deserializer Board Simplified Block Diagram
Deserializer Board Figure 2–3. Deserializer Board Simplified Block Diagram Multiplier Select Multiplexed Band Select Clock (LVDS) PLL/Multiplier SN65LVDS150 (U1) LCI (LVDS) J2-4/5 Cascade Enable Cascade_DI Clock Out (LVDS) J2-7/8 Deserializer SN65LVDS152 (U2) DO-9 DO-9 Cascade 10 Bits Data (LVDS) DO-0 DO-0 Clock Out Deserializer... -
Page 16: Adapter Header
Adapter Header Figure 2–4. Deserializer Board 2.3 Adapter Header Two connectors are included, one on each board, so the user can use his own interconnect to evaluate and predict performance. The user can connect the two boards using any suitable cable of their choice, such as UTP CAT-5, or the two boards may be connected directly using the adapter header provided. -
Page 17: Test Equipment
Chapter 3 Test Equipment This chapter describes the test equipment used with the MuxIt EVM. Topic Page Pattern Generator ..........Oscilloscope and Scope Probes . -
Page 18: Pattern Generator
Pattern Generator 3.1 Pattern Generator A signal or pattern generator can provide a clock reference input signal to the serializer board. Twenty simultaneous inputs are required to fully exercise the cascade inputs, so a pattern generator with 20 parallel outputs and a clock rate range up to 50 MHz is suggested. -
Page 19: Operation
Chapter 4 Operation This chapter describes the operation of the MuxIt EVM. Topic Page Before Operating the EVM ........Basic Operation Using a Single LVDS Data Pair . -
Page 20: Before Operating The Evm
Before Operating the EVM 4.1 Before Operating the EVM Before operating the MuxIt EVM the user should become familiar with the schematics, data sheets, and The MuxIt Data Transmission System Applications, Examples, and Design Guidelines (SLLA093). The user should locate each connector, test point, and jumper on each board and on each schematic. -
Page 21: Basic 10:1 Serial Operation
Basic Operation Using a Single LVDS Data Pair Figure 4–1. Basic 10:1 Serial Operation Data and Clock Input – + + – – + DI–0 ... DI–9 LCRI LCRO SN65LVDS151 SN65LVDS150 ST–A MuxIt MuxIt PLL Serializer–Transmitter (U3) Frequency Multiplier (U1) LCRO BSEL + –... -
Page 22: Multiplier And Band Select Switch To Pll
Basic Operation Using a Single LVDS Data Pair Figure 4–2. Multiplier and Band Select Switch to PLL PLL SN65LVDS150 BSEL Basic serial operation is the simplest of the MuxIt capabilities. For 10:1 serial data, the Clock Reference input can be increased to 1/10th the serial LVDS signaling rate. -
Page 23: Cascade Data Operation
Cascade Data Operation Table 4–1. Input–to-Output Bit Mapping for 4–10 Bit Serial Operation Outputs Inp ts Inputs M = 4 M = 6 M = 8 M = 9 M = 10 DI–0 (A1:P2) DO–6 (A2:P1) DO–4 (A2:P1) DO–2 (A2:P1) DO–1 (A2:P1) DO–0 (A2:P1) DI–1 (A1:P2) -
Page 24: Cascade Mode Operation For 12- To 20-Parallel Bits
Cascade Data Operation Figure 4–3. Cascade Mode Operation for 12- to 20-Parallel Bits Data and Clock Input DI–0 ... DI–9 – + DI–0 ... DI–9 – + + – – + LCRI LCRI LCRO SN65LVDS151 SN65LVDS151 SN65LVDS150 MuxIt MuxIt MuxIt PLL Serializer–Transmitter (U3) Serializer–Transmitter (U2) Frequency Multiplier (U1) -
Page 25: Input-To-Output Bit Mapping For 12- To 20-Bit Cascade Mode
Cascade Data Operation Table 4–2. Input-to-Output Bit Mapping for 12- to 20-Bit Cascade Mode Outputs Inp ts Inputs M = 12 M = 13 M = 14 M = 15 M = 16 M = 17 M = 18 M = 19 M = 20 DI–0 DO–8... -
Page 26: Parallel Operation Using Two Lvds Data Pairs
Parallel Operation Using Two LVDS Data Pairs Although not supported by this EVM, up to 40 LVTTL parallel inputs can be serialized down to two pair of LVDS lines. This topology would require four SN65LVDS151 serializer-transmitters and four SN65LVDS152 deserializer- receivers. - Page 27 Parallel Operation Using Two LVDS Data Pairs Figure 4–4. 8- to 20-Bit Parallel Operation Using Two LVDS Data Lines Data and Clock Input DI–0 ... DI–9 – + DI–0 ... DI–9 – + + – – + LCRI LCRI LCRO SN65LVDS151 SN65LVDS151 SN65LVDS150...
- Page 28 Parallel Operation Using Two LVDS Data Pairs to eight) and the effective throughput. For example, if 16-bit parallel input data needs to be sampled at 10 MHz, then the data is equally divided between A1:P2 and A1:P3. The clock reference is set to 10 MHz and the PLL multiplier to 8.
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Page 29: System Design Issues
Chapter 5 System Design Issues This chapter discusses basic design issues and board layout guidelines used in designing the MuxIt EVM boards. These guidelines should be followed to ensure the user is successful in designing their MuxIt interface. The user should also refer to the Application Note SLLA014, Low Voltage Differential Signaling (LVDS) Design Notes , for general board layout guidelines. -
Page 30: Pc Board Layout Considerations
PC Board Layout Considerations 5.1 PC Board Layout Considerations The difference in propagation delay of signal interfaces is an important parameter, and the signal interface between the PLL and the serializer or deserializer devices needs to be matched in length and medium. Propagation delays are inevitable, but it is important to maintain a timing relationship between the multiplied clock (MCO, MCI) and the link clock reference (LCRO, LCRI) signals at the source end. - Page 31 PC Board Layout Considerations System Design Issues...
- Page 32 PC Board Layout Considerations System Design Issues...
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Page 33: Serializer Board Mco Trace Routing
PC Board Layout Considerations Like the clock signals, the propagation delay of data signal interfaces also have to be related. The remaining critical propagation delays for Figure 5–1 are given by: pd(LCO) pd(CASCADE_DO) pd(CASCADE_DO) pd(A1:MC2) pd(SERIAL_DO) pd(A1:MC3) and for Figure 5–2 are given by: pd(CASCADE_DI) pd(LCI1) pd(SERIAL_DI) -
Page 34: Terminations And Multidrop Configurations
Terminations and Multidrop Configurations Figure 5–4. Deserializer LCI Trace Routing SN65LVDS150 (U1) SN65LVDS151 (U2) SN65LVDS151 (U3) SN65LVDS151 (U4) Fly-by Routing Stub LCI Termination Resistor Deserializer Board Layer1 Layer6 Stub 5.2 Terminations and Multidrop Configurations Designers should notice that an internal termination resistor is provided on the CI input of the SN65LVDS151 serializer-transmitter. -
Page 35: Multidrop Configuration Of Muxit Evms
Terminations and Multidrop Configurations Figure 5–5. Multidrop Configuration of MuxIt EVMs MuxIt Serializer Board Data and Clock Input (A1) DI–0 ... DI–9 – + + – – + LCRI LCRO SN65LVDS150 SN65LVDS151 ST–A MuxIt PLL MuxIt Frequency Multiplier (U1) Serializer–Transmitter (U3) LCRO –... -
Page 37: Pc Board Bill Of Material And Schematics
Appendix A PC Board Bill of Material and Schematics This appendix contains the PC board bill of materials, silkscreen art and board layers, and schematics for the MuxIt EVM. Topic Page PC Board Bill of Materials ........Board Layers and Silkscreen Art . -
Page 38: Pc Board Bill Of Materials
PC Board Bill of Materials A.1 PC Board Bill of Materials Table A–1.Parts Lists for MuxIt EVM Serializer Board REFERENCE PART NUMBER DESCRIPTION KITTED PART NUMBER DESIGNATOR BD06 Switch, 6 PST, dip GRAYHILL P/N 76SB06 CES–112–02–T–S–RA 1 12 .1 CTR FEM R/A 51.1 Ω, 0.1 W, 1% CRCW080551R1F R1, R2... - Page 39 Table A–2.Parts Lists for MuxIt EVM Deserializer Board REFERENCE PART NUMBER DESCRIPTION KITTED PART NUMBER DESIGNATOR 76SB06 Switch, 6 PST, dip GRAYHILL CES–112–02–T–S–RA 1 12 .1 CTR FEM R/A 51.1 Ω, 0.1 W, 1%, 603 PCK CRCW060351R1F R40–R72 Not installed (Part Not In Kit) 100 Ω...
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Page 40: Board Layers And Silkscreen Art
Board Layers and Silkscreen Art A.2 Board Layers and Silkscreen Art Figure A–1. Serializer Layer 1 Figure A–2. Serializer Layer 6 Figure A–3. Serializer Layer 8... -
Page 41: Serializer Silkscreen Bottom
Board Layers and Silkscreen Art Figure A–4. Serializer Silkscreen Bottom Figure A–5. Serializer Silkscreen Top PC Board Bill of Material and Schematics... -
Page 42: Deserializer Layer
Board Layers and Silkscreen Art Figure A–6. Deserializer Layer 1 Figure A–7. Deserializer Layer 2 Figure A–8. Deserializer Layer 8... -
Page 43: Deserializer Silkscreen Bottom
Board Layers and Silkscreen Art Figure A–9. Deserializer Silkscreen Bottom Figure A–10. Deserializer Silkscreen Top PC Board Bill of Material and Schematics... -
Page 44: Schematics
Schematics A.3 Schematics...
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