Sino Wealth 8051 Manual

Microcontroller with 24 channels touch-key input and pwm
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Enhanced 8051 Microcontroller with 24 channels Touch-key input and PWM

1. Features

8 bits micro-controller with Pipe-line structured 8051
compatible instruction set
Flash ROM: 64K Bytes
RAM: internal 256 Bytes, external 1280 Bytes, LCD
RAM 28 Bytes, Touchkey RAM 48 Bytes
EEPROM-Like:build-in 4096 Bytes(code option)
Operation Voltage:
f
= 32.768kHz - 24MHz, V
OSC
Oscillator (code option)
- Crystal oscillator: 32.768kHz
- Crystal oscillator: 2MHz - 16MHz
- Ceramic oscillator: 2MHz - 16MHz
- Internal RC oscillator: 24MHz (± 2%)/128K (± 10%)
42/46 CMOS bi-directional I/O pins (44Pin/48Pin)
Built-in pull-up resistor for input pin (30kΩ)
Eight large current driver I/O
24 channels touch-key input
Three 16-bit timer/counters T3 and T4, T5
PCA0 containing two comparison/ capture modules
Two channels 12-bits PWM timer
SPI (Master/slave Mode)
TWI (I2C Interface)
Powerful interrupt sources:
- Timer3, 4, 5, PCA0
- INT0-3
- INT4: 8 input
- ADC, EUART, SPI, TouchKey
- PWM, SCM, CRC, TWI, LPD, LED
Internal Logic Configuration Module (LCM)
Three Enhanced UART (EUART) with own baud rate
generator

2. General Description

The SH79F9461 is a high performance 8051 compatible micro-controller. The SH79F9461 can perform more fast operation
speed and higher calculation performance, if compare SH79F9461 with standard 8051 at same clock speed.
The SH79F9461 retains most features of the standard 8051. These features include internal 256 bytes RAM, Three UART
andINT0, INT1, INT2, INT3, INT4. In addition, SH79F9461 provides external 1280 bytes RAM. It also contains 64K bytes Flash
memory block for program storage.
The SH79F9461 not only include many standard communication modules, such as EUART, TWI, SPI and so on, but also
include dimming LED, LCD diver, 12bit ADC, PWM timer, etc.
In addition, the SH79F9461 also have Touch Key module, CRC module, Logic configurable module (LCM) built in it.
For high reliability and low cost issues, the SH79F9461 builds in Watchdog Timer, Low Voltage Reset function and system
clock monitor. And SH79F9461 also supports two power saving modes to reduce power consumption.
DS000017E
= 2.0V - 5.5V
DD
9 analog inputs 12-bit Analog Digital Converter
LED driver:
- 8 COM/16 SEG LED driver with diming mode
LCD driver:
- 8 X 24dots (1/8 duty 1/4 bias)
- 6 X 26dots (1/6 duty 1/4 bias or 1/3 bias)
- 5 X 27dots (1/5 duty 1/3 bias)
- 4 X 28dots (1/4 duty 1/3 bias)
Built-in low voltage Reset (LVR) function (code
option)
- LVR Voltage1: 4.1V
- LVR Voltage2: 3.7V
- LVR Voltage3: 2.8V
- LVR Voltage4: 2.1V
Built-in CRC verification module, the verify size
can be selected
Low Power Detect (LPD) Module with 16 level
optional
Support single line simulation and download
CPU Machine period:
- 1 oscillator clock
Built-in Watch Dog Timer (WDT)
Built-in oscillator Warm-up timer
Support Low power operation modes:
- Idle Mode
- Power-Down Mode
Flash Type
Package:
- TQFP48
- LQFP44
1
SH79F9461
V2.1

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Summary of Contents for Sino Wealth 8051

  • Page 1: Features

    SH79F9461 with standard 8051 at same clock speed. The SH79F9461 retains most features of the standard 8051. These features include internal 256 bytes RAM, Three UART andINT0, INT1, INT2, INT3, INT4. In addition, SH79F9461 provides external 1280 bytes RAM. It also contains 64K bytes Flash memory block for program storage.
  • Page 2: Block Diagram

    SH79F9461 3. Block Diagram Reset circuit Power Pipelined 8051 architecture Watch Dog 64K Bytes Flash ROM Port 5 Configuration I/Os Internal 256 Bytes P5.0 - P5.5 External 1280Bytes (Exclude System Port 4 Register) Configuration I/Os P4.0 - P4.7 Timer3 (16bit)
  • Page 3: Pin Configration

    SH79F9461 4. Pin Configration 4.1 TQFP48 Package 31 30 TK7/LED_S7/SEG7/P1.6 P3.6/COM7/LED_C7/SEG27/AN6 P3.7/COM8/LED_C8/SEG28/AN7/VIN TK8/LED_S8/SEG8/P1.7 RXD2/LED_S9/SEG9/P2.0 P4.0/INT40/AN0/SWE TXD2/LED_S10/SEG10/P2.1 P4.1/INT41/AN1/TK24 LED_S11/MOSI/SEG11/P2.2 P4.2/INT42/AN2/TK23 SH79F9461U LED_S12/MISO/SEG12/P2.3 P4.3/INT43/AN3/TK22 LED_S13/SCK/SEG13/P2.4 P4.4/AN8/AVREF/TK21 LED_S14/SS/SEG14/P2.5 P4.5/SEG24/TK20 LED_S15/SEG15/P2.6 P4.6/SEG23 LED_S16/SEG16/P2.7 P4.7/SEG22 TK9/SEG17/P0.0 P5.5/SEG21 TK10/SEG18/P0.1 P5.4/SEG20 10 11...
  • Page 4: Lqfp44 Package

    SH79F9461 4.2 LQFP44 Package 25 24 TK8/LED_S8/SEG8/P1.7 P3.4/COM5/LED_C5 /SEG25 /AN4 RXD2/LED_S9/SEG9/P2.0 P3.5/COM6/LED_C6 /SEG26 /AN5 P3.6/COM7/LED_C7 /SEG27 /AN6 TXD2/LED_S10/SEG10/P2.1 P3.7/COM8/LED_C8 /SEG28 /AN7/VIN LED_S11/MOSI/ SEG11/P2.2 P4.0 /INT40/AN0/SWE LED_S12/MISO/ SEG12/P2.3 LED_S13/SCK/ SEG13/P2.4 P4.1 /INT41/AN1/TK24 SH79F9461P LED_S14/SS/ SEG14/P2.5 P4.2/ INT42/AN2/TK23 LED_S15/SEG15/P2.6 P4.3 /INT43 /AN3/TK22 LED_S16/SEG16/P2.7 P4.4 /AN8/ AVREF/TK21 TK9/SEG17 /P0.0...
  • Page 5 SH79F9461 Function UART0 UART1 PWM0 PWM1 PCA0 INT2 RXD0 TXD0 RXD1 TXD1 PWM0 PWM1 P0CEX0 P0CEX1 ECI0 INT2 ◼ ● ● ● ● P0.0 ◼ ● ● ● ● P0.1 ◼ ● ● P0.2 ● ● ● P0.3 ● P0.4 ●...
  • Page 6: Pin Function And Pin Description

    SH79F9461 5. Pin Function and Pin Description Pin No. Type Description I/O PORT P0.0 - P0.7 8-bit bi-directional I/O port P1.0 - P1.7 8-bit bi-directional I/O port P2.0 - P2.7 8-bit bi-directional I/O port P3.0 - P3.7 8-bit bi-directional I/O port P4.0 - P4.7 8-bit bi-directional I/O port P5.0 - P5.5...
  • Page 7 SH79F9461 (continue) Interrupt & Reset & Clock & Power INT0 - INT3 External interrupt 0-3 input source INT40 - INT47 External interrupt 40-47 input source The device will be reset by A low voltage on this pin longer than 10us, an internal ————...
  • Page 8: Product Information

    SH79F9461 6. Product Information SH79F9461: TQFP48, LQFP44 Flash PCA0 Part Num EUARTx LED TouchK Timerx TWI ExINT LCD Package (byte) (byte) (byte) (12bit) (16bit) (12bit) 8 X 24 6 X 26 SH79F9461 1280 4096 0,1,2 16 X 8 3,4,5 ±0.5% TQFP48 5 X 27 4 X 28...
  • Page 9: Sfr Mapping

    SH79F9461 7. SFR Mapping SH79F9461 has 256-byte direct-addressing register,includes universal deat storage and special function register (SFR), The SFR of the SH79F9461 fall into the following categories: CPU Core Registers: ACC, B, PSW, SP, DPL, DPH Enhanced CPU Core Registers: AUXC, DPL1, DPH1, INSCON, XPAGE Power and Clock Control Registers: PCON, SUSLO Flash Registers:...
  • Page 10 SH79F9461 Table 7.1 C51 Core SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 /PIN Reset Value Accumulator 00000000 ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 B Register 00000000 AUXC C Register 00000000 Program Status Word 00000000 Stack Pointer 00000111...
  • Page 11 SH79F9461 Table 7.3 Flash control SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 /PIN Reset Value IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF Offset Register for Programming 00000000 Bank0 SET.7 SET.6 SET.5 SET.4 SET.3 SET.2 SET.1 SET.0...
  • Page 12 SH79F9461 Table 7.6 Interrupt SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 /PIN Reset Value IEN0 Interrupt Enable Control 0 00000000 EADC Bank0 IEN1 Interrupt Enable Control 1 00000000 ESCM ELPD ELED ETWI Bank0 IEN2 Interrupt Enable Control 1 -0000000 EPWM2 EPCA0...
  • Page 13 SH79F9461 Table 7.8 Port SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 /PIN Reset Value 8-bit Port0 00000000 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 Bank0 8-bit Port1 00000000 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 Bank0...
  • Page 14 SH79F9461 Table 7.9 Timer SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 /PIN Reset Value T3CON Timer/Counter3 Control 0-00-000 T3PS.1 T3PS.0 T3CLKS.1 T3CLKS.0 Bank1 Timer/Counter3 Low Byte 00000000 TL3.7 TL3.6 TL3.5 TL3.4 TL3.3 TL3.2 TL3.1 TL3.0 Bank1 Timer/Counter3 High Byte 00000000...
  • Page 15 SH79F9461 (continue) PCA0 capture/compare module 0 P0CPL0 00000000 P0CPL0.7 P0CPL0.6 P0CPL0.5 P0CPL0.4 P0CPL0.3 P0CPL0.2 P0CPL0.1 P0CPL0.0 Bank1 low byte PCA0 capture/compare module 0 P0CPH0 00000000 P0CPH0.7 P0CPH0.6 P0CPH0.5 P0CPH0.4 P0CPH0.3 P0CPH0.2 P0CPH0.1 P0CPH0.0 Bank1 high byte PCA0 capture/compare module 1 P0CPL1 00000000 P0CPL1.7...
  • Page 16 SH79F9461 (continue) SADEN1 Slave Address Mask1 00000000 SADEN1.7 SADEN1.6 SADEN1.5 SADEN1.4 SADEN1.3 SADEN1.2 SADEN1.1 SADEN1.0 Bank1 SADDR1 Slave Address1 00000000 SADDR1.7 SADDR1.6 SADDR1.5 SADDR1.4 SADDR1.3 SADDR1.2 SADDR1.1 SADDR1.0 Bank1 SBRTH1 Baudrate Generator1 00000000 SBRTEN SBRT1.14 SBRT1.13 SBRT1.12 SBRT1.11 SBRT1.10 SBRT1.9 SBRT1.8 Bank1 SBRTL1...
  • Page 17 SH79F9461 Table 7.13 ADC SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 /PIN Reset Value —---—-----— ADCON1 ADC Control1 00000000 ADON ADCIF REFC XTRGEN GO/DONE Bank0 TRGEN TRGEN TRGEN ADCON2 ADC Control2 0000-000 GRP2 GRP1 GRP0 TGAP2 TGAP1 TGAP0...
  • Page 18 SH79F9461 Table 7.15 LED SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 /PIN Reset Value LEDCON LED Control register 0-000--0 LEDON MODE LEDIF COMIF MODSW Bank0 DISCOM COM scan width control register 00000000 DCOM.7 DCOM.6 DCOM.5 DCOM.4 DCOM.3 DCOM.2...
  • Page 19 SH79F9461 Table 7.17 LPD SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 /PIN Reset Value LPDCON LPD Control register 00000--- LPDEN LPDF LPDV LPDIF LPDMD Bank0 LPDSEL LPD level selection register ----0000 LPDS3 LPDS2 LPDS1 LPDS0 Bank0 Table 7.18 CRC SFRs POR/WDT/LVR...
  • Page 20 SH79F9461 (continue) Touch Key amplification coefficient TKDIV04 ----0000 DIV27 DIV26 DIV25 DIV24 Bank0 Register 4 Reference voltage source selection TKVREF 00000000 VREF1 VREF0 CMPD1 CMPD0 VTK1 VTK0 TUNE1 TUNE0 Bank0 Register Touch Key frequency selection TKST -0000000 ST.6 ST.5 ST.4 ST.3 ST.2 ST.1...
  • Page 21 SH79F9461 SFR Map Bank0 Non Bit addressable addressable SPSTA CRCDL CRCDH IB_OFFSET IB_DATA CRCCON TWITOUT AUXC IB_CON1 IB_CON2 IB_CON3 IB_CON4 IB_CON5 XPAGE EXF0 P0PCR P1PCR P2PCR P3PCR P4PCR UTOS ELEDCON P0CR P1CR P2CR P3CR P4CR LCDSEG0 LCDSEG1 EXF1 PWM0CON PWM0PL PWM0PH PWM0DL PWM0DH...
  • Page 22: Normal Function

    SH79F9461 8. Normal Function 8.1 CPU 8.1.1 CPU Core Special Function Register Feature ◼ CPU core registers: ACC, B, PSW, SP, DPL, DPH Accumulator ACC is the Accumulator register. The mnemonics for accumulator-specific instructions, however, refer to the Accumulator simply as A. B Register The B register is used during multiply and divide operations.
  • Page 23: Enhanced Cpu Core Sfrs

    After reset, the CPU is in standard mode, which means that the 'MUL' and 'DIV' instructions are operating like the standard 8051 instructions. To enable the 16 bits mode operation, the corresponding enable bit in the INSCON register must be set.
  • Page 24: Random Access Data Memory (Ram)

    SH79F9461 8.2 Random access data memory (RAM) 8.2.1 Feature SH79F9461 provides both internal RAM and external RAM for random data storage. The internal data memory is mapped into four separated segments: ◼ The Lower 128 bytes of RAM (addresses 00H to 7FH) are directly and indirectly addressable. ◼...
  • Page 25: Flash Program Memory

    SH79F9461 8.3 Flash Program Memory 8.3.1 Features ◼ The program memory consists 128 X 512Byte sectors, total 64KB ◼ EEPROM like memory 0 - 4KB (code option) ◼ Programming and erasing can be done over the full operation voltage range ◼...
  • Page 26 SH79F9461 (2) Mass Erase Regardless of the state of the code protection control mode, the overall erasure operation will erase all programs, code options, the code protection bit, but they will not erase EEPROM-like memory block. The user must use the following way to complete the overall erasure: Flash programmer in ICP mode send overall erasure instruction to run overall erasure.
  • Page 27: Flash Operation In Icp Mode

    SH79F9461 8.3.2 Flash Operation in ICP Mode Single Line Simulation model ICP mode is performed without removing the micro-controller from the system. In ICP mode, the user system must be power-off, and the programmer can refresh the program memory through ICP programming interface. The ICP programming interface consists of 3 pins (VDD, GND, SWE).
  • Page 28: Ssp Function

    SH79F9461 8.4 SSP Function The SH79F9461 provides SSP (Self Sector Programming) function, each sector can be sector erased or programmed by the user’s code if the selected sector is not be protected. But once sector has been programmed, it cannot be reprogrammed before sector erase.
  • Page 29 SH79F9461 Table 8.7 Data Register for Programming FCH, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IB_DATA IB_DATA.7 IB_DATA.6 IB_DATA.5 IB_DATA.4 IB_DATA.3 IB_DATA.2 IB_DATA.1 IB_DATA.0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description IB_DATA[7:0] Data to be programmed Table 8.8 SSP Type select Register F2H, Bank0 Bit7 Bit6...
  • Page 30 SH79F9461 Table 8.11 SSP Flow Control Register3 F5H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IB_CON4 IB_CON4.3 IB_CON4.2 IB_CON4.1 IB_CON4.0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description IB_CON4[3:0] Must be 09H, else Flash Programming will terminate Table 8.12 SSP Flow Control Register4 F6H, Bank0 Bit7 Bit6...
  • Page 31: Flash Control Flow

    SH79F9461 8.4.2 Flash Control Flow Set IB_OFFSET Set XPAGE Set IB_DATA Set IB_CON1 IB_CON2[3:0]≠5H Set IB_CON2[3:0]=5H IB_CON2≠5H IB_CON3≠AH IB_CON2≠5H Set IB_CON3=AH ELSE IB_CON3≠AH Set IB_CON4=9H IB_CON4≠9H Reset IB_CON1-5 Set IB_CON5=6H Sector Erase IB_CON1=E6H &IB_CON2[3:0]=5H &IB_CON3=AH &IB_CON4=9H &IB_CON5=6H IB_CON1=6EH &IB_CON2[3:0]=5H &IB_CON3=AH &IB_CON4=9H &IB_CON5=6H Programming...
  • Page 32: Ssp Programming Note

    SH79F9461 8.4.3 SSP Programming Note To successfully complete SSP programming, the user’s software must following the steps below: (1) For Code/Data Programming 1. Disable interrupt; 2. Fill in the XPAGE, IB_OFFSET for the corresponding address; 3. Fill in IB_DATA if programming is wanted; 4.
  • Page 33: System Clock And Oscillator

    SH79F9461 8.5 System Clock and Oscillator 8.5.1 Features ◼ Six oscillator types: 32.768kHz crystal, crystal oscillator, ceramic oscillator, 24MHz/128K internal RC and External Clock ◼ Two Oscillator pin(XTAL1, XTAL2) ◼ Built-in 24MHz/128KHz Internal RC ◼ Built-in 32.768kHz speed up circuit ◼...
  • Page 34: Registers

    SH79F9461 8.5.4 Registers Table 8.14 System Clock Control Register B2H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CLKCON 32k_SPDUP CLKS1 CLKS0 SCMIF HFON Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description 32.768kHz oscillator speed up mode control bit 0: 32.768kHz oscillator normal mode, cleared by software.
  • Page 35: Oscillator Type

    SH79F9461 8.5.5 Oscillator Type (1) OP_OSC = 0000, 0011: internal 24M/128K RC, XTAL shared with IO. XTAL1 XTAL2 (2) OP_OSC = 1010: 32.768kHz Crystal Oscillator from XTAL input, internal 24M RC Oscillator can be enabled. XTAL1 32.768kHz XTAL2 (3) OP_OSC = 1110: 2M- 16M Crystal/Ceramic Oscillator input from XTAL. XTAL1 Crystal/ Ceramic...
  • Page 36: Capacitor Selection For Oscillator

    SH79F9461 8.5.6 Capacitor Selection for Oscillator Ceramitor Oscillator Remarks Frequency 2MHz 25 - 30pF 25 - 30pF no bulit-in ceramic resonator load capacitance 25 - 30pF 25 - 30pF 4MHz 12 - 15pF 12 - 15pF Different parameters under model 15pF 15pF 25 - 30pF...
  • Page 37: System Clock Monitor (Scm)

    SH79F9461 8.6 System Clock Monitor (SCM) In order to enhance the system reliability, SH79F9461 contains a system clock monitor (SCM) module. If the system clock fails (for example the oscillator stops oscillating), the built-in SCM will switch the OSCSCLK to the internal clock and set system clock monitor bit (SCMIF) to 1.
  • Page 38: I/O Port

    SH79F9461 8.7 I/O Port 8.7.1 Features ◼ 46/42 bi-directional I/O ports ◼ Share with alternative functions The SH79F9461 has 46/42 bi-directional I/O ports. The PORT data is put in Px register. The PORT control register (PxCRy) controls the PORT as input or output. Each I/O port has an internal pull-high resistor, which is controlled by PxPCRy when the PORT is used as input (x = 0-5, y = 0-7).
  • Page 39 SH79F9461 Table 8.18 Port Data Register 80H - C0H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P0 (80H, Bank0) P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 P1 (90H, Bank0) P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 P2 (A0H, Bank0) P2.7 P2.6 P2.5...
  • Page 40: Port Diagram

    SH79F9461 8.7.3 Port Diagram SFEN PxPCRy Output Mode Input Mode 0 = ON (Pull-up) PxCRy 1 = OFF I/O Pad Write Data Data Bus Register Read Port Data Register Read Read Data Register/Pad Selection 0: From Pad 1: From data register 0 = OFF 1 = ON Second...
  • Page 41: Port Share

    SH79F9461 8.7.4 Port Share The 46 bi-directional I/O ports can also share second or third special function. But the share priority should obey the Outer Most Inner Lest rule: The out most pin function in Pin Configuration has the highest priority, and the inner most pin function has the lowest priority. This means when one pin is occupied by a higher priority function (if enabled), it cannot be used as the lower priority functional pin, even the lower priority function is also enabled.
  • Page 42 SH79F9461 PORT1: - TK1-TK8: Touch Key Channels (P1.0-P1.7) - LED SEG 1-8 (P1.0-P1.7) - LCD SEG 1-8 (P1.0-P1.7) - INT44-INT47 (P1.0-P1.3): external interrupt4 Table 8.21 PORT1 Share function Table Pin No. Priority Function Enable bit TQFP48 LQFP44 TK1-4 Set P1SS.0-3 bit in P1SS register LED S1-4 Set seg1- 4 bit in SEG01, and MODSW = 0, set LEDON bit LCD SEG1-4...
  • Page 43 SH79F9461 (continue) LED_SEG11 Set seg11 bit in SEG02, and MODSW = 0, set LEDON bit Set SPEN bit in SPSTA register in slave mode MOSI (when set SPEN, CPHA, SSDIS bit in slave mode, auto pull up) LCD_SEG11 Set P2S2 bit in LCDSEG2 register, at the same time set LCDON bit P2.2 Above condition is not met LED_SEG12...
  • Page 44 SH79F9461 PORT3: - LED COM1-COM8 (P3.0-P3.7) - LCD COM1-COM8 (P3.0-P3.7) - AN4-AN7:ADC channel (P3.4-P3.7) - LCD SEG25-SEG28 (P3.4-P3.7) Table 8.23 PORT3 share function table Pin No. Priority Function Enable bit TQFP48 LQFP44 Set LPDEN and LPDV bit in LPDCON register Set CH7 bit in ADCH1 register and set ADON bit in ADCON register, and set SEQCHX[3:0] corresponding bit LED_C8...
  • Page 45 SH79F9461 (continue) TK22 Set P4SS.3 bit in P4SS register Set CH3 bit in ADCH2 register and set ADON bit in ADCON register, and set SEQCHX[3:0] corresponding bit INT43 Set EX4 bit in IEN1 register and set EXS43 bit in IENC register, P4.3 as input port P4.3 Above condition is not met TK23...
  • Page 46: Timer

    SH79F9461 8.8 Timer 8.8.1 Timer3 Timer3 is a 16-bit auto-reload timer. It is implemented as a 16-bit register accessed as two cascaded Data Registers: TH3 and TL3. It is controlled by the T3CON register. The Timer3 interrupt can be enabled by setting ET3 bit in IEN0 register (Refer to Interrupt Section for details).
  • Page 47 SH79F9461 Registers Table 8.26 Timer3 Control Register 88H, Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 T3CON T3PS.1 T3PS.0 T3CLKS.1 T3CLKS.0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Timer3 overflow flag bit 0: No overflow (cleared by hardware) 1: Overflow (Set by hardware) Timer3 input clock Prescaler Select bits 00: 1/1...
  • Page 48: Timer4

    SH79F9461 8.8.2 Timer4 Timer4 is a 16-bit auto-reload timer. It is accessed as two cascaded data registers: TH4 and TL4. It is controlled by the T4CON register. The Timer 4 interrupt can be enabled by setting ET4 bit in IEN1 register (Refer to interrupt Section for details). When writing to TH4 and TL4, they are used as timer load register.
  • Page 49 SH79F9461 Mode2: 16 bit Auto-Reload Timer with T4 Edge Trig Timer4 operates as 16-bit timer in Mode2.Timer4 can select system clock as clock source. Other setting accords with mode 0. In Mode2, After Setting the TR4 bit (T4CON.1), Timer4 does not start counting but waits the trig signal (rising or falling edge controlled by T4M[1:0]) from T4.
  • Page 50 SH79F9461 Registers Table 8.28 Timer4 Control Register C8H, Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 T4CON T4PS1 T4PS0 T4M1 T4M0 T4CLKS Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Timer4 overflow flag bit 0: No overflow (cleared by hardware) 1: Overflow (Set by hardware) Compare function Enable bit When T4M[1:0] = 00...
  • Page 51: Timer5

    SH79F9461 8.8.3 Timer5 Timer5 is a 16-bit auto-reload timer. It is accessed as two cascaded data registers: TH5 and TL5. It is controlled by the T5CON register. The interrupt can be enabled by setting ET5 bit in IEN0 register (Refer to interrupt Section for details). When writing to TH5 and TL5, they are used as timer load register.
  • Page 52 SH79F9461 Registers Table 8.30 Timer5 Control Register C0H, Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 T5CON T5PS1 T5PS0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Timer5 overflow flag bit 0: No overflow (cleared by hardware) 1: Overflow (Set by hardware) Timer5 input clock Prescaler Select bits 00: 1/1 T5PS[1:0]...
  • Page 53: Programmable Counter Array (Pca0)

    The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU intervention than the standard 8051 counter/timers. The PCA0 consists of a dedicated 16-bit counter/timer and two 16-bit capture/compare modules. The PCA0 block diagram is shown in Figure 8.9-1, Each capture/compare module has its own associated I/O line (P0CEXn (n = 0, 1).
  • Page 54 SH79F9461 The 16-bit PCA0 counter/timer consists of a 16-bit SFRs, PxTOPH and PxTOPL.consist of the 16-bit counter/timer. PxTOPH and PxTOPL can be configured TOP value, initial value of PxTOPH and PxTOPL is 0XFFFF. 16 bit counter/timer is the most basic module of PCA0, Enable or disable bit PRX of PCACON register can Start or Stop counter, when PR0 is set to logic '0', 16 bit counter was also forced the clear '0'.
  • Page 55 SH79F9461 Working mode selection is show in the following table: PCAx Mode Select Table Mode P0SDEN P0SMPn P0SMNn P0FSPn P0FSNn Function Capture triggered by positive edge (single slope) Mode0 Capture triggered by negative edge on (single slope) Capture triggered by transition (single slope) Continuous software timer (single slope) Mode1 Single software timer (single slope)
  • Page 56: Mode0:Edge-Triggered Capture Mode

    SH79F9461 8.9.2 Mode0:Edge-triggered Capture Mode In this mode, a valid transition on the P0CEXn pin causes the PCA0 to capture the value of the PCA counter/timer and load it into the corresponding module's 16-bit capture/compare register (P0CPLn and P0CPHn). The P0FSPn and P0FSNn bits in thePCA0CPMn register are used to select the type of transition that triggers the capture: low-to-high transition (positive edge trigger P0FSPn:P0FSNn = 0X), high-to-low transition (negative edge trigger P0FSPn:P0FSNn = 10), or either transition (positive or negative edge trigger P0FSPn:P0FSNn = 11).
  • Page 57: Mode1: Software Timer Mode

    SH79F9461 8.9.3 Mode1: Software Timer Mode In Software Timer mode (P0SMPn:P0SMNn = 01, P0FSPn:P0FSNn = 0x), the PCA counter/timer value is compared to the module's 16-bit capture/compare register (P0CPHn and P0CPLn). When a match occurs, the Capture/Compare Flag (P0CCFn) in PCA0CF is set to logic 1 and an interrupt request is generated if P0CCFn interrupts are enabled. When P0TCPn = 1, the state of P0CEXn port pin can be changed.The P0CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by software.
  • Page 58: Mode2: Frequency Output Mode

    SH79F9461 8.9.4 Mode2: Frequency Output Mode Frequency Output Mode produces a programmable-frequency square wave on the module’s associated P0CEXn pin. The capture/compare module high byte holds the number of PCA clocks to count before the output is toggled. The square wave frequency FP0CEXn = FPCA0/(2 X P0CPHn) Note: A value of 0x00 in the P0CPHn register is equal to 256 for this equation.
  • Page 59: Mode3: Pwm Mode

    SH79F9461 8.9.5 Mode3: PWM Mode Each PCA0 module can be used independently to generate a pulse width modulated (PWM) output. The following Table summarizes the bit (P0FSPn, P0FSNn) settings in the P0CPMn registers used to select the PCA capture/compare module’s operating PWM modes. PCA0 Function Select Table P0FSPn P0FSNn...
  • Page 60 SH79F9461 The duty cycle of the PWM output signal is varied using the module's P0CPHn capture/compare register. (in this mode, P0CPHn register is not double buffered) when P0TCPn = 0, When the value in the low byte of the PCA counter/timer (PL0) is equal to the value in P0CPLn, the output on the P0CEXn pin will be cleared.
  • Page 61 SH79F9461 DutyCycle = (65536-(P0CPn+1))/65536 The following Figure 8.9-11, the state of P0CEXn pin is default at the first time clock cycle. The state of P0CEXn pin at the first clock cycle for P0CPLn = 0. P0CEXn pin output pwm wave from second time clock cycle to fourth time clock for P0CPLn = 0001H, 8000H, FFFEH.
  • Page 62 SH79F9461 The dual-slope operation has lower maximum operation frequency than single slope operation.However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode can be configured by P0TOP. The minimum resolution allowed is 2-bit (P0TOP set to 0x003), and the maximum resolution is 16-bit.
  • Page 63 SH79F9461 The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The main difference between the phase correct, and the phase and frequency correct PWM mode is the time the P0TOP and P0CPn Register is updated by the P0TOP and P0CPn Buffer Register (see Figure 8.9-13 and Figure 8.9-15).
  • Page 64: Register

    SH79F9461 8.9.6 Register Table 8.32 PCA0 Flag Register 98H (Bank1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P0CF P0CCF1 P0CCF0 RESET Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description PCA0 Counter/Timer Overflow Flag Set by hardware when the PCA0 Counter/Timer overflows from 0xFFFF to 0x0000. When the Counter/Timer Overflow (CF0) interrupt is enabled, setting this bit causes the CPU to jump to the PCA interrupt service routine.
  • Page 65 SH79F9461 Table 8.35 P0CPMn: PCA Capturre/Compare Register 9AH - 9BH, Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P0CPM0 P0SMP0 P0SMN0 P0FSP0 P0FSN0 P0ECOM0 P0TCP0 P0MAT0 P0ECCF0 P0CPM1 P0SMP1 P0SMN1 P0FSP1 P0FSN1 P0ECOM1 P0TCP1 P0MAT1 P0ECCF1 RESET Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description...
  • Page 66 SH79F9461 Table 8.36 P0FORCE Forced Output Control Register DCH, Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P0FORCE P0OSC1 P0OSC0 P0FCO1 P0FCO0 RESET Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description P0CEX1 output registers of Module1, the bit is effective only when the P0SMPn:P0SMNn = 01 and P0FSPn:P0FSNn = 1x Write '0' to this bit, P0CEX1 pin output high level, when the compare match, P0OSC1...
  • Page 67 SH79F9461 Table 8.38 PCA0 Count Maximum High Byte 9FH, Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P0TOPH P0TOPH.7 P0TOPH.6 P0TOPH.5 P0TOPH.4 P0TOPH.3 P0TOPH.2 P0TOPH.1 P0TOPH.0 RESET Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description P0TOPH.y P0TOPH: PCA0 TOP defines high byte (MSB) (y = 0-7) Table 8.39 PCA0 Capture/Compare Module Low Byte Bank1...
  • Page 68: Interrupt

    SH79F9461 8.10 Interrupt 8.10.1 Features ◼ 22 interrupt sources ◼ 4 interrupt priority levels The SH79F9461 provides total 22 interrupt sources: 5 External interrupts (External interrupt0/1/2/3/40-47), 3 timer interrupts (Timer3-5), 1 PCA0 interrupts, 3 EUART interrupts, SCM interrupt, SPI interrupt, ADC interrupt, 2 PWM interrupts, Touch Key interrupt and LED interrupt, 1 TWI interrupt, 1 CRC interrupt, 1 LPD interrupt.
  • Page 69 SH79F9461 Table 8.42 Interrupt Enable Register1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IEN1 ESCM ELPD ELED ETWI Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description SCM interrupt enable bit ESCM 0: Disable SCM interrupt 1: Enable SCM interrupt LPD interrupt enable bit ELPD 0: Disable LPD interrupt...
  • Page 70 SH79F9461 Table 8.43 Interrupt Enable Register2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IEN2 EPWM1 EPCA0 ESPI EPWM0 ECRC Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description PWM1 interrupt enable bit EPWM1 0: Disable PWM1 interrupt 1: Enable PWM1 interrupt PCA0 interrupt enable bit EPCA0 0: Disable PCA0 interrupt...
  • Page 71: Interrupt Flag

    SH79F9461 8.10.3 Interrupt Flag Each Interrupt source has its own interrupt flag, when interrupt occurs, corresponding flag will be set by hardware, the interrupt flag bits are listed in Table bellow. For external interrupt (INT0/1), when an external interrupt0/1 is generated, if the interrupt was edge trigged, the flag(IE0/1 in EXF0)that generated this interrupt is cleared by hardware when the service routine is vectored.
  • Page 72 SH79F9461 Table 8.47 External Interrupt Control Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EXF0 IT4.1 IT4.0 IT3.1 IT3.0 IT2.1 IT2.0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description External interrupt4 trigger mode selection bits 00: Low Level trigger 01: Trigger on falling edge IT4[1:0] 10: Trigger on rising edge...
  • Page 73: Interrupt Vector

    SH79F9461 8.10.4 Interrupt Vector When an interrupt occurs, the program counter is pushed onto the stack and the corresponding interrupt vector address is loaded into the program counter. The interrupt vector addresses are listed in Interrupt Summary table. 8.10.5 Interrupt Priority Each interrupt source can be individually programmed to one of four priority levels by setting or clearing corresponding bits in the interrupt priority control registers IPL0, IPH0, IPL1, and IPH1.
  • Page 74: Interrupt Handling

    SH79F9461 8.10.6 Interrupt Handling The interrupt flags are sampled and polled at the fetch period of each machine period. All interrupts are sampled at the rising edge of the clock. If one of the flags was set, the CPU will find it and the interrupt system will generate a LCALL to the appropriate service routine, provided this hardware-generated LCALL is not blocked by any of the following conditions: An interrupt of equal or higher priority is already in progress.
  • Page 75: External Interrupt Input

    SH79F9461 8.10.8 External Interrupt Input The SH79F9461 has 5 external interrupt inputs. External interrupt0-3 every has one vector address. External interrupt 4 has 8 inputs, all of them share one vector address. External interrupt0-1 can be programmed to be level-triggered or edge-triggered by clearing or setting bit IT0 or IT1 in register TCON.
  • Page 76 SH79F9461 Table 8.50 External Interrupt Sample Times Rontrol Registrer 8BH, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EXCON I1PS1 I1PS0 I1SN1 I1SN0 I0PS1 I0PS0 I0SN1 I0SN0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description INT4 sample clock Prescaler Select bits 00: 1/1 I1PS[1:0] 01: 1/4...
  • Page 77: Interrupt Summary

    SH79F9461 8.10.9 Interrupt Summary Vector Interrupt No. Source Enable bits Flag bits Polling Priority Address (C51) Reset 0000H 0 (highest) INT0 0003H 000BH IFERR+IFGO+IFAVE+IFCOUNT INT1 0013H Timer5 001BH EUART0 0023H RI+TI Timer3 002BH 0033H EADC ADCIF/ADGIF/ADLIF 003BH ETWI TWINT 0043H ELED LEDIF+COMIF Timer4...
  • Page 78: Enhanced Function

    SH79F9461 9. Enhanced Function 9.1 Touch Key Function TKU1 Key1 Key2 Key3 Key4 Key5 Key6 Key7 OPInput Key8 VREF[0:1] VTK[0:1] Key9 Key10 Key11 Touch Key Key12 Logic Circuit D15-D0 Data Output Key13 Key14 Key15 Key16 Key17 10nF~100nF Key18 Key19 Key20 Key21 Key22 Key23...
  • Page 79 SH79F9461 There are four kinds of touch buttons will produce the interrupt flag, in which the 1th-4th will be interrupted, need to judge the interrupt flag bit after the implementation of interrupt subroutine: (1) After the end of the scan button, if the result of the operation is high, the interrupt flag bit IFERR is set to 1. If it is a multi - sampling, the system will stop the current sampling status and wait for the next restart, and do not perform the sampling.
  • Page 80 SH79F9461 Operating Flow: START TKCON = 1 CHOSE CHANNELS REGISTER: TKU1-TKU3 FUNCTION REGISTER: VREF[0:1] ,VTK[0:1] ,CMPD[0:1] ,VTK[0:1] ,RANDOM [0:1] ,TKST[0:7],FSW[0:1],TKRANDOM[0:7] 28Bit AMPLIFICATION FACTOR REGISTER: TKDIV01-TKDIV04 DELAY 10uS TKGO=1 WATING FOR THE TOUCH-KEY INTERRUPT PRODUCE OR SCANNING TKIF. TOUCH KEY INTERRUPT IFAVE=1 IFERR=1 IFGO=1...
  • Page 81: Register

    SH79F9461 9.1.1 Register Table 9.1 Touch Key Functional Control Register C1H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TKGO TKCON1 TKCON DATACON MODE FSW1 FSW0 ---- ---- ---- ---- RESET Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Touch Key Enable bit TKCON 0: Disable Touch Key Function 1: Enable Touch Key Function...
  • Page 82 SH79F9461 Table 9.3 Touch Key Frequency Random Setting Register C2H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TKRANDOM TKRADON TKOFFSET TKHYSW TKOSM RANDOM1 RANDOM0 RESET Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Touch Key Random Frequency Enable bit TKRADON 0: Disable Touch Key random frequency function 1: Enable Touch Key random frequency function...
  • Page 83 SH79F9461 Table 9.4 Touch Key Interrupt Flag Register (The register only can be cleared) C7H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TKF0 IFERR IFGO IFAVE IFCOUNT RESET Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Calculated Result Overflow Interrupt Flag bit 0: Calculated result high-bit don’t overflow IFERR 1: Calculated result high-bit overflow and generate interrupt...
  • Page 84 SH79F9461 Table 9.6 Port Function Control Register BCH-BFH, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P0SS (BCH) P0SS.6 P0SS.5 P0SS.4 P0SS.3 P0SS.2 P0SS.1 P0SS.0 P1SS (BDH) P1SS.7 P1SS.6 P1SS.5 P1SS.4 P1SS.3 P1SS.2 P1SS.1 P1SS.0 P4SS (BEH) P4SS.5 P4SS.4 P4SS.3 P4SS.2 P4SS.1...
  • Page 85 SH79F9461 Table 9.8 Reference Voltage Selection Register CEH, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TKVREF VREF1 VREF0 CMPD1 CMPD0 VTK1 VTK0 TUNE1 TUNE0 RESET Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Internal Reference Voltage Selection bit 00: V = 2.0V VREF[1:0] 01: V...
  • Page 86 SH79F9461 Table 9.9 Key Scan Sequence Register C9H-CBH, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TKU1 (C9H) TKU2 (CAH) TK16 TK15 TK14 TK13 TK12 TK11 TK10 TKU3 (CBH) TK24 TK23 TK22 TK21 TK20 TK19 TK18 TK17 RESET Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic...
  • Page 87 SH79F9461 (continue) 518H TK13L 519H TK13H 51AH TK14L 51BH TK14H 51CH TK15L 51DH TK15H 51EH TK16L 51FH TK16H 520H TK17L 521H TK17H 522H TK18L 523H TK18H 524H TK19L 525H TK19H 526H TK20L 527H TK20H 528H TK21L 529H TK21H 52AH TK22L 52BH TK22H 52CH...
  • Page 88: Lcd Driver

    SH79F9461 9.2 LCD Driver Normal Display Mode /Fast Charge Mode The LCD driver contains a controller, a duty cycle generator, 4/5/6/8 Common signal pins and 28 Segment driver pins. Segment and COM1-COM8 can also be used as I/O port, which is controlled by the LCDSEG0, LCDSEG1, LCDSEG2, LEDCOM register.
  • Page 89 SH79F9461 one frame COM4 COM1 COM3 COM2 COM2 COM1 COM3 COM4 SEGn+1 SEGn SEGn SEGn+1 COM4 - SEGn -Vcc LCD Waveform (1/4duty, 1/3bias)
  • Page 90 SH79F9461 COM8 COM1 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM2 COM3 COM4 SEGn SEGn COM1- SEGn - V1 - V2 - V3 LCD Waveform (1/8duty, 1/4bias)
  • Page 91: Register

    SH79F9461 9.2.1 Register Table 9.11 LCD Control Register A4H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LCDCON LCDON MODSW ELCC VOL3 VOL2 VOL1 VOL0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description LCD enable control bit LCDON 0: Disable LCD driver 1: Enable LCD driver LCD share selected bit 0: active LCD port control bit...
  • Page 92 SH79F9461 Table 9.12 LCD Control Register1 AEH, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DISPCON1 DUTY2 DUTY1 DUTY0 RLCD FCCTL1 FCCTL2 MOD1 MOD0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description LCD duty selected bits (control with DUTY0) 000: 1/4 Duty, 1/3 Bias (4 COM X 28 SEG) COM: COM1-4 SEG: SEG1-28 COM5-8 shared as SEG25-28...
  • Page 93 SH79F9461 Table 9.13 LCD Clock Control Register ADH, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DISPCLK0 DCK1 DCK0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description LCD clock frequency division selectiom bits 00: divided by 4 01: divided by 3 DCK[1:0] 10: divided by 2 11: divided by 1...
  • Page 94 SH79F9461 Table 9.15 P1 Mode Selection Register E7H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LCDSEG1 P1S7 P1S6 P1S5 P1S4 P1S3 P1S2 P1S1 P1S0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description P1 port mode selection bit (x = 0-7) P1S[7:0] 0: P1.0-P1.7 is I/O 1: P1.0-P1.7 is SEG (SEG1 - SEG8)
  • Page 95: Lcd Ram Configuration

    SH79F9461 9.2.2 LCD RAM Configuration LCD 1/4 duty, 1/3 bias (COM1 - 4, SEG1 - 28) Address COM4 COM3 COM2 COM1 530H SEG1 SEG1 SEG1 SEG1 531H SEG2 SEG2 SEG2 SEG2 532H SEG3 SEG3 SEG3 SEG3 533H SEG4 SEG4 SEG4 SEG4 534H SEG5...
  • Page 96 SH79F9461 LCD 1/8 duty, 1/4 bias (COM1 - 8, SEG1 - 24) Address COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 530H SEG1 SEG1 SEG1 SEG1 SEG1 SEG1 SEG1 SEG1 531H SEG2 SEG2 SEG2 SEG2 SEG2 SEG2 SEG2 SEG2 532H SEG3 SEG3 SEG3...
  • Page 97 SH79F9461 LCD 1/5 duty, 1/3 bias (COM1 - 5, SEG1 - 27) Address COM5 COM4 COM3 COM2 COM1 530H SEG1 SEG1 SEG1 SEG1 SEG1 531H SEG2 SEG2 SEG2 SEG2 SEG2 532H SEG3 SEG3 SEG3 SEG3 SEG3 533H SEG4 SEG4 SEG4 SEG4 SEG4 534H...
  • Page 98 SH79F9461 LCD 1/6 duty, 1/3 or 1/4 bias (COM1 - 6, SEG1 - 26) Address COM6 COM5 COM4 COM3 COM2 COM1 530H SEG1 SEG1 SEG1 SEG1 SEG1 SEG1 531H SEG2 SEG2 SEG2 SEG2 SEG2 SEG2 532H SEG3 SEG3 SEG3 SEG3 SEG3 SEG3 533H...
  • Page 99: Led Driver

    SH79F9461 9.3 LED Driver The LED driver contains a controller, 8 Common signal pins and 16 Segment driver pins.Support 1/1 - 1/8 duty voltage driving mode. The LED driver have two kind of operate mode. Mode 1: Light LED Mode When LED driver working under the light LED mode, each LEDRAM control a LED light, if LEDRAM bit is 0, LED light out;...
  • Page 100: Register

    SH79F9461 9.3.1 Register Table 9.18 LED Control Register D6H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDCON LEDON LEDMD MODE LEDIF COMIF MODSW Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description LED enable control bit LEDON 0: Disable LED driver 1: Enable LED driver LED interrupt operating mode control bit 0: when LEDIF = 1, LED keep scaning...
  • Page 101 SH79F9461 Table 9.20 LED Dead-time Width Control Register D7H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDDZ DZ.7 DZ.6 DZ.5 DZ.4 DZ.3 DZ.2 DZ.1 DZ.0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description LED dead-time width selection bits DZ[7:0] dead-time width = system clock width X LEDDZ Note: suggest to set the dead-time width more than 10 system clock width (LEDDZ >...
  • Page 102 SH79F9461 Mode2 example: is the width of single LED COM scan, T is the width of system clock, T is the width of LED scan time. X 256 X DISCOM S is the quantity of scan LED COM: scan 4COM: S = 4, scan 5COM: S = 5, and so on. For example, the LED frame rate which is needed to display is 200Hz (5ms), when LED is 5COM and the system clock selected internal RC 24MHz: X 256 X DISCOM...
  • Page 103 SH79F9461 Mode2 Dimming Diagram: COMIF=1 COMIF=1 COMIF=1 COMIF=1 COMIF=1 interrupt interrupt interrupt interrupt interrupt Initialization COM1 COM2 SEG0daty=0xFF SEG0daty=0x00 SEG0daty=0x00 SEG0daty=0x00 SEG0 SEG1daty=0x00 SEG1daty=0x00 SEG1 SEG1daty=0x00 SEG1daty=0x7F SEG2daty=0x00 SEG2daty=0xFF SEG2daty=0xFF SEG2 SEG2daty=0x00 SEG3daty=0x00 SEG3daty=0x00 SEG3daty=0x55 SEG3daty=0x00 SEG3 SEG4daty=0x00 SEG4daty=0xFF SEG4daty=0x00 SEG4daty=0xFF SEG4 SEG5daty=0x00...
  • Page 104 SH79F9461 LED RAM Mode1: Address 530H COM1 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 531H COM1 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 532H COM2 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 533H COM2 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11...
  • Page 105 SH79F9461 COM1 COM2 COM3 COM4 SEG1 SEG2 Note: t stand for the non-overlapping time between LED Common signals, its width configurated by LEDDZ (LEDDZ > 0AH). The hatched section of COM waveforms represent floating state.
  • Page 106: Bit Pulse Width Modulation (Pwm0/1)

    SH79F9461 9.4 12bit Pulse Width Modulation (PWM0/1) 9.4.1 Feature ◼ Two 12bit PWM modules ◼ Provided interrupt function on period overflow ◼ Selectable output polarity The SH79F9461 has two 12-bit PWM module. Which can provide two channel pulse width modulation waveform with the period and the duty being controlled individually by corresponding register.
  • Page 107 SH79F9461 (continue) PWMx pin output control bit 0: PWMx output disable, PWM0 as I/O Note: if this bit is 0 but PWMxEN = 1,the PWM timer can work normally, only can PWMxSS not output waveform, the PWMx still can be used as a timer. 1: PWMx output enable Note: if this bit is 1 but PWMxEN = 0, the PWMx output unselected level (selected high, output low;...
  • Page 108 SH79F9461 Table 9.26 PWM0 Duty Control Register PWM0DH/L DDH, DCH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWM0DH (DDH) PWM0D.11 PWM0D.10 PWM0D.9 PWM0D.8 PWM0DL (DCH) PWM0D.7 PWM0D.6 PWM0D.5 PWM0D.4 PWM0D.3 PWM0D.2 PWM0D.1 PWM0D.0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description PWM0 Duty control bits, control the duty output time of PWM0 1.
  • Page 109 SH79F9461 PWM clock t PWM output (PWMS=0) PWM output (PWMS=1) PWMP = F0H PWM output duty cycle = 7FH x t PWMD = 7FH PWM output period cycle = F0H x t PWM Output Example 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 01 02 PWMn clock t Write [PPn.11, PPn.0] = 0DH...
  • Page 110: Euart0/1/2

    ◼ The SH79F9461 has three enhanced EUART with own baud rate generator ◼ The baud rate generator is a 15-bit up-counter timer ◼ Enhancements over the standard 8051 the EUART include Framing Error detection and automatic address recognition ◼ EUARTx (x = 0, 1, 2) can be operated in four modes Notice: the subscript x stand for EUART number, for example, EUARTx (x = 0, 1, 2).
  • Page 111 SH79F9461 Any instruction that uses SBUFx as a destination register (“write to SBUFx” signal) will start the transmission. The next system clock tells the Tx control block to commence a transmission. The data shift occurs at the falling edge of the SHIFT CLOCK, and the contents of the transmit shift register is shifted one position to the right.
  • Page 112 SH79F9461 Transmission begins with a “write to SBUFx” signal, and it actually commences at the next system clock following the next rollover in the divide-by-16 counter (divide baud-rate by 16), thus, the bit times are synchronized to the divide-by-16 counter, not to the “write to SBUFx”...
  • Page 113 SH79F9461 Mode2: 9-Bit EUARTx, Fixed Baud Rate, Asynchronous Full-Duplex This mode provides the 11 bits full duplex asynchronous communication. The 11 bits consists of one start bit (logical 0), 8 data bits (LSB first), a programmable 9 data bit, and a stop bit (logical 1). Mode 2 supports multiprocessor communications and hardware address recognition (Refer to Multiprocessor Communication Section for details).
  • Page 114 SH79F9461 Reception is enabled only if RXDx is high. The serial port actually starts the receiving of serial data, with the detection of a falling edge on the RXDx pin. For this purpose RXDx is sampled at the rate of 16 times baud rate. When a falling edge is detected, the divide-by-16 counter is immediately reset.
  • Page 115: Baud Rate Generate

    SH79F9461 9.5.3 Baud Rate Generate EUARTx with own baud rate generator, the baud rate generator is an 15-bit up-counting timer. Overflow 15-bit timer To EUART Fsys From 7FFFH to 0000H SBRTEN=1 SBRTH[14:8],SBRTL7:0] Baudrate Generator for EUART The overflow rate of baud rate generator can be calculated as follow: Fsys SBRT = SBRTH...
  • Page 116: Multi-Processor Communication

    XXXXXXXX (all bits don’t care). This effectively removes the multiprocessor communications feature, since any selectivity is disabled. This ensures that the EUARTx will reply to any address, which it is backwards compatible with the 8051 microcontrollers that do not support automatic address recognition. So the user may implement multiprocessor by software...
  • Page 117: Error Detection

    SH79F9461 9.5.5 Error Detection Error detection is available when the SSTAT bit in register PCON is set to logic 1. All the 3 bits should be cleared by software after they are set, even when the following frames received without any error will not be cleared automatically. Note: The SSTAT bit must be logic 1 to access any of the status bits (FE, RXOV, and TXCOL).
  • Page 118 SH79F9461 Table 9.29 EUART0 Control and Status Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCON /RXOV /TXCOL Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description EUART0 Serial mode control bits, when SSTAT = 0 00: mode 0, Synchronous Mode, fixed baud rate SM[0:1] 01: mode 1, 8-bit Asynchronous Mode, variable baud rate 10: mode 2, 9-bit Asynchronous Mode, fixed baud rate...
  • Page 119 SH79F9461 Table 9.30 EUART0 Data Buffer Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SBUF SBUF.7 SBUF.6 SBUF.5 SBUF.4 SBUF.3 SBUF.2 SBUF.1 SBUF.0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description This SFR accesses two registers; a transmit shift register and a receive latch register SBUF[7:0] A write of SBUF will send the byte to the transmit shift register and then initiate a...
  • Page 120 SH79F9461 Table 9.34 EUART1 Control & Status Register A0H, Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SM11/ SM12/ SCON1 SM10/FE1 REN1 TB81 RB81 RXOV1 TXCOL1 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description EUART1 Serial mode control bits, when SSTAT = 0 00: mode 0, Synchronous Mode, fixed baud rate SM1 [0:1] 01: mode 1, 8-bit Asynchronous Mode, variable baud rate...
  • Page 121 SH79F9461 Table 9.35 EUART1 Serial Control Register A7H, Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PCON1 SMOD1 SSTAT1 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description EUART1 Baud rate doubler SMOD1 0: in Mode2, the baud-rate of EUART is 1/64 of the system clock 1: in Mode2, the baud-rate of EUART is 1/32 of the system clock SCON1[7:5] function select bit SSTAT1...
  • Page 122 SH79F9461 Table 9.38 EUART1 Baudrate Generator Register A5H-A4H, Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SBRTH1(A5H) SBRTEN1 SBRT1.14 SBRT1.13 SBRT1.12 SBRT1.11 SBRT1.10 SBRT1.9 SBRT1.8 SBRTL1 (A4H) SBRT1.7 SBRT1.6 SBRT1.5 SBRT1.4 SBRT1.3 SBRT1.2 SBRT1.1 SBRT1.0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description EUART1 Baudrate enable control bit...
  • Page 123 SH79F9461 (continue) bit ‘1’ checker), when EUART2 Multi-processor communication enable bit (9 SSTAT2 = 0 0: In Mode0, baud-rate is 1/12 of system clock In Mode1, disable stop bit validation check, any stop bit will set RI2 to generate interrupt SM22 In Mode2 &...
  • Page 124 SH79F9461 Table 9.42 EUART2 Data Buffer Register 91H, Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SBUF2 SBUF2.7 SBUF2.6 SBUF2.5 SBUF2.4 SBUF2.3 SBUF2.2 SBUF2.1 SBUF2.0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description This SFR accesses two registers; a transmit shift register and a receive latch register SBUF2 [7:0] A write of SBUF2 will send the byte to the transmit shift register and then initiate...
  • Page 125 SH79F9461 Table 9.45 EUART2 Baudrate Generator Fine-tune Register 96H, Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFINE2 SFINE2.3 SFINE2.2 SFINE2.1 SFINE2.0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description SFINE2 [3:0] EUART2 Baudrate generator fine-tune register Table 9.46 UART(2-0) Port Mode Selection Register EEH, Bank0 Bit7 Bit6...
  • Page 126: Twi Serial Interface (Twi)

    SH79F9461 9.6 TWI Serial Interface (TWI) 9.6.1 Feature ◼ Simple Two-wire Interface ◼ Support Both Master and Slave Mode ◼ Operates as Transmitter or Receiver ◼ Includes the capacity of Arbitration and the Possibility to have Multiple Masters On the Bus ◼...
  • Page 127 SH79F9461 START STOP START Repeated START STOP SH79F9461 generates an ACK by pulling the SDA line low. After the interrupt flag be set, SH79F9461 pulls the SCL line low,and releases SDA line.When the interrupt process has completed, SCL line should be released and TWINT flag should be cleared.
  • Page 128: Overview Of The Twi Module

    SH79F9461 Data Arbitration A master may start a transfer only if the bus is free. Two or more masters may generate a START condition within the minimum hold time (tHD;STA) of the START condition which results in a defined START condition to the bus. Arbitration takes place on the SDA line, while the SCL line is at the HIGH level, in such a way that the master which transmits a HIGH level, while another master is transmitting a LOW level will switch off its DATA output stage because the level on the bus doesn’t correspond to its own level.
  • Page 129: Transmission Modes

    SH79F9461 BUS Interface Unit This unit contains the Data and Address Shift Register (TWIDAT), a START/STOP Controller,and Arbitration and Bus Timeout detection hardware. The TWIDAT contains the address or data bytes to be transmitted,or the address or data bytes be received. The START/STOP Controller is responsible for generation and detection of START, REPEATED START, and STOP conditions.
  • Page 130 SH79F9461 Master Transmitter Mode In the Master Transmitter mode, a number of data bytes are transmitted to a Slave Receiver. In order to enter a Master mode, a START condition must be transmitted. The format of the following address packet determines whether Master Transmitter or Master Receiver mode is to be entered.
  • Page 131 SH79F9461 Master Transmitter Successfull transmission to a slave SLA+W DATA receiver Next transfer started with a repeated start SLA+W condition SLA+R Not acknowledge received Master Nack after the slave address Receiver Not acknowledge received Nack after a data byte Arbitration lost in slave Ack or Nack Ack or Nack address or data byte...
  • Page 132 SH79F9461 Master Receiver Mode In the Master Receiver mode, a number of data bytes are received from a Slave Transmitter. In order to enter a Master mode, a START condition mustbe transmitted. The format of the following address packet determines whether MasterTransmitter or Master Receiver mode is to be entered.
  • Page 133 SH79F9461 Master Receiver Successfull reception SLA+R DATA DATA Nack from a slave transmitter Next transfer started with a repeated start SLA+R condition SLA+W Master Not acknowledge received Nack after a data byte Transmitter Arbitration lost in slave Ack or address or not acknowledged Nack Other Master Other Master...
  • Page 134 SH79F9461 Slave Transmitter Mode Receiver To initiate the In the Slave Transmitter mode, a number of data bytes are transmitted to a Master Slave transmitter mode, TWICON register and TWIADR register must be initialized: set ENTWI bit and AA bit in TWICON register, clearing STA, STO and TWINT;...
  • Page 135 SH79F9461 Reception of the own SLA+R DATA DATA Nack P or S slave address and transmission of one or more data bytes Arbitration lost as master and addressed as slave transmitter Last data byte transmitted, Switched to not addressed All '1' P or S slave (AA = 0) Other Device Actions...
  • Page 136 SH79F9461 (continue) Arbitration lost in SLA + Receive data byte; Transmit NACK R/W as master; General No TWIDAT address has been action received; Receive data byte; Transmit ACK ACK has been received Previously addressed Receive data byte; Transmit NACK with own SLA address; Read data byte Data has been received;...
  • Page 137 SH79F9461 Reception of the own SLA+W DATA DATA P or S slave address and one or more data bytes, All are acknowledged Arbitration lost as master and addressed as slave receiver Last data byte received is Nack P or S not acknowledged Reception of general General...
  • Page 138: Register

    SH79F9461 9.6.5 Register Table 9.47 TWI Control Register C8H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TWICON TOUT ENTWI TWINT TFREE EFREE Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Bus Timeout Flag 0: No Timeout TOUT 1: Timeout happened when the periods of bus low level is more than N X T Then the bit will be set.
  • Page 139 SH79F9461 Table 9.48 Timeout For Bus Low level Count Register FEH, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TWITOUT CNT1 CNT0 TWIPCR Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Bus Timeout Count 00: N = 25000 01: N = 50000 CNT[1:0] 10: N = 100000 11: N = 200000...
  • Page 140 SH79F9461 Table 9.51 TWI Bit Rate Register 8AH, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TWIBR TWIBR.7 TWIBR.6 TWIBR.5 TWIBR.4 TWIBR.3 TWIBR.2 TWIBR.1 TWIBR.0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description TWIBR[7:0] Selects the division factor for the bit rate generator Table 9.52 TWI Address Register 8CH, Bank0 Bit7...
  • Page 141: Serial Peripheral Interface (Spi)

    SH79F9461 9.7 Serial Peripheral Interface (SPI) 9.7.1 Feature ◼ Full-duplex, three-wire synchronous transfers ◼ Master or slave operation ◼ Seven programmable master clock rates ◼ Serial clock with programmable polarity and phase ◼ Master mode fault error flag with MCU interrupt capability ◼...
  • Page 142: Baud Rate

    SH79F9461 9.7.3 Baud Rate In master mode, the baud rate is chosen from one of the seven clock rates by the division of the internal clock by 8, 16, 32, 64 , 128, 256 or 512 set by the three bits SPR[2:0] in the SPCON register. Note: SPR[2:0] = 000 is invalid.
  • Page 143: Operating Modes

    SH79F9461 9.7.5 Operating Modes The Serial Peripheral Interface can be configured as one of the two modes, master mode or slave mode. The configuration and initialization of the SPI module is made through SPCON (the serial peripheral control register) and SPSTA (the serial peripheral status register).
  • Page 144: Transmission Formats

    SH79F9461 9.7.6 Transmission Formats Software can select any of four combinations of serial clock (SCK) phase and polarity using two bits in the SPCON, the clock polarity CPOL and the clock phase CPHA. CPOL defines the default SCK line level in idle state. It has no significant effect on the transmission format.
  • Page 145: Error Detection

    SH79F9461 9.7.7 Error Detection The following flags in the SPSTA signal SPI error conditions: (1) Mode Fault (MODF) ——— Mode fault error in master mode SPI indicates that the level on the SS pin is inconsistent with the actual mode of the device. MODF is set to warn that there may be a multi-master conflict for system control.
  • Page 146: Registers

    SH79F9461 9.7.9 Registers Table 9.55 Serial Peripheral Control Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SPCON MSTR CPHA CPOL SSDIS SPR2 SPR1 SPR0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Transfer Direction Selection 0: MSB first 1: LSB first Serial Peripheral Master MSTR 0: Configure the SPI as a Slave...
  • Page 147 SH79F9461 Table 9.56 SPI Status Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SPSTA SPEN SPIF MODF WCOL RXOV Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description SPI Enable SPEN 0: Disable the SPI interface 1: Enable the SPI interface Serial Peripheral data transfer flag SPIF 0: Clear by software...
  • Page 148: Logic Configurable Module (Lcm)

    SH79F9461 9.8 Logic Configurable Module (LCM) 9.8.1 Features ◼ Though the Logic Configurable Module 12 kinds of Logic function port can be remap to I/O, and each function can choose one of the eight IO to map. The Logic Configurable Module (LCM) used to realize the remap of some logic function port, and keep the one-to-one match between logic and hardware.
  • Page 149 SH79F9461 Function UART0 UART1 PWM0 PWM1 PCA0 INT2 RXD0 TXD0 RXD1 TXD1 PWM0 PWM1 P0CEX0 P0CEX1 ECI0 INT2 ◼ ● ● ● ● P0.0 ● ◼ ● ● ● P0.1 ● ● ◼ P0.2 ● ● ● P0.3 ● P0.4 ●...
  • Page 150: Register

    SH79F9461 9.8.2 Register Table 9.58 TXD0 and RXD0 Selection Register E2H, Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 UART0CR TX0CR2 TX0CR1 TX0CR0 RX0CR2 RX0CR1 RX0CR0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description TXD0 Selection Bits 000: TXD0 map to P0.0 001: TXD0 map to P0.1 (Default) 010: TXD0 map to P0.2 TX0CR[2:0]...
  • Page 151 SH79F9461 Table 9.60 SCK and SDA Selection Register E5H, Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TWICR SCKCR2 SCKCR1 SCKCR0 SDACR2 SDACR1 SDACR0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description SCK Selection Bits 000: SCK map to P0.0 001: SCK map to P0.1 010: SCK map to P2.2 (Default) SCKCR[2:0]...
  • Page 152 SH79F9461 Table 9.62 P0CEX1 and P0CEX0 Selection Register E7H, Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CEXCR CE1CR2 CE1CR1 CE1CR0 CE0CR2 CE0CR1 CE0CR0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description P0CEX1 Selection Bits 000: P0CEX1 map to P0.0 001: P0CEX1 map to P0.1 010: P0CEX1 map to P0.5 (Default) CE1CR[2:0]...
  • Page 153: Analog Digital Converter (Adc)

    SH79F9461 9.9 Analog Digital Converter (ADC) 9.9.1 Feature ◼ 12-bit Resolution ◼ Reference voltage Selectable : external VREF or VDD ◼ Maximum 9 channels analog input. ◼ Start a conversion, the ADC can complete multi-channel conversion(Sequence), and each channel of the sequence can be configurated to any of the multiplexed input channels.
  • Page 154: Adc Diagram

    SH79F9461 9.9.2 ADC Diagram Software Trigger Event Trigger sequence mode SEQCH0 State pointer GRP[2:0] SEQCHn SEQCH7 Mode Arbiter ADD0L/H 12-Bits ADDnL/H ADD7L/H (1.20V) CH8/VREF ADC_Clk Time Gap Refc Logic Pre-Counter for ADC clock,4-bit ADCON1[REFC] SOC Stands for Start of Convertion System Clock EOC Stands for End of Convertion ADT[TADC]...
  • Page 155: Adc Register

    SH79F9461 9.9.3 ADC Register The registers of ADC moldule are as follows: Function Name Register Description ADC Clock Register Configuration of ADC clock, sample time Enable of ADC module, start a conversion, reference voltage selection, trigger ADCON1 mode and sources, interrupt flag ADC control Register The total number of a sequence and the time interval between neighbouring ADCON2...
  • Page 156 SH79F9461 For Example: System TADC[2:0] TS[3:0] Sample time Conversion time Clock 0000 0.083*1=0.083us 0000 2*0.083=0.166us 14*0.083+0.166=1.328us 0000 0.083*1=0.083us 0111 8*0.083=0.664us 14*0.083+0.664=1.826us 0000 0.083*1=0.083us 1111 15*0.083=1.245us 14*0.083+1.245=2.407us 12MHz 1111 0.083*192=15.936us 0000 2*15.936=31.872us 14*15.936+31.872=254.976us 1111 0.083*192=15.936us 0111 8*15.936=127.488us 14*15.936+127.488=350.592us 1111 0.083*192=15.936us 1111 15*15.936=239.04us 14*15.936+239.04=462.144us 0000...
  • Page 157 SH79F9461 (continue) TIMER4 Overflow Trigger Sequence Enable Bit TIMTRGEN 0: Disable this function 1: Enable Timer4 overflow trigger conversion ADC Status Flag bit 0: Automatically cleared by hardware when AD convert is completed. Clearing —---—-----— GO/DONE this bit during converting time will stop current conversion. 1: Set to start AD convert or digital compare.
  • Page 158 SH79F9461 Table 9.67 Map Control Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SEQCON REG2 REG1 REG0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description ADC result left & right aligned selection bit 0: The 12-bits result stored in result register ADDxL/H (x = 0 - 7) are stored in left aligned.
  • Page 159 SH79F9461 Table 9.69 ADC Channel Configure Register 2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADCH2 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Channel Configuration bit 1: P4.4 is ADC input port 0: P4.4 is I/O port Table 9.70 Channel Register x (x = 0 - 7) Bit7 Bit6 Bit5...
  • Page 160 SH79F9461 Right Alignment Mode: Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADDxL Reset Value (POR/WDT/LVR/PIN) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADDxH Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Left alignment mode (ALR = 0) After the conversion of a channel, the data updated immediately and stored in ADDxL/H(x = 0 - 7) High 8 bits are stored in ADDxH, the low 4 bits are stored in the high 4 bits in ADDxL register.
  • Page 161: Sequence Conversion Mode

    SH79F9461 9.9.4 Sequence Conversion Mode The ADC sequence consist of one or more channels, the conversion of sequence is to convert the channels in the sequence one by one. It makes multiple signals to convert at the same time become possible in hardware. (the minmum sampling gap between two channels is 1us,so it can be regard as at the same time approximately) The conversion result is stored in the corresponding result register ADDxL/H (x = 0 - 7), the result register is read only register.
  • Page 162 SH79F9461 GRP[2:0]=2 Result SEQCH0 =5 ADD0L/H SEQCH1= 2 ADD1L/H SEQCH2 = 8 ADD2L/H SEQCH3 = x ADD3L/H sequencer SEQCH6 = x ADD6L/H SEQCH7 = x ADD7L/H Figure 9.9-4 The Configuration of Gap Time Between Adjacent Channel During Sequence Conversion During sequence conversion, the time between last channel finished conversion and next channel start sampling can be set by TGAP bit in ADCON2 register.
  • Page 163: The Configuration Of Adc Conversion Time

    SH79F9461 9.9.5 The Configuration of ADC Conversion Time The ADC clock and sampling time can be set through ADT register. By setting the TADC[3:0] bits in the ADT can set the ADC clock. The TS[3:0] bits in the register ADT can be used to set the sampling time (t ) for each channel, t = (TS[3:0]+1) X t SAMP...
  • Page 164: Low Power Detect (Lpd)

    SH79F9461 9.10 Low Power Detect (LPD) 9.10.1 Feature ◼ An internal flag indicates low power is detected ◼ LPD detect voltage is selectable ◼ LPD include bilateral debounce, when the voltage decrease below the specified value, LPD occurs and generate an internal interrupt flag Low Power Detect( LPD) function is used to monitor the supply voltage and generate an internal flag if the voltage decrease below the specified value.
  • Page 165 SH79F9461 Table 9.73 LPD Voltage Selection Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LPDSEL LPDS3 LPDS2 LPDS1 LPDS0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description LPD Voltage Select Bit 0000: 2.4V 0001: 2.55V 0010: 2.7V 0011: 2.85V 0100: 3.00V 0101: 3.15V 0110: 3.30V...
  • Page 166: Low Voltage Reset (Lvr)

    SH79F9461 9.11 Low Voltage Reset (LVR) 9.11.1 Features ◼ Enabled by the code option and VLVR is 2.1V, 2.7V, 3.7V or 4.1V ◼ LVR de-bounce timer TLVR is about 30-60s ◼ An internal reset flag indicates low voltage reset generates The LVR function is used to monitor the supply voltage and generate an internal reset in the device when the supply voltage below the specified value VLVR.
  • Page 167: Watchdog Timer (Wdt), Ovl Reset And Reset State

    To enhance the anti-noise ability, SH79F9461 built in Program Counter (PC) over range detect circuit, if program counter value is larger than flash romsize, or detect operation code equal to A5H which is not exist in 8051 instruction set, a OVL reset will be generate to reset CPU, and set WDOF bit.
  • Page 168: Crc Verification Module

    SH79F9461 9.13 CRC verification module 9.13.1 Feature ◼ Generate CRC check code of the Flash Rom Code, verify the Flash Rom Code whether changed or not ◼ The check Flash ROM range and the initial value of CRC can be set ◼...
  • Page 169 SH79F9461 Table 9.76 CRC Result Register (Note: low bits address in front, high bits address in the post) F9H, FAH, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CRCDL (F9H) CRCD.7 CRCD.6 CRCD.5 CRCD.4 CRCD.3 CRCD.2 CRCD.1 CRCD.0 CRCDH (FAH) CRCD.15 CRCD.14 CRCD.13...
  • Page 170: Power Management

    SH79F9461 9.14 Power Management 9.14.1 Features ◼ Two power saving modes: Idle mode and Power-Down mode ◼ Two ways to exit Idle and Power-Down mode: interrupt and reset To reduce power consumption, SH79F9461 supplies two power saving modes: Idle mode and Power-Down mode. These two modes are controlled by PCON &...
  • Page 171: Register

    SH79F9461 9.14.4 Register Table 9.78 Power Control Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PCON SMOD SSTAT Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description SMOD EUART Baud rate doubler SSTAT SCON[7:5] function select bit GF[1:0] General purpose flags for software use Power-Down mode control bit 0: Cleared by hardware when an interrupt or reset occurs 1: Set by software to activate the Power-Down mode...
  • Page 172: Warm-Up Timer

    SH79F9461 9.15 Warm-up Timer 9.15.1 Featueres ◼ Built-in power on warm-up counter to eliminate unstable state of power on ◼ Built-in oscillator warm-up counter to eliminate unstable state when oscillation startup SH79F9461 has a built-in power warm-up counter; it is designed to eliminate unstable state after power on or to do some internal initial operation such as read customer option etc.
  • Page 173: Code Option

    SH79F9461 9.16 Code Option OP_WDT: 0: Disable WDT function (default) 1: Enable WDT function OP_WDTPD: 0: Disable WDT function in Power-Down mode (default) 1: Enable WDT function in Power-Down mode OP_RST: 0: enable pin reset (default) 1: select P5.2 as IO OP_WMT: (unavailable for 32kHz crystal and Internal RC) 00: longest warm up time (default) 01: longer warm up time...
  • Page 174 SH79F9461 OP_EEPROMSIZE: 0000: 8 X 512Bytes (default) 0001: 7 X 512Bytes 0010: 6 X 512Bytes 0011: 5 X 512Bytes 0100: 4 X 512Bytes 0101: 3 X 512Bytes 0110: 2 X 512Bytes 0111: 1 X 512Bytes 1000: 0 bytes Other: 0 bytes OP_MODSW: 0: LCD/LED Counter RUN, when MODSW set 1 (default) 1: LCD/LED Counter STOP and data is preserved, when MODSW set 0...
  • Page 175: Instruction Set

    SH79F9461 10. Instruction Set ARITHMETIC OPERATIONS Opcode Description Code Byte Cycle ADD A, Rn Add register to accumulator 0x28-0x2F ADD A, direct Add direct byte to accumulator 0x25 ADD A, @Ri Add indirect RAM to accumulator 0x26-0x27 ADD A, #data Add immediate data to accumulator 0x24 ADDC A, Rn...
  • Page 176 SH79F9461 LOGIC OPERATIONS Opcode Description Code Byte Cycle ANL A, Rn AND register to accumulator 0x58-0x5F ANL A, direct AND direct byte to accumulator 0x55 ANL A, @Ri AND indirect RAM to accumulator 0x56-0x57 ANL A, #data AND immediate data to accumulator 0x54 ANL direct, A AND accumulator to direct byte...
  • Page 177 SH79F9461 DATA TRANSFERS Opcode Description Code Byte Cycle MOV A, Rn Move register to accumulator 0xE8-0xEF MOV A, direct Move direct byte to accumulator 0xE5 MOV A, @Ri Move indirect RAM to accumulator 0xE6-0xE7 MOV A, #data Move immediate data to accumulator 0x74 MOV Rn, A Move accumulator to register...
  • Page 178 SH79F9461 PROGRAM BRANCHES Opcode Description Code Byte Cycle ACALL addr11 Absolute subroutine call 0x11-0xF1 LCALL addr16 Long subroutine call 0x12 Return from subroutine 0x22 RETI Return from interrupt 0x32 AJMP addr11 Absolute jump 0x01-0xE1 LJMP addr16 Long jump 0x02 SJMP rel Short jump (relative address) 0x80 JMP @A+DPTR...
  • Page 179 SH79F9461 BOOLEAN MANIPULATION Opcode Description Code Byte Cycle CLR C Clear carry flag 0xC3 CLR bit Clear direct bit 0xC2 SETB C Set carry flag 0xD3 SETB bit Set direct bit 0xD2 CPL C Complement carry flag 0xB3 CPL bit Complement direct bit 0xB2 ANL C, bit...
  • Page 180: Electrical Characteristics

    SH79F9461 11. Electrical Characteristics Absolute Maximum Rating* *Comments Stresses exceed those listed under “Absolute Maximum DC Supply Voltage....-0.3V to +6.0V Ratings” may cause permanent damage to this device. Input/Output Voltage.
  • Page 181 SH79F9461 (continue) ——-------—— , T3, T4, INT0/1/2/3/4, P0CEX0, ECI0, MISO, Input low Voltage2 0.2 X V MOSI, SCK, SS, RXD0, RXD1, RXD2, V = 2.0- 5.5V, UART TTL turn off ——-------—— , T3, T4, INT0/1/2/3/4, P0CEX0, ECI0, MISO, Input High Voltage2 0.8 X V MOSI, SCK, SS, RXD0, RXD1, RXD2, V = 2.0-...
  • Page 182 SH79F9461 A/D Converter Electrical Characteristics (The conversion rate of 1M SPS: 1LSB = V /4096 (V = 2.0 - 5.5V, GND = 0V, T = +25° C, unless otherwise specified) Parameter Symbol Min. Max. Unit Condition operating voltage range = 5.0V Resolution A/D input voltage A/D input resistance...
  • Page 183 SH79F9461 AC Electrical Characteristics (V =2.0 - 5.5V, GND = 0V, T = +25° C, f = 24MHz ,unless otherwise specified) Parameter Symbol Min. Max. Unit Condition = 32.768kHz Oscillator start time = 16MHz s RESET pulse width RESET WDT RC Frequency Internal RC |F - 24MHz|/24MHz = 2.0 - 5.5V, T...
  • Page 184: Ordering Information

    SH79F9461 12. Ordering Information Part No. Package SH79F9461P/044PR LQFP44 SH79F9461U/048UR TQFP48...
  • Page 185: Product Naming Rules

    048: Package pins is 48 044: Package pins is 44 /: Divider U: TQFP package P: LQFP package 61: Product serial number 4: Product flash size 64K bytes 9: Appliance MCU F: flash product 79: 8051 core SH: Sinowealth Electronics...
  • Page 186: Package Information

    SH79F9461 14. Package Information TQFP 48L Outline Dimensions unit: inches/mm 2 See Detail F DETAIL F Dimensions in inches Dimensions in mm Symbol 0.047 0.002 0.006 0.05 0.15 0.035 0.041 1.05 0.270 0.281 6.85 7.15 0.270 0.281 6.85 7.15 0.346 0.362 0.346 0.362...
  • Page 187 SH79F9461 LQFP 44L Outline Dimensions unit: inches/mm 2 See Detail F DETAIL F Seating Plane Dimensions in inches Dimensions in mm Symbol 0.057 0.065 1.45 1.65 0.000 0.001 0.01 0.21 0.051 0.059 0.388 0.400 9.85 10.15 0.388 0.400 9.85 10.15 0.465 0.480 11.8...
  • Page 188: Product Spec.change Notice

    SH79F9461 15. Product SPEC.Change Notice Version Content Data Original Nov. 2023...
  • Page 189 SH79F9461 IMPORTANT NOTICE This manual is the property of Sino Wealth Electronic Ltd. and its affiliates ("Company"). This manual, including all of the Company's products ("Products") described herein, is owned by the Company according to relevant laws or treaties. The Company reserves all rights under such laws and treaties, and does not grant you any license to use its patents, copyrights, trademarks and other intellectual property rights.
  • Page 190: Table Of Contents

    SH79F9461 Content FEATURES ...................................... 1 GENERAL DESCRIPTION ................................1 BLOCK DIAGRAM ..................................2 PIN CONFIGRATION ................................... 3 4.1 TQFP48 P ....................................3 ACKAGE 4.2 LQFP44 P ....................................4 ACKAGE PIN FUNCTION AND PIN DESCRIPTION ..........................6 PRODUCT INFORMATION ................................. 8 SFR MAPPING....................................
  • Page 191 SH79F9461 8.10.4 Interrupt Vector ..................................73 8.10.5 Interrupt Priority ..................................73 8.10.6 Interrupt Handling ..................................74 8.10.7 Interrupt Response Timing ................................ 74 8.10.8 External Interrupt Input ................................75 8.10.9 Interrupt Summary ..................................77 ENHANCED FUNCTION ................................78 9.1 T ..................................78 OUCH UNCTION 9.1.1 Register .......................................
  • Page 192 SH79F9461 9.12.2 Registers ....................................167 9.13 CRC ................................168 VERIFICATION MODULE 9.13.1 Feature ....................................168 9.13.2 Register ....................................168 9.14 P ..................................170 OWER ANAGEMENT 9.14.1 Features ....................................170 9.14.2 Idle Mode (Idle) ..................................170 9.14.3 Power-Down Mode (Power-Down) ............................170 9.14.4 Register ....................................

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