Sino Wealth SH79F1640A Manual

Enhanced 8051 microcontroller with 20 channels touch-key input and pwm
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Enhanced 8051 Microcontroller with 20 channels Touch-key input and PWM

1. Features

8 bits micro-controller with Pipe-line structured 8051
Flash ROM: 16K Bytes
RAM: internal 256 Bytes, external 4096 Bytes
EEPROM-Like: build-in 4096 Bytes(code option)
Operation Voltage:
- f
= 24MHz, V
= 2.7V - 5.5V
OSC
DD
Oscillator (code option):
- Internal RC oscillator: 24M/16MHz (± 1%)/128K
(± 10%)
26 bi-directional I/O pins
Built-in pull-up resistor for input pin (30kΩ)
Four large current driver I/O
20 channels touch key input
Two 16-bit timer T3 and T5, one 16-bit timer/counter T4
PCA0 containing two comparison/ capture modules
Two channels 12-bits PWM
TWI
Powerful interrupt sources:
- Timer3, 4, 5, PCA0
- INT0 - 3
- INT4: 8 input
- ADC, EUART, TouchKey
- PWM, CRC, TWI, LPD, LED

2. General Description

The SH79F1640A is a high performance 8051 compatible micro-controller. The SH79F1640A can perform more fast operation
speed and higher calculation performance, if compare SH79F1640A with standard 8051 at same clock speed.
The SH79F1640A retains most features of the standard 8051. These features include internal 256 bytes RAM, Two UART and
INT0, INT1, INT2, INT3, INT4. In addition, SH79F1640A provides external 4096 bytes RAM. It also contains 16K bytes Flash
memory block for program storage.
The SH79F1640A not only include many standard communication modules, such as EUART, TWI, and so on, but also include
dimming LED, 12bit ADC, PWM timer, etc.
In addition, the SH79F1640A also have Touch Key module, CRC module, Logic configurable module (LCM) built in it.
For high reliability and low cost issues, the SH79F1640A builds in Watchdog Timer, Low Voltage Reset function. And
SH79F1640A also supports two power saving modes to reduce power consumption.
DS000010E
Internal Logic Configuration Module (LCM)
Two Enhanced UART (EUART)
4 analog inputs 12-bit Analog Digital Converter
LED driver:
- 4 COM/8 SEG LED driver with dimming mode
Built-in Low Voltage Reset (LVR) function (code option):
- LVR Voltage1: 4.1V
- LVR Voltage2: 3.7V
- LVR Voltage3: 3.1V
Built-in CRC verification module, the verify size can be
selected
Low Power Detect (LPD) Module with 13 level optional
Support single line simulation and download
CPU Machine period:
- 1 oscillator clock
Built-in Watch Dog Timer (WDT)
Built-in oscillator Warm-up timer
Support Low power operation modes:
- Idle Mode
- Power-Down Mode
Flash Type
Package:
- SOP28
1
SH79F1640A
V1.0

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Summary of Contents for Sino Wealth SH79F1640A

  • Page 1: Features

    SH79F1640A with standard 8051 at same clock speed. The SH79F1640A retains most features of the standard 8051. These features include internal 256 bytes RAM, Two UART and INT0, INT1, INT2, INT3, INT4. In addition, SH79F1640A provides external 4096 bytes RAM. It also contains 16K bytes Flash memory block for program storage.
  • Page 2: Block Diagram

    SH79F1640A 3. Block Diagram Power Pipelined 8051 architecture Watch Dog 16K Bytes Flash ROM Internal 256 Bytes External 4096Bytes Port 5 (Exclude System Configuration I/Os Register) P5.0 ,P5.1 Port 4 Timer3 (16bit) Configuration I/Os Timer4 (16bit) P4.0 - P4.3 Timer5 (16bit)
  • Page 3: Pin Configration

    SH79F1640A 4. Pin Configration SOP28 Package TK15/P0.6 P0.5/INT1/TK14 C/INT3/P0.7 P0.4/INT0/TK13 P0.3/T4/TK12 TK16/P5.0 P0.2/TK11 TK17/P5.1 P0.1/TK10 P0.0/TK9 TK22/AN3/INT43/P4.3 P1.7/LED_S8/TK8 TK23/AN2/INT42/P4.2 P1.6/LED_S7/TK7 TK24/AN1/INT41/P4.1 P1.5/LED_S6/TK6 SWE/AN0/INT40/P4.0 P1.4/LED_S5/TK5 LED_C4/P3.3 P1.3/INT47/LED_S4/TK4/TCK LED_C3/P3.2 P1.2/INT46/LED_S3/TK3/TDI P1.1/INT45/LED_S2/TK2/TMS LED_C2/P3.1 LED_C1/P3.0 P1.0/INT44/LED_S1/TK1/TDO...
  • Page 4 SH79F1640A Function UART0 UART1 PWM0 PWM1 PCA0 INT2 RXD0 TXD0 RXD1 TXD1 PWM0 PWM1 P0CEX0 P0CEX1 ECI0 INT2 ◼ ● ● ● ● P0.0 ◼ ● ● ● ● P0.1 ◼ ● ● P0.2 ● ● ● P0.3 ● P0.4 ●...
  • Page 5: Pin Description

    SH79F1640A 5. Pin Description Pin No. Type Description I/O PORT P0.0 - P0.7 8-bit bi-directional I/O port P1.0 - P1.7 8-bit bi-directional I/O port P3.0 - P3.3 4-bit bi-directional I/O port P4.0 - P4.3 4-bit bi-directional I/O port P5.0 - P5.1...
  • Page 6 SH79F1640A (continue) Single simulation interface Single simulation interface, if the power on or down slope of VDD is greater than SWE (P4.0) 500ms/v, it is recommended to connect the 47K-1M resistor to GND or VDD to increase the stability of the chip.
  • Page 7: Product Information

    SH79F1640A 6. Product Information SH79F1640A: SOP28 Flash PCA0 Part Num EUARTx TouchK Timerx ExINT Package (byte) (byte) (byte) (12bit) (16bit) (12bit) SH79F1640A 4096 4096 4 X 8 3,4,5 ±0.5% SOP28...
  • Page 8: Sfr Mapping

    SH79F1640A 7. SFR Mapping SH79F1640A has 256-byte direct-addressing register, includes universal deat storage and special function register (SFR), The SFR of the SH79F1640A fall into the following categories: CPU Core Registers: ACC, B, PSW, SP, DPL, DPH Enhanced CPU Core Registers:...
  • Page 9 SH79F1640A Table 7.1 C51 Core SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset Value Accumulator 00000000 ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 B Register 00000000 AUXC C Register 00000000 Program Status Word 00000000...
  • Page 10 SH79F1640A Table 7.3 Flash control SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset Value IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF Offset Register for Programming 00000000 Bank0 SET.7 SET.6 SET.5 SET.4 SET.3 SET.2 SET.1...
  • Page 11 SH79F1640A Table 7.6 Interrupt SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset Value IEN0 Interrupt Enable Control 0 00000000 EADC Bank0 IEN1 Interrupt Enable Control 1 -0000000 ELPD ELED ETWI Bank0 IEN2 Interrupt Enable Control 2...
  • Page 12 SH79F1640A Table 7.8 Port SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset Value 8-bit Port0 00000000 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 Bank0 8-bit Port1 00000000 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0...
  • Page 13 SH79F1640A Table 7.9 Timer SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset Value T3CON Timer/Counter3 Control 0-00-000 T3PS.1 T3PS.0 T3CLKS.1 T3CLKS.0 Bank1 Timer/Counter3 Low Byte 00000000 TL3.7 TL3.6 TL3.5 TL3.4 TL3.3 TL3.2 TL3.1 TL3.0 Bank1...
  • Page 14 SH79F1640A (continue) PCA0 capture/compare module 0 P0CPH0 00000000 P0CPH0.7 P0CPH0.6 P0CPH0.5 P0CPH0.4 P0CPH0.3 P0CPH0.2 P0CPH0.1 P0CPH0.0 Bank1 high byte PCA0 capture/compare module 1 P0CPL1 00000000 P0CPL1.7 P0CPL1.6 P0CPL1.5 P0CPL1.4 P0CPL1.3 P0CPL1.2 P0CPL1.1 P0CPL1.0 Bank1 low byte PCA0 capture/compare module 1...
  • Page 15 SH79F1640A (continue) SADDR1 EUART1 Slave Address 00000000 SADDR1.7 SADDR1.6 SADDR1.5 SADDR1.4 SADDR1.3 SADDR1.2 SADDR1.1 SADDR1.0 Bank1 SBRTH1 EUART1 Baudrate Generator 00000000 SBRTEN SBRT1.14 SBRT1.13 SBRT1.12 SBRT1.11 SBRT1.10 SBRT1.9 SBRT1.8 Bank1 SBRTL1 EUART1 Baudrate Generator 00000000 SBRT1.7 SBRT1.6 SBRT1.5 SBRT1.4 SBRT1.3 SBRT1.2...
  • Page 16 SH79F1640A Table 7.13 LED SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset Value LEDCON LED Control register 00000--0 LEDON LEDMD MODE LEDIF COMIF MODSW Bank0 DISCOM COM scan width control register 00000000 DCOM.7 DCOM.6 DCOM.5 DCOM.4...
  • Page 17 SH79F1640A Table 7.15 LPD SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset Value LPDCON LPD Control register 00-00--- LPDEN LPDF LPDIF LPDMD Bank0 LPDSEL LPD level selection register ----0000 LPDS3 LPDS2 LPDS1 LPDS0 Bank0 Table 7.16 CRC SFRs...
  • Page 18 SH79F1640A (continue) Reference voltage source selection TKVREF 00000000 VREF1 VREF0 CMPD1 CMPD0 VTK1 VTK0 TUNE1 TUNE0 Bank0 Register Touch Key frequency TKST -0000000 ST.6 ST.5 ST.4 ST.3 ST.2 ST.1 ST.0 Bank0 selection Register Touch Key frequency TKRANDOM 000--000 TKRADON TKOFFSET...
  • Page 19 SH79F1640A SFR Map Bank0 Non Bit addressable addressable CRCDL CRCDH IB_OFFSET IB_DATA CRCCON TWITOUT AUXC IB_CON1 IB_CON2 IB_CON3 IB_CON4 IB_CON5 XPAGE EXF0 P0PCR P1PCR P3PCR P4PCR UTOS ELEDCON P0CR P1CR P3CR P4CR EXF1 PWM0CON PWM0PL PWM0PH PWM0DL PWM0DH TWISTA LEDST...
  • Page 20: Normal Function

    SH79F1640A 8. Normal Function 8.1 CPU 8.1.1 CPU Core Special Function Register Feature ◼ CPU core registers: ACC, B, PSW, SP, DPL, DPH Accumulator ACC is the Accumulator register. The mnemonics for accumulator-specific instructions, however, refer to the Accumulator simply as A.
  • Page 21: Enhanced Cpu Core Sfrs

    ◼ Dual Data Pointer ◼ Enhanced CPU core registers: AUXC, DPL1, DPH1, INSCON The SH79F1640A has modified 'MUL' and 'DIV' instructions. These instructions support 16 bits operand. A new register - the register is applied to hold the upper part of the operand/result.
  • Page 22: Random Access Data Memory(Ram

    256 bytes RAM; MOVX A, @DPTR or MOVX @DPTR, A also to access external 4096 bytes RAM. In SH79F1640A the user can also use XPAGE register to access external RAM only with MOVX A, @Ri or MOVX @Ri, A instructions.
  • Page 23: Flash Program Memory

    Flash memory supports the following operations: (1) Code-Protect Control mode Programming SH79F1640A implements code-protect function to offer high safeguard for customer code. Four modes are available for each sector. Code-protect control mode 0: Used to enable/disable the write/read operation (except mass erase) from any programmer.
  • Page 24 SH79F1640A (2) Mass Erase Regardless of the state of the code protection control mode, the overall erasure operation will erase all programs, code options, the code protection bit, but they will not erase EEPROM-like memory block. The user must use the following way to complete the overall erasure: Flash programmer in ICP mode send overall erasure instruction to run overall erasure.
  • Page 25: Flash Operation In Icp Mode

    SH79F1640A 8.3.2 Flash Operation in ICP Mode Single Line Simulation model ICP mode is performed without removing the micro-controller from the system. In ICP mode, the user system must be power-off, and the programmer can refresh the program memory through ICP programming interface. The ICP programming interface consists of 3 pins (VDD, GND, SWE).
  • Page 26: Ssp Function

    But once sector has been programmed, it cannot be reprogrammed before sector erase. The SH79F1640A builds in a complex control flow to prevent the code from carelessly modification. If the dedicated conditions are not met (IB_CON1-5), the SSP will be terminated.
  • Page 27 SH79F1640A Table 8.7 Data Register for Programming FCH, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IB_DATA IB_DATA.7 IB_DATA.6 IB_DATA.5 IB_DATA.4 IB_DATA.3 IB_DATA.2 IB_DATA.1 IB_DATA.0 Reset Value (POR/WDT/LVR) Bit Number Bit Mnemonic Description IB_DATA[7:0] Data to be programmed Table 8.8 SSP Type select Register...
  • Page 28 SH79F1640A Table 8.11 SSP Flow Control Register3 F5H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IB_CON4 IB_CON4.3 IB_CON4.2 IB_CON4.1 IB_CON4.0 Reset Value (POR/WDT/LVR) Bit Number Bit Mnemonic Description IB_CON4[3:0] Must be 09H, else Flash Programming will terminate Table 8.12 SSP Flow Control Register4...
  • Page 29: Flash Control Flow

    SH79F1640A 8.4.2 Flash Control Flow Set IB_OFFSET Set XPAGE Set IB_DATA Set IB_CON1 IB_CON2[3:0]≠5H Set IB_CON2[3:0]=5H IB_CON2≠5H IB_CON3≠AH IB_CON2≠5H Set IB_CON3=AH ELSE IB_CON3≠AH Set IB_CON4=9H IB_CON4≠9H Reset IB_CON1-5 Set IB_CON5=6H Sector Erase IB_CON1=E6H &IB_CON2[3:0]=5H &IB_CON3=AH &IB_CON4=9H &IB_CON5=6H IB_CON1=6EH &IB_CON2[3:0]=5H &IB_CON3=AH &IB_CON4=9H...
  • Page 30: Ssp Programming Note

    SH79F1640A 8.4.3 SSP Programming Note To successfully complete SSP programming, the user’s software must following the steps below: (1) For Code/Data Programming: 1. Disable interrupt; 2. Fill in the XPAGE, IB_OFFSET for the corresponding address; 3. Fill in IB_DATA if programming is wanted;...
  • Page 31: Readable Identificantion Code

    SH79F1640A 8.4.4 Readable Identificantion Code A 40-Bit readable identificantion code is burned in the chip after produced, Every byte is between 0 and 0xffffffffff. They can not be erased, and can be read by program and program tool. Reading the identificantion code program: Unsigned char Temp1, Temp2, Temp3, Temp4, Temp5;...
  • Page 32: System Clock And Oscillator

    SYSCLK frequency. t is defined as the SYSCLK period. 8.5.3 Description SH79F1640A has two oscillator types: internal RC (24MHz/16MHz,128KHz). The oscillator generates the basic clock pulse that provides the system clock to supply CPU and on-chip peripherals. CLKS[1:0] HFON,FS...
  • Page 33: Register

    SH79F1640A 8.5.4 Register Table 8.14 System Clock Control Register B2H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CLKCON CLKS1 CLKS0 HFON Reset Value (POR/WDT/LVR) Bit Number Bit Mnemonic Description SYSCLK Prescaler Register 00: f OSCS CLKS[1:0] 01: f...
  • Page 34: I/O Port

    ◼ Share with alternative functions The SH79F1640A has 26 bi-directional I/O ports. The PORT data is put in Px register. The PORT control register (PxCRy) controls the PORT as input or output. Each I/O port has an internal pull-high resistor, which is controlled by PxPCRy when the PORT is used as input (x = 0-5, y = 0-7).
  • Page 35 SH79F1640A Table 8.17 Port Data Register 80H - C0H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P0 (80H, Bank0) P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 P1 (90H, Bank0) P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 P3 (B0H, Bank0) P3.3...
  • Page 36: Port Diagram

    SH79F1640A 8.6.3 Port Diagram SFEN PxPCRy Output Mode Input Mode 0 = ON (Pull-up) PxCRy 1 = OFF I/O Pad Write Data Data Bus Register Read Port Data Register Read Read Data Register/Pad Selection 0: From Pad 1: From data register...
  • Page 37: Port Share

    SH79F1640A 8.6.4 Port Share The 46 bi-directional I/O ports can also share second or third special function. But the share priority should obey the Outer Most Inner Lest rule: The out most pin function in Pin Configuration has the highest priority, and the inner most pin function has the lowest priority.
  • Page 38 SH79F1640A PORT1: - TK1-TK8(P1.0-P1.7) - LED SEG 1-8(P1.0-P1.7) - INT44-INT47(P1.0-P1.3):external interrupt4 Table 8.20 PORT1 Share function Table Pin No. Priority Function Enable bit TK1-4 Set P1SS.0-3 bit in P1SS register LED S1-4 Set seg1- 4 bit in SEG01 15-18 Set EX4 bit in IEN1 register and set EXS44-47 bit in IENC register, P1.0-1.3 as...
  • Page 39 SH79F1640A PORT4: - INT40-INT43 (P4.0-P4.3): external interrupt4 - AN0-AN3 (P4.0-P4.3): ADC channel - TK22-TK24: Touch Key Channels (P4.1-P4.3) Table 8.22 PORT4 share function table Pin No. Priority Function Enable bit TK22 Set P4SS.3 bit in P4SS register Set CH3 bit in ADCH1 register and set ADON bit in ADCON register, and set...
  • Page 40: Timer

    SH79F1640A 8.7 Timer 8.7.1 Timer3 Timer3 is a 16-bit auto-reload timer. It is implemented as a 16-bit register accessed as two cascaded Data Registers: TH3 and TL3. It is controlled by the T3CON register. The Timer3 interrupt can be enabled by setting ET3 bit in IEN0 register (Refer to Interrupt Section for details).
  • Page 41 SH79F1640A Register Table 8.24 Timer3 Control Register 88H, Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 T3CON T3PS.1 T3PS.0 T3CLKS.1 T3CLKS.0 Reset Value (POR/WDT/LVR) Bit Number Bit Mnemonic Description Timer3 overflow flag bit 0: No overflow (cleared by hardware)
  • Page 42: Timer4

    SH79F1640A 8.7.2 Timer4 Timer4 is a 16-bit auto-reload timer. It is accessed as two cascaded data registers: TH4 and TL4. It is controlled by the T4CON register. The Timer 4 interrupt can be enabled by setting ET4 bit in IEN1 register (Refer to interrupt Section for details).
  • Page 43 SH79F1640A Mode2: 16 bit Auto-Reload Timer with T4 Edge Trig Timer4 operates as 16-bit timer in Mode2.Timer4 can select system clock as clock source. Other setting accords with mode 0. In Mode2, set TR4 bit of T4CON.1 and Timer4 wait for trigger signal of T4 port (controlled by T4M[1:0] rising/falling edge) to start counting.
  • Page 44 SH79F1640A Register Table 8.26 Timer4 Control Register C8H, Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 T4CON T4PS1 T4PS0 T4M1 T4M0 T4CLKS Reset Value (POR/WDT/LVR) Bit Number Bit Mnemonic Description Timer4 overflow flag bit 0: No overflow (cleared by hardware)
  • Page 45: Timer5

    SH79F1640A 8.7.3 Timer5 Timer5 is a 16-bit auto-reload timer. It is accessed as two cascaded data registers: TH5 and TL5. It is controlled by the T5CON register. The interrupt can be enabled by setting ET5 bit in IEN0 register (Refer to interrupt Section for details).
  • Page 46 SH79F1640A Register Table 8.28 Timer5 Control Register C0H, Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 T5CON T5PS1 T5PS0 Reset Value (POR/WDT/LVR) Bit Number Bit Mnemonic Description Timer5 overflow flag bit 0: No overflow (cleared by hardware) 1: Overflow (Set by hardware)
  • Page 47: Programmable Counter Array(Pca0)

    SH79F1640A 8.8 Programmable counter array(PCA0) 8.8.1 Feature ◼ SH79F1640A have a PCA, which is a general purpose 16-bit Timer/Counter module, with two independent Output Compare Units ◼ Phase Correct PWM Mode, Phase frequency Correct PWM Mode The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU intervention than the standard 8051 counter/timers.
  • Page 48 SH79F1640A The 16-bit PCA0 counter/timer consists of a 16-bit SFRs, PxTOPH and PxTOPL.consist of the 16-bit counter/timer. PxTOPH and PxTOPL can be configured TOP value, initial value of PxTOPH and PxTOPL is 0XFFFF. 16 bit counter/timer is the most basic module of PCA0, Enable or disable bit PRX of PCACON register can Start or Stop counter, when PR0 is set to logic '0', 16 bit counter was also forced the clear '0'.
  • Page 49 SH79F1640A Working mode selection is show in the following table: PCAx Mode Select Table Mode P0SDEN P0SMPn P0SMNn P0FSPn P0FSNn Function Capture triggered by positive edge (single slope) Mode0 Capture triggered by negative edge on (single slope) Capture triggered by transition (single slope)
  • Page 50: Mode0:Edge-Triggered Capture Mode

    SH79F1640A 8.8.2 Mode0:Edge-triggered Capture Mode In this mode, a valid transition on the P0CEXn pin causes the PCA0 to capture the value of the PCA counter/timer and load it into the corresponding module's 16-bit capture/compare register (P0CPLn and P0CPHn). The P0FSPn and P0FSNn bits in the...
  • Page 51: Mode1: Software Timer Mode

    SH79F1640A 8.8.3 Mode1: Software Timer Mode In Software Timer mode (P0SMPn:P0SMNn = 01, P0FSPn:P0FSNn = 0x), the PCA counter/timer value is compared to the module's 16-bit capture/compare register (P0CPHn and P0CPLn). When a match occurs, the Capture/Compare Flag (P0CCFn) in PCA0CF is set to logic 1 and an interrupt request is generated if P0CCFn interrupts are enabled. When P0TCPn = 1, the state of P0CEXn port pin can be changed.
  • Page 52: Mode2: Frequency Output Mode

    SH79F1640A 8.8.4 Mode2: Frequency Output Mode Frequency Output Mode produces a programmable-frequency square wave on the module’s associated P0CEXn pin. The capture/compare module high byte holds the number of PCA clocks to count before the output is toggled. The square wave frequency FP0CEXn = FPCA0/(2 X P0CPHn).
  • Page 53: Mode3: Pwm Mode

    SH79F1640A 8.8.5 Mode3: PWM Mode Each PCA0 module can be used independently to generate a pulse width modulated (PWM) output. The following Table summarizes the bit (P0FSPn, P0FSNn) settings in the P0CPMn registers used to select the PCA capture/compare module's operating PWM modes.
  • Page 54 SH79F1640A The following Figure 8.8-9, the state of P0CEXn pin is default at the first time clock cycle. The state of P0CEXn pin at the first clock cycle for P0CPLn = 0. P0CEXn pin output pwm wave from second time clock cycle to fourth time clock for P0CPLn = 01H, 80H, FEH.
  • Page 55 SH79F1640A Duty = (P0TOP – (P0CPn +1))/65536 The following Figure 8.8-11, the state of P0CEXn pin is default at the first time clock cycle. The state of P0CEXn pin at the first clock cycle for P0CPLn = 0. P0CEXn pin output pwm wave from second time clock cycle to fourth time clock for P0CPLn = 0001H, 8000H, FFFEH.
  • Page 56 SH79F1640A The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode can be configured by P0TOP. The minimum resolution allowed is 2-bit (P0TOP set to 0x003), and the maximum resolution is 16-bit.
  • Page 57 SH79F1640A The dual-slope operation has lower maximum operation frequency than single-slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The main difference between the phase correct, and the phase and frequency correct PWM mode is the time the P0TOP and P0CPn Register is updated by the P0TOP and P0CPn Buffer Register (see Figure 8.8-13 and Figure 8.8-15).
  • Page 58: Register

    SH79F1640A 8.8.6 Register Table 8.30 PCA0 Flag Register 98H, Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P0CF P0CCF1 P0CCF0 Reset Value (POR/WDT/LVR) Bit Number Bit Mnemonic Description PCA0 Counter/Timer Overflow Flag Set by hardware when the PCA0 Counter/Timer overflows from 0xFFFF to 0x0000. When the Counter/Timer Overflow (CF0) interrupt is enabled, setting this bit causes the CPU to jump to the PCA interrupt service routine.
  • Page 59 SH79F1640A Table 8.33 P0CPMn: PCA Capturre/Compare Register 9AH-9BH, Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P0CPM0 P0SMP0 P0SMN0 P0FSP0 P0FSN0 P0ECOM0 P0TCP0 P0MAT0 P0ECCF0 P0CPM1 P0SMP1 P0SMN1 P0FSP1 P0FSN1 P0ECOM1 P0TCP1 P0MAT1 P0ECCF1 Reset Value (POR/WDT/LVR) Bit Number...
  • Page 60 SH79F1640A Table 8.34 P0FORCE Forced Output Control Register DCH, Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P0FORCE P0OSC1 P0OSC0 P0FCO1 P0FCO0 Reset Value (POR/WDT/LVR) Bit Number Bit Mnemonic Description P0CEX1 output registers of Module1, the bit is effective only when the P0SMPn: P0SMNn = 01 and P0FSPn:P0FSNn = 1x.
  • Page 61 SH79F1640A Table 8.36 PCA0 Count Maximum High Byte 9FH, Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P0TOPH P0TOPH7 P0TOPH.6 P0TOPH.5 P0TOPH.4 P0TOPH3 P0TOPH2 P0TOPH1 P0TOPH.0 Reset Value (POR/WDT/LVR) Bit Number Bit Mnemonic Description P0TOPH.y P0TOPH: PCA0 TOP defines high byte (MSB) (y = 0-7) Table 8.37 PCA0 Capture/Compare Module Low Byte...
  • Page 62: Interrupt

    (Timer3-5), 1 PCA0 interrupts, 2 EUART interrupts, ADC interrupt, 2 PWM interrupts, Touch Key interrupt and LED interrupt, 1 TWI interrupt, 1 CRC interrupt, 1 LPD interrupt. The SH79F1640A have 4 interrupt priority levels, which make operating 19 interrupt sources becoming flexible.
  • Page 63 SH79F1640A Table 8.40 Interrupt Enable Register1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IEN1 ELPD ELED ETWI Reset Value (POR/WDT/LVR) Bit Number Bit Mnemonic Description LPD interrupt enable bit ELPD 0: Disable LPD interrupt 1: Enable LPD interrupt External interrupt2 enable bit...
  • Page 64 SH79F1640A (continue) PWM0 interrupt enable bit EPWM0 0: Disable PWM0 interrupt 1: Enable PWM0 interrupt CRC interrupt enable bit ECRC 0: Disable CRC interrupt 1: Enable CRC interrupt EUART1 interrupt enable bit 0: Disable EUART1 interrupt 1: Enable EUART1 interrupt Table 8.42 Interrupt Channel Enable Register...
  • Page 65: Interrupt Flag

    SH79F1640A 8.9.3 Interrupt Flag Each Interrupt source has its own interrupt flag, when interrupt occurs, corresponding flag will be set by hardware, the interrupt flag bits are listed in Table bellow. For external interrupt (INT0/1), when an external interrupt0/1 is generated, if the interrupt was edge trigged, the flag (IE0/1 in EXF0) that generated this interrupt is cleared by hardware when the service routine is vectored.
  • Page 66 SH79F1640A Table 8.45 External Interrupt Control Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EXF0 IT4.1 IT4.0 IT3.1 IT3.0 IT2.1 IT2.0 Reset Value (POR/WDT/LVR) Bit Number Bit Mnemonic Description External interrupt4 trigger mode selection bits 00: Low Level trigger...
  • Page 67: Interrupt Vector

    SH79F1640A 8.9.4 Interrupt Vector When an interrupt occurs, the program counter is pushed onto the stack and the corresponding interrupt vector address is loaded into the program counter. The interrupt vector addresses are listed in Interrupt Summary table. 8.9.5 Interrupt Priority Each interrupt source can be individually programmed to one of four priority levels by setting or clearing corresponding bits in the interrupt priority control registers IPL0, IPH0, IPL1, and IPH1.
  • Page 68: Interrupt Handling

    SH79F1640A 8.9.6 Interrupt Handling The interrupt flags are sampled and polled at the fetch period of each machine period. All interrupts are sampled at the rising edge of the clock. If one of the flags was set, the CPU will find it and the interrupt system will generate a LCALL to the appropriate service routine, provided this hardware-generated LCALL is not blocked by any of the following conditions: An interrupt of equal or higher priority is already in progress.
  • Page 69: External Interrupt Input

    The operation of INT4 is similar with INT0, 1, but it has more trigger modes. When SH79F1640A is in IDLE mode or PD mode, interrupt will cause the processor to wake up and resume operation, refer to “Power Management” chapter for details.
  • Page 70 SH79F1640A Table 8.48 External Interrupt Sample Times Rontrol Registrer 8BH, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EXCON I1PS1 I1PS0 I1SN1 I1SN0 I0PS1 I0PS0 I0SN1 I0SN0 Reset Value (POR/WDT/LVR) Bit Number Bit Mnemonic Description INT4 sample clock Prescaler Select bits...
  • Page 71: Interrupt Summary

    SH79F1640A 8.9.9 Interrupt Summary Vector Polling Interrupt No. Source Enable bits Flag bits Address Priority (C51) Reset 0000H 0 (higest) INT0 0003H 000BH IFERR+IFGO+IFAVE+IFCOUNT INT1 0013H Timer5 001BH EUART0 0023H RI+TI Timer3 002BH 0033H EADC ADCIF/ADGIF/ADLIF 003BH ETWI TWINT 0043H...
  • Page 72: Enhanced Function

    SH79F1640A built-in Touch Key function module, which can connect at most 20 keys. SH79F1640A built-in simplified operating circuit in Touch Key function module, the application of it only need to use a external connected C1 capacitor. The value of C1 capacitor choose 10nF -100nF, must use polyester capacitor of 10% or more accuracy, X7R capacitor or NPO capacitor.
  • Page 73 SH79F1640A There are four kinds of touch buttons will produce the interrupt flag, in which the 1th-4th will be interrupted, need to judge the interrupt flag bit after the implementation of interrupt subroutine: (1) After the end of the scan button, if the result of the operation is high, the interrupt flag bit IFERR is set to 1. If it is a multi - sampling, the system will stop the current sampling status and wait for the next restart, and do not perform the sampling.
  • Page 74 SH79F1640A Operating Flow: START TKCON = 1 CHOSE CHANNELS REGISTER: TKU1-TKU3 FUNCTION REGISTER: VREF[0:1] ,VTK[0:1] ,CMPD[0:1] ,VTK[0:1] ,RANDOM [0:1] ,TKST[0:7],FSW[0:1],TKRANDOM[0:7] 28Bit AMPLIFICATION FACTOR REGISTER: TKDIV01-TKDIV04 DELAY 10uS TKGO=1 WATING FOR THE TOUCH-KEY INTERRUPT PRODUCE OR SCANNING TKIF. TOUCH KEY INTERRUPT...
  • Page 75: Register

    SH79F1640A 9.1.1 Register Table 9.1 TouchKey Functional Control Register C1H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TKGO TKCON1 TKCON DATACON MODE FSW1 FSW0 ---- ---- ---- ---- Reset Value (POR/WDT/LVR) Bit Number Bit Mnemonic Description Touch Key Enable bit...
  • Page 76 SH79F1640A Table 9.3 Touch Key Frequency Random Setting Register C2H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TKRANDOM TKRADON TKOFFSET TKHYSW TKOSM RANDOM1 RANDOM0 Reset Value (POR/WDT/LVR) Bit Number Bit Mnemonic Description Touch Key Random Frequency Enable bit...
  • Page 77 SH79F1640A Table 9.4 Touch Key Interrupt Flag Register (The register only can be cleared) C7H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TKF0 IFERR IFGO IFAVE IFCOUNT Reset Value (POR/WDT/LVR) Bit Number Bit Mnemonic Description Calculated Result Overflow Interrupt Flag bit 0: Calculated result high-bit don’t overflow...
  • Page 78 SH79F1640A Table 9.6 Port Function Control Register BCH-BFH, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P0SS (BCH) P0SS.6 P0SS.5 P0SS.4 P0SS.3 P0SS.2 P0SS.1 P0SS.0 P1SS (BDH) P1SS.7 P1SS.6 P1SS.5 P1SS.4 P1SS.3 P1SS.2 P1SS.1 P1SS.0 P4SS (BEH) P4SS.3 P4SS.2 P4SS.1...
  • Page 79 SH79F1640A Table 9.8 Reference Voltage Selection Register CEH, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TKVREF VREF1 VREF0 CMPD1 CMPD0 VTK1 VTK0 TUNE1 TUNE0 Reset Value (POR/WDT/LVR) Bit Number Bit Mnemonic Description Internal Reference Voltage Selection bit 00: V = 2.0V...
  • Page 80 SH79F1640A Table 9.9 Key Scan Sequence Register C9H-CBH (Bank0) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TKU1 (C9H) TKU2 (CAH) TK16 TK15 TK14 TK13 TK12 TK11 TK10 TKU3 (CBH) TK24 TK23 TK22 TK17 Reset Value (POR/WDT/LVR) Bit Number Bit Mnemonic...
  • Page 81 SH79F1640A (continue) 518H TK13L 519H TK13H 51AH TK14L 51BH TK14H 51CH TK15L 51DH TK15H 51EH TK16L 51FH TK16H 520H TK17L 521H TK17H 52AH TK22L 52BH TK22H 52CH TK23L 52DH TK23H 52EH TK24L 52FH TK24H Note: (1) OP output voltage is supply voltage of Touch Key, V is reference voltage source of Touch Key.
  • Page 82: Led Driver

    SH79F1640A 9.2 LED Driver The LED driver contains a controller, 4 Common signal pins and 8 Segment driver pins. Support 1/1 - 1/4 duty voltage driving mode. The LED driver have two kind of operate mode. Mode 1: Light LED Mode When LED driver working under the light LED mode, each LEDRAM control a LED light, if LEDRAM bit is 0, LED light out;...
  • Page 83: Register

    SH79F1640A 9.2.1 Register Table 9.11 LED Control Register D6H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDCON LEDON LEDMD MODE LEDIF COMIF MODSW Reset Value (POR/WDT/LVR) Bit Number Bit Mnemonic Description LED enable control bit LEDON 0: Disable LED driver...
  • Page 84 SH79F1640A Table 9.13 LED Dead-time State Control Register D5H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDST COMTCP SEGTCP Reset Value (POR/WDT/LVR) Bit Number Bit Mnemonic Description COMTCP active level control bit COMTCP 0: Output low when valid, floating when invalid...
  • Page 85 SH79F1640A Note: Mode1 example: is the width of single LED COM scan, T is the width of system clock, T is the width of LED scan time. X 256 X DISCOM S is the quantity of scan LED COM: scan 3COM: S = 3, scan 5COM: S = 4, and so on.
  • Page 86 SH79F1640A Mode2 example: is the width of single LED COM scan, T is the width of system clock, T is the width of LED scan time. X 256 X DISCOM S is the quantity of scan LED COM: scan 3COM: S = 3, scan 4COM: S = 4, and so on.
  • Page 87 SH79F1640A Mode2 Dimming Diagram: COMIF=1 COMIF=1 COMIF=1 COMIF=1 COMIF=1 interrupt interrupt interrupt interrupt interrupt Initialization COM1 COM2 SEG0daty=0xFF SEG0daty=0x00 SEG0daty=0x00 SEG0daty=0x00 SEG0 SEG1daty=0x00 SEG1daty=0x00 SEG1 SEG1daty=0x00 SEG1daty=0x7F SEG2daty=0x00 SEG2daty=0xFF SEG2daty=0xFF SEG2daty=0x00 SEG2 SEG3daty=0x00 SEG3daty=0x00 SEG3daty=0x55 SEG3daty=0x00 SEG3 SEG4daty=0x00 SEG4daty=0xFF SEG4daty=0x00...
  • Page 88 0: used as I/O 1: used as SEG (LED_S1 - LED_S8) Note: The VCC_IN of SH79F1640A have maximum over current restriction (refers to Electrical Characteristics chapter). Please evaluate the current which flowing through VDD, if over 8 SEG have been enabled.
  • Page 89 SH79F1640A LED RAM Mode1: Address 530H COM1 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 532H COM2 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 534H COM3 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 536H COM4 SEG8 SEG7 SEG6...
  • Page 90: Bit Pulse Width Modulation (Pwm0/1)

    ◼ Selectable output polarity The SH79F1640A has two 12-bit PWM module. Which can provide two channel pulse width modulation waveform with the period and the duty being controlled individually by corresponding register. PWMxEN (x = 0-1) used to enable PWM modules.
  • Page 91 SH79F1640A (continue) PWMx interrupt flag bit PWMxIF 0: PWMx period counter isn’t overflow 1: Set by hardware to indicate that the PWM0 period counter overflow PWMx pin output control bit 0: PWMx output disable, PWM0 as I/O Note: if this bit is 0 but PWMxEN = 1, the PWM timer can work normally, only PWMxSS can not output waveform, the PWMx still can be used as a timer.
  • Page 92 SH79F1640A Table 9.20 PWM0 Duty Control Register PWM0DH/L DDH, DCH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWM0DH (DDH) PWM0D.11 PWM0D.10 PWM0D.9 PWM0D.8 PWM0DL (DCH) PWM0D.7 PWM0D.6 PWM0D.5 PWM0D.4 PWM0D.3 PWM0D.2 PWM0D.1 PWM0D.0 Reset Value (POR/WDT/LVR) Bit Number Bit Mnemonic...
  • Page 93 SH79F1640A PWM clock t PWM output (PWMS=0) PWM output (PWMS=1) PWMP = F0H PWM output duty cycle = 7FH x t PWMD = 7FH PWM output period cycle = F0H x t PWM Output Example 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 01 02 03 04 05 06 07...
  • Page 94: Euart0/1

    This mode provides synchronous communication with external devices. In this mode serial data is transmitted and received on the RXDx line. TXDx is used to output the shift clock. The TXDx clock is provided by the SH79F1640A whether the device is transmitting or receiving.
  • Page 95 SH79F1640A Any instruction that uses SBUFx as a destination register (“write to SBUFx” signal) will start the transmission. The next system clock tells the Tx control block to commence a transmission. The data shift occurs at the falling edge of the SHIFT CLOCK, and the contents of the transmit shift register is shifted one position to the right.
  • Page 96 SH79F1640A Transmission begins with a “write to SBUFx” signal, and it actually commences at the next system clock following the next rollover in the divide-by-16 counter (divide baud-rate by 16), thus, the bit times are synchronized to the divide-by-16 counter, not to the “write to SBUFx”...
  • Page 97 SH79F1640A Mode2: 9-Bit EUARTx, Fixed Baud Rate, Asynchronous Full-Duplex This mode provides the 11 bits full duplex asynchronous communication. The 11 bits consists of one start bit (logical 0), 8 data bits (LSB first), a programmable 9 data bit, and a stop bit (logical 1). Mode 2 supports multiprocessor communications and hardware address recognition (Refer to Multiprocessor Communication Section for details).
  • Page 98 SH79F1640A Reception is enabled only if RXDx is high. The serial port actually starts the receiving of serial data, with the detection of a falling edge on the RXDx pin. For this purpose RXDx is sampled at the rate of 16 times baud rate. When a falling edge is detected, the divide-by-16 counter is immediately reset.
  • Page 99: Baud Rate Generate

    SH79F1640A 9.4.3 Baud Rate Generate EUARTx with own baud rate generator, the baud rate generator is an 15-bit up-counting timer. Overflow 15-bit timer To EUART Fsys From 7FFFH to 0000H SBRTEN=1 SBRTH[14:8],SBRTL7:0] Baudrate Generator for EUART The overflow rate of baud rate generator can be calculated as follow:...
  • Page 100: Multi-Processor Communication

    SH79F1640A 9.4.4 Multi-Processor Communication Software Address Recognition Modes 2 and 3 of the EUARTx have a special provision for multi-processor communication. In these modes, 9 data bits are received. The 9th bit goes into RB8. Then a stop bit follows. The EUARTx can be programmed such that when the stop bit is received, the EUARTx interrupt will be activated (i.e.
  • Page 101: Error Detection

    SH79F1640A 9.4.5 Error Detection Error detection is available when the SSTAT bit in register PCON is set to logic 1. All the 3 bits should be cleared by software after they are set, even when the following frames received without any error will not be cleared automatically.
  • Page 102 SH79F1640A Table 9.23 EUART0 Control and Status Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCON /RXOV /TXCOL Reset Value (POR/WDT/LVR) Bit Number Bit Mnemonic Description EUART0 Serial mode control bits, when SSTAT = 0 00: mode 0, Synchronous Mode, fixed baud rate...
  • Page 103 SH79F1640A Table 9.24 EUART0 Data Buffer Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SBUF SBUF.7 SBUF.6 SBUF.5 SBUF.4 SBUF.3 SBUF.2 SBUF.1 SBUF.0 Reset Value (POR/WDT/LVR) Bit Number Bit Mnemonic Description This SFR accesses two registers; a transmit shift register and a receive latch register...
  • Page 104 SH79F1640A Table 9.28 EUART1 Control & Status Register A0H, Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SM10 SM11 SM12 SCON1 REN1 TB81 RB81 /FE1 /RXOV1 /TXCOL1 Reset Value (POR/WDT/LVR) Bit Number Bit Mnemonic Description EUART1 Serial mode control bits, when SSTAT = 0...
  • Page 105 SH79F1640A Table 9.29 EUART1 Serial Control Register A7H, Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PCON1 SMOD1 SSTAT1 Reset Value (POR/WDT/LVR) Bit Number Bit Mnemonic Description EUART1 Baud rate doubler SMOD1 0: in Mode2, the baud-rate of EUART is 1/64 of the system clock...
  • Page 106 SH79F1640A Table 9.32 EUART1 Baudrate Generator Register A5H-A4H, Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SBRTH1 (A5H) SBRTEN1 SBRT1.14 SBRT1.13 SBRT1.12 SBRT1.11 SBRT1.10 SBRT1.9 SBRT1.8 SBRTL1 (A4H) SBRT1.7 SBRT1.6 SBRT1.5 SBRT1.4 SBRT1.3 SBRT1.2 SBRT1.1 SBRT1.0 Reset Value (POR/WDT/LVR)
  • Page 107: Twi Serial Interface (Twi)

    ◼ System in Idle state can be Wake-up ◼ Programmable Slave Address The TWI Interface complete the transition with SDA and SCL, between Master and Slaver. SH79F1640A has the ability to process and transmit byte, and track the serial transaction automaticly, which conforms to TWI protocol.
  • Page 108 STOP SH79F1640A generates an ACK by pulling the SDA line low. After the interrupt flag be set, SH79F1640A pulls the SCL line low, and releases SDA line. When the interrupt process has completed, SCL line should be released and TWINT flag should be cleared.
  • Page 109 SH79F1640A Data Arbitration A master may start a transfer only if the bus is free. Two or more masters may generate a START condition within the minimum hold time (tHOLD:STA) of the START condition which results in a defined START condition to the bus.
  • Page 110: Overview Of The Twi Moudle

    FREE the Bus. The function is only used in the transmission process of one packet (8 + 1 bit). When SH79F1640A is in slave transfer mode and the first byte of transferred message is low, the function can be used. STA and RSTA is not situable for this function.
  • Page 111: Transmission Modes

    SH79F1640A Bit Rate Generator Unit This unit controls the period of SCL when operating in a Master mode. The SCL period is controlled by settings in the TWI Bit Rate Register (TWIBR) and in the TWICON(CR[1:0]). The SCL frequency is generated according to the following equation: /(16+2 X CR X TWIBR).
  • Page 112 SH79F1640A Master Transmitter Mode In the Master Transmitter mode, a number of data bytes are transmitted to a Slave Receiver. In order to enter a Master mode, a START condition must be transmitted. The format of the following address packet determines whether Master Transmitter or Master Receiver mode is to be entered.
  • Page 113 Arbitration lost in slave Ack or Nack Ack or Nack address or data byte Other Master Other Master Continue Continue Arbitration lost and addressed as slave To Corresponding state in slave mode 68H/78H/B0H Other Device Actions SH79F1640A Actions...
  • Page 114 SH79F1640A Master Receiver Mode In the Master Receiver mode, a number of data bytes are received from a Slave Transmitter. In order to enter a Master mode, a START condition mustbe transmitted. The format of the following address packet determines whether MasterTransmitter or Master Receiver mode is to be entered.
  • Page 115 Transmitter Arbitration lost in slave Ack or address or not acknowledged Nack Other Master Other Master Continue Continue Arbitration lost and addressed as slave To Corresponding state in slave mode Other Device Actions 68H/78H/B0H SH79F1640A Actions...
  • Page 116 TWICON register and TWIADR register must be initialized: set ENTWI bit and AA bit in TWICON register, clearing STA, STO and TWINT; The high 7-bit in TWIADR register is used to prepare the corresponding address for SH79F1640A. If GC is set, SH79F1640A will respond the general address (00H);...
  • Page 117 When AA = 0, SH79F1640A can’t respond the visit to its own address. However, SH79F1640A still monitors the bus status, and address recognition may resume at any time by setting AA. This implies that the AA bit may be used to temporarity isolate SH79F1640A from the bus.
  • Page 118 SH79F1640A (continue) Arbitration lost in SLA + Receive data byte; Transmit NACK R/W as master; General No TWIDAT address has been action received; Receive data byte; Transmit ACK ACK has been received Previously addressed Receive data byte; Transmit NACK with own SLA address;...
  • Page 119 P or S not acknowledged Other Device Actions SH79F1640A Actions Other Modes There are two status codes that do not correspond to a defined TWI state. Status 0xF8 indicates that no relevant information is available because the TWINT Flag is not set, and when the TWI is not involved in a serial transfer.
  • Page 120: Register

    SH79F1640A 9.5.5 Register Table 9.34 TWI Control Register C8H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TWICON TOUT ENTWI TWINT TFREE EFREE Reset Value (POR/WDT/LVR) Bit Number Bit Mnemonic Description Bus Timeout Flag 0: No Timeout TOUT 1: Timeout happened when the periods of bus low level is more than N X T Then the bit will be set.
  • Page 121 SH79F1640A Table 9.35 Timeout For Bus Low level Count Register FEH, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TWITOUT CNT1 CNT0 TWIPCR Reset Value (POR/WDT/LVR) Bit Number Bit Mnemonic Description Bus Timeout Count 00: N = 25000 01: N = 50000...
  • Page 122 SH79F1640A Table 9.38 TWI Bit Rate Register 8AH, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TWIBR TWIBR.7 TWIBR.6 TWIBR.5 TWIBR.4 TWIBR.3 TWIBR.2 TWIBR.1 TWIBR.0 Reset Value (POR/WDT/LVR) Bit Number Bit Mnemonic Description TWIBR[7:0] Selects the division factor for the bit rate generator Table 9.39 TWI Address Register...
  • Page 123: Logic Configurable Module (Lcm)

    SH79F1640A 9.6 Logic Configurable Module (LCM) 9.6.1 Feature ◼ Though the Logic Configurable Module 12 kinds of Logic function port can be remap to I/O, and each function can choose one of the eight IO to map. The Logic Configurable Module (LCM) used to realize the remap of some logic function port, and keep the one-to-one match between logic and hardware.
  • Page 124 SH79F1640A Function UART0 UART1 PWM0 PWM1 PCA0 INT2 RXD0 TXD0 RXD1 TXD1 PWM0 PWM1 P0CEX0 P0CEX1 ECI0 INT2 ◼ ● ● ● ● P0.0 ◼ ● ● ● ● P0.1 ◼ ● ● P0.2 ● ● ● P0.3 ● P0.4 ◼...
  • Page 125: Register

    SH79F1640A 9.6.2 Register Table 9.42 TXD0 and RXD0 Selection Register E2H, Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 UART0CR TX0CR2 TX0CR1 TX0CR0 RX0CR2 RX0CR1 RX0CR0 Reset Value (POR/WDT/LVR) Bit Number Bit Mnemonic Description TXD0 Selection Bits 000: TXD0 map to P0.0 001: TXD0 map to P0.1 (Default)
  • Page 126 SH79F1640A Table 9.44 SCK and SDA Selection Register E5H, Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TWICR SCKCR2 SCKCR1 SCKCR0 SDACR2 SDACR1 SDACR0 Reset Value (POR/WDT/LVR) Bit Number Bit Mnemonic Description SCK Selection Bits 000: SCK map to P0.0 001: SCK map to P0.1...
  • Page 127 SH79F1640A Table 9.46 P0CEX1 and P0CEX0 Selection Register E7H, Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CEXCR CE1CR2 CE1CR1 CE1CR0 CE0CR2 CE0CR1 CE0CR0 Reset Value (POR/WDT/LVR) Bit Number Bit Mnemonic Description P0CEX1 Selection Bits 000: P0CEX1 map to P0.0 001: P0CEX1 map to P0.1...
  • Page 128: Analog Digital Converter (Adc)

    ◼ The conversion rate of 1 channels (AN3) ADC is up to 1MSPS The SH79F1640A includes a single ended, 12-bit SAR Analog to Digital Converter (ADC Analog-to-Digit Converter). Module as shown in Figure 9.7-1. After reset, the default reference voltage of ADC is V...
  • Page 129: Adc Diagram

    SH79F1640A 9.7.2 ADC Diagram Software Trigger Event Trigger sequence mode SEQCH0 State pointer GRP[2:0] SEQCHn SEQCH7 Mode Arbiter ADD0L/H 12-Bits ADDnL/H ADD7L/H (1.20V) ADC_Clk Time Gap Refc Logic Pre-Counter for ADC clock,4-bit SOC Stands for Start of Convertion System Clock...
  • Page 130: Adc Register

    SH79F1640A 9.7.3 ADC Register The registers of ADC moldule are as follows: Function Name Register Description ADC Clock Register Configuration of ADC clock, sample time Enable of ADC module, start a conversion, trigger mode and sources, ADCON1 interrupt flag ADC control Register...
  • Page 131 SH79F1640A For Example: System Clock TADC[2:0] TS[3:0] Sample time Conversion time 0000 0.083*1=0.083us 0000 2*0.083=0.166us 14*0.083+0.166=1.328us 0000 0.083*1=0.083us 0111 8*0.083=0.664us 14*0.083+0.664=1.826us 0000 0.083*1=0.083us 1111 15*0.083=1.245us 14*0.083+1.245=2.407us 12MHz 1111 0.083*192=15.936us 0000 2*15.936=31.872us 14*15.936+31.872=254.976us 1111 0.083*192=15.936us 0111 8*15.936=127.488us 14*15.936+127.488=350.592us 1111 0.083*192=15.936us 1111 15*15.936=239.04us...
  • Page 132 SH79F1640A Table 9.50 ADC Control Register2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADCON2 GRP2 GRP1 GRP0 TGAP2 TGAP1 TGAP0 Reset Value (POR/WDT/LVR) Bit Number Bit Mnemonic Description Reference source switch bit 0: Disable 1.20V Reference 1: Enable 1.20V Reference...
  • Page 133 SH79F1640A Table 9.51 Map Control Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SEQCON REG2 REG1 REG0 Reset Value (POR/WDT/LVR) Bit Number Bit Mnemonic Description ADC result left & right aligned selection bit 0: The 12-bits result stored in result register ADDxL/H (x = 0 - 7) are stored in left aligned.
  • Page 134 SH79F1640A Table 9.53 Channel Register x (x = 0 - 7) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SEQCHX SEQx3 SEQx2 SEQx1 SEQx0 Reset Value (POR/WDT/LVR) Bit Number Bit Mnemonic Description Channel selection bits 0000: Channel0 (CH0) 0001: Channel1 (CH1)
  • Page 135 SH79F1640A (continue) Bit Number Bit Mnemonic Description Left alignment mode (ALR = 0) After the conversion of a channel, the data updated immediately and stored in ADDxL/H(x = 0 - 7) High 8 bits are stored in ADDxH, the low 4 bits are stored in the high 4 bits in ADDxL register.
  • Page 136: Sequence Conversion Mode

    SH79F1640A 9.7.4 Sequence Conversion Mode The ADC sequence consist of one or more channels, the conversion of sequence is to convert the channels in the sequence one by one. It makes multiple signals to convert at the same time become possible in hardware. (the minmum sampling gap between two channels is 1us,so it can be regard as at the same time approximately) The conversion result is stored in the corresponding result register ADDxL/H (x = 0 - 7), the result register is read only register.
  • Page 137 SH79F1640A GRP[2:0] = 2 Result SEQCH0 = 3 ADD0L/H SEQCH1 = 2 ADD1L/H SEQCH2 = 0 ADD2L/H SEQCH3 = x ADD3L/H sequencer SEQCH6 = x ADD6L/H SEQCH7 = x ADD7L/H Figure 9.7-4 The Configuration of Gap Time Between Adjacent Channel During Sequence Conversion During sequence conversion, the time between last channel finished conversion and next channel start sampling can be set by TGAP bit in ADCON2 register.
  • Page 138: The Configuration Of Adc Conversion Time

    SH79F1640A 9.7.5 The Configuration of ADC Conversion Time The ADC clock and sampling time can be set through ADT register. By setting the TADC[3:0] bits in the ADT can set the ADC clock. The TS[3:0] bits in the register ADT can be used to set the sampling time (t...
  • Page 139: Low Power Detect (Lpd)

    SH79F1640A 9.8 Low Power Detect (LPD) 9.8.1 Feature ◼ An internal flag indicates low power is detected ◼ LPD detect voltage is selectable ◼ LPD include bilateral debounce Low Power Detect (LPD) function is used to monitor the supply voltage and generate an internal flag if the voltage decrease below the specified value.
  • Page 140 SH79F1640A Table 9.56 LPD Voltage Selection Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LPDSEL LPDS3 LPDS2 LPDS1 LPDS0 Reset Value (POR/WDT/LVR) Bit Number Bit Mnemonic Description LPD Voltage Select Bit 0011:2.85V 0100:3.00V 0101:3.15V 0110:3.30V 0111:3.45V 1000:3.60V LPDS[3:0] 1001:3.75V 1010:3.90V...
  • Page 141: Low Voltage Reset (Lvr)

    SH79F1640A 9.9 Low Voltage Reset (LVR) 9.9.1 Feature ◼ Enabled by the code option and VLVR is 3.1V, 3.7V or 4.1V ◼ LVR de-bounce timer TLVR is about 30-60s ◼ An internal reset flag indicates low voltage reset generates The LVR function is used to monitor the supply voltage and generate an internal reset in the device when the supply voltage below the specified value VLVR.
  • Page 142: Watchdog Timer (Wdt), Ovl Reset And Reset State

    OVL Reset To enhance the anti-noise ability, SH79F1640A built in Program Counter (PC) over range detect circuit, if program counter value is larger than flash romsize, or detect operation code equal to A5H which is not exist in 8051 instruction set, a OVL reset will be generate to reset CPU, and set WDOF bit.
  • Page 143: Crc Verification Module

    ◼ CRC generator polynomial adopt the CRC-CCITT Standard: X16 + X12 + X5 + 1, high bit first To improve the system reliability, the SH79F1640A has one CRC verification module built-in, CRC check code can be used to generate real-time code, using the generation polynomial: X + 1, which adopt the CRC-CCITT Standard.
  • Page 144 SH79F1640A Table 9.59 CRC Result Register (Note: low bits address in front, high bits address in the post) F9H, FAH, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CRCDL (F9H) CRCD.7 CRCD.6 CRCD.5 CRCD.4 CRCD.3 CRCD.2 CRCD.1 CRCD.0 CRCDH (FAH) CRCD.15...
  • Page 145: Power Management

    (2) Reset signal (WDT RESET if enabled, LVR RESET if enabled), this will restore the clock to the CPU, the SUSLO register and the IDL bit in PCON register will be cleared by hardware, finally the SH79F1640A will be reset. And the program will execute from address 0000H.
  • Page 146: Register

    SH79F1640A 9.12.4 Register Table 9.61 Power Control Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PCON SMOD SSTAT Reset Value (POR/WDT/LVR) Bit Number Bit Mnemonic Description SMOD EUART Baud rate doubler SSTAT SCON[7:5] function select bit GF[1:0] General purpose flags for software use...
  • Page 147: Warm-Up Timer

    ◼ Built-in oscillator warm-up counter to eliminate unstable state when oscillation startup SH79F1640A has a built-in power warm-up counter; it is designed to eliminate unstable state after power on or to do some internal initial operation such as read customer option etc.
  • Page 148: Code Option

    SH79F1640A 9.14 Code Option OP_WDT: 0101: Disable WDT function other: Enable WDT function (default) OP_WDTPD: 0: Disable WDT function in Power-Down mode (default) 1: Enable WDT function in Power-Down mode OP_OSC: 0000: OSC1CLK is Internal high RC oscillator, OSC2CLK closed (default)
  • Page 149: Instruction Set

    SH79F1640A 10. Instruction Set ARITHMETIC OPERATIONS Opcode Description Code Byte Cycle ADD A, Rn Add register to accumulator 0x28-0x2F ADD A, direct Add direct byte to accumulator 0x25 ADD A, @Ri Add indirect RAM to accumulator 0x26-0x27 ADD A, #data...
  • Page 150 SH79F1640A LOGIC OPERATIONS Opcode Description Code Byte Cycle ANL A, Rn AND register to accumulator 0x58-0x5F ANL A, direct AND direct byte to accumulator 0x55 ANL A, @Ri AND indirect RAM to accumulator 0x56-0x57 ANL A, #data AND immediate data to accumulator...
  • Page 151 SH79F1640A DATA TRANSFERS Opcode Description Code Byte Cycle MOV A, Rn Move register to accumulator 0xE8-0xEF MOV A, direct Move direct byte to accumulator 0xE5 MOV A, @Ri Move indirect RAM to accumulator 0xE6-0xE7 MOV A, #data Move immediate data to accumulator...
  • Page 152 SH79F1640A PROGRAM BRANCHES Opcode Description Code Byte Cycle ACALL addr11 Absolute subroutine call 0x11-0xF1 LCALL addr16 Long subroutine call 0x12 Return from subroutine 0x22 RETI Return from interrupt 0x32 AJMP addr11 Absolute jump 0x01-0xE1 LJMP addr16 Long jump 0x02 SJMP rel...
  • Page 153 SH79F1640A BOOLEAN MANIPULATION Opcode Description Code Byte Cycle CLR C Clear carry flag 0xC3 CLR bit Clear direct bit 0xC2 SETB C Set carry flag 0xD3 SETB bit Set direct bit 0xD2 CPL C Complement carry flag 0xB3 CPL bit...
  • Page 154: Electrical Characteristics

    SH79F1640A 11. Electrical Characteristics Absolute Maximum Rating* *Comments Stresses exceed those listed under “Absolute Maximum DC Supply Voltage....-0.3V to +6.0V Ratings” may cause permanent damage to this device.
  • Page 155 SH79F1640A (continue) Pull-high Resistor = 5.0V, V = GND k I/O Port (P0, P1, P4, P3, P5), = 4.3V, V = 5.0V IO Output Current I/O Port (P0, P1, P4, P3, P5), OH1MAX(1) = 5.0V, T = 25° C I/O Port (P0, P1, P4, P3, P5), (OP_P33-P30 Select sink ability normal mode) = 0.6V, V...
  • Page 156 SH79F1640A (continue) 8 = 5.0V, ADC CLK  24MHz Total absolute error LSB V = 5.0V, V s ADC clock period 0.04 s ADC sampling time SAMP Total conversion time Note: (1) “*” Here the A/D input Resistor is the ADC input-resistance of A/D itself.
  • Page 157: Ordering Information

    SH79F1640A 12. Ordering Information Part No. Package SH79F1640AM/028MU SOP28...
  • Page 158: Product Naming Rules

    SH79F1640A 13. Product Naming Rules SH 79 F 16 40 A M / 028 M U U: Tube M: SOP package 028: Package pins is 28 /: Divider M: SOP package A: version 40: Product serial number 16: Product flash size 16K bytes...
  • Page 159: Package Information

    SH79F1640A 14. Package Information SOP 28L Outline Dimensions unit: inches/mm  Detail F See Detail F Seating Plane Dimensions in inches Dimensions in mm Symbol 0.085 0.104 2.15 2.65 0.004 0.012 0.10 0.30 0.081 0.098 2.05 2.50 0.013 0.02 0.33 0.51...
  • Page 160: Product Spec Change Notice

    SH79F1640A 15. Product SPEC Change Notice Version Content Data Original Aug. 2023...
  • Page 161 SH79F1640A IMPORTANT NOTICE This manual is the property of Sino Wealth Electronic Ltd. and its affiliates ("Company"). This manual, including all of the Company's products ("Products") described herein, is owned by the Company according to relevant laws or treaties. The Company reserves all rights under such laws and treaties, and does not grant you any license to use its patents, copyrights, trademarks and other intellectual property rights.
  • Page 162: Table Of Contents

    SH79F1640A Content FEATURES ......................................1 GENERAL DESCRIPTION ................................1 BLOCK DIAGRAM .................................... 2 PIN CONFIGRATION ..................................3 PIN DESCRIPTION .................................... 5 PRODUCT INFORMATION ................................7 SFR MAPPING ....................................8 NORMAL FUNCTION ..................................20 8.1 CPU ........................................20 8.1.1 CPU Core Special Function Register ............................20 8.1.2 Enhanced CPU core SFRs ................................
  • Page 163 SH79F1640A ENHANCED FUNCTION ................................72 9.1 T ..................................72 OUCH UNCTION 9.1.1 Register ....................................... 75 9.2 LED D ....................................... 82 RIVER 9.2.1 Register ....................................... 83 9.3 12 (PWM0/1) ........................... 90 ULSE IDTH ODULATION 9.3.1 Feature ....................................... 90 9.3.2 12bit PWM Timer ..................................90 9.4 EUART0/1 ......................................

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