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1. Features
8bits micro-controller with Pipe-line structured 8051
compatible instruction set
Flash ROM:64K Bytes
RAM:Internal 256 Bytes, external 2816 Bytes
EEPROM-Like:bulid-in 4096 Bytes(code option)
Operation Voltage:
- f
= 32.768kHz - 24MHz, V
OSC
Oscillator (code option):
- Crystal oscillator: 32.768kHz
- Crystal oscillator: 2MHz - 16MHz
- Ceramic oscillator: 2MHz - 16MHz
- Internal RC oscillator: 24MHz (±1%)/128K (±10%)
42/30/26 CMOS bi-directional I/O pins (44 pins/32
pins/28 pins)
Built-in pull-up resistor for input pin (30kΩ)
12 large current driver I/O (code option optional
enhanced or standardized or weakened)
P0 port can reduce the pull current capacity (code option
optional weakened or standardized)
One16-bit timer/counters T3
Three 16-bit PCA0, PCA1 and PCA2 each contain two
comparison/capture units
3 channels 12-bits PWM timer
Interrupt sources:
- Timer3, PCA0-2
- INT0-3
- INT4: 8 input
- ADC, EUART, SPI
- PWM, SCM, CRC, TWI, LPD
2. General Description
The SH79F6441 is high performance 8051 compatible micro-controller. The SH79F6441 can perform more fast operation
speed and higher calculation performance, if compare SH79F6441 with standard 8051 at same clock speed.
The SH79F6441 retains most features of the standard 8051. These features include internal 256 bytes RAM, Three UART and
INT0, INT1, INT2, INT3, INT4. In addition, SH79F6441 provides external 2816 bytes RAM. It also contains 64K bytes Flash
memory block for program storage.
The SH79F6441 not only include many standard communication modules, such as EUART, TWI, SPI and so on, but also
include 12bit ADC, PWM timer, ect.
In addition, the SH79F6441 also have CRC module, Logic configurable module (LCM) built in it.
For high reliability and low cost issues, the SH79F6441 builds in Watchdog Timer, Low Voltage Reset function and system clock
monitor. And SH79F6441 also supports two power saving modes to reduce power consumption.
= 2.7V - 5.5V
DD
Enhanced 8051 Microcontroller
SPI (Master/Slave Mode)
TWI (Master/Slave Mode)
Internal Logic Configuration Module(LCM)
3 enhanced UART (3V/5V communication) (own
baudrate generator)
15 analog inputs 12-bit Analog Digital Converter
Built-in low voltage Reset (LVR) function (code option)
- LVR voltage1: 4.1V
- LVR voltage2: 3.7V
- LVR voltage3: 2.8V
Built-in CRC verification module, the verify size can be
selected
Low Power Detect (LPD) Module with 13 level optional
Support single line simulation and download
CPU Machine period: 1 oscillator clock
Built-in Watch Dog Timer (WDT)
Built-in oscillator Warm-up timer
Support Low power operation modes:
- Idle Mode
- Power-Down Mode
Flash Type
Package:
- LQFP44
- LQFP32
- QFN32
- SOP28
1
SH79F6441
V2.3

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Summary of Contents for Sino Wealth SH79F6441

  • Page 1 In addition, the SH79F6441 also have CRC module, Logic configurable module (LCM) built in it. For high reliability and low cost issues, the SH79F6441 builds in Watchdog Timer, Low Voltage Reset function and system clock monitor. And SH79F6441 also supports two power saving modes to reduce power consumption.
  • Page 2: Block Diagram

    SH79F6441 3. Block Diagram Reset circuit Power Pipelined 8051 architecture Watch Dog 64K Bytes Flash ROM Port 5 Configuration I/Os Internal 256 Bytes P5.0 - P5.1 External 2816Bytes (Exclude System Port 4 Register) Configuration I/Os P4.0 - P4.7 Timer3 (16bit)
  • Page 3 SH79F6441 4. Pin Configration 4.1 LQFP44 Package 27 26 AN2/P0.4 P2.2/MOSI/RXD2 AN1/P0.3 P2.1/MISO/TXD2 AN0/P0.2 P2.0/SCK/P1CEX1 INT3/P0.1 P3.5/AN10 P0.0 P3.0/AN9/SS SH79F6441 INT47/P1.0 P3.1/INT0/ECI1 INT44/P1.1 P3.2/P1CEX0 P4.3 SWE/TDO/AN4/INT43/P1.2 P4.2 TMS/AN5/INT42/P1.3 TDI/AN6/INT41/P1.4 P4.1 TCK/AN7/INT40/P1.5 P4.0 9 10 Note: In pin designation, the pin function written on the outermost side has the highest priority and the innermost pin function has the lowest priority (see the pin configuration diagram).
  • Page 4 SH79F6441 4.2 LQFP32 Package AN0/P0.2 P2.4 INT3/P0.1 P2.3/VIN P0.0 P2.2/MOSI/RXD2 INT47/P1.0 SH79F6441 P2.1/MISO/TXD2 INT44/P1.1 P2.0/SCK/P1CEX1 SWE/TDO/AN4/INT43/P1.2 P3.5/AN10 TMS/AN5/INT42/P1.3 P3.0/AN9/SS TDI/AN6/INT41/P1.4 P3.1/INT0/ECI1 Note: In pin designation, the pin function written on the outermost side has the highest priority and the innermost pin function has the lowest priority (see the pin configuration diagram).
  • Page 5 SH79F6441 4.3 QFN32 Package AN0/P0.2 P2.4 INT3/P0.1 P2.3/VIN P0.0 P2.2/MOSI/RXD2 INT47/P1.0 SH79F6441 P2.1/MISO/TXD2 INT44/P1.1 P2.0/SCK/P1CEX1 SWE/TDO/AN4/INT43/P1.2 P3.5/AN10 TMS/AN5/INT42/P1.3 P3.0/AN9/SS TDI/AN6/INT41/P1.4 P3.1/INT0/ECI1 Note: In pin designation, the pin function written on the outermost side has the highest priority and the innermost pin function has the lowest priority (see the pin configuration diagram).
  • Page 6 SH79F6441 4.4 SOP28 Package SWE/TDO/AN4/INT43/P1.2 P0.2/AN0 P0.3/AN1 TMS/AN5/INT42/P1.3 P0.4/AN2 TDI/AN6/INT41/P1.4 TCK/AN7/INT40/P1.5 P0.5/AN3 T3/AVREF/AN8/P1.6 P0.6/ECI2 RST/P1.7 P0.7/INT1/P2CEX0 XTAL2/P3.3 P2.7/INT46/P2CEX1 XTAL1/P3.4 P2.6/INT45 P2.5/PWM2 P2.4 P1CEX0/P3.2 P2.3/VIN ECI1/INT0/P3.1 P2.2/MOSI/RXD2 SS/AN9/P3.0 P2.1/MISO/TXD2 AN10/P3.5 P2.0/SCK/P1CEX1 Note: In pin designation, the pin function written on the outermost side has the highest priority and the innermost pin function has the lowest priority (see the pin configuration diagram).
  • Page 7 SH79F6441 LCM (Logical Function Configuration Module) Pin Allocation Table Function UART0 UART1 PWM0 PWM1 INT2 PCA0 RXD0 TXD0 RXD1 TXD1 PWM0 PWM1 INT2 P0CEX0 P0CEX1 ECI0 ● ● ■ P0.0 ● ● P0.1 ● ● ● ● P0.2 ● ●...
  • Page 8 SH79F6441 5. Pin Description Pin No. Type Description I/O PORT P0.0-P0.7 8-bit bi-directional I/O port P1.0-P1.7 8-bit bi-directional I/O port P2.0-P2.7 8-bit bi-directional I/O port P3.0-P3.7 8-bit bi-directional I/O port P4.0-P4.7 8-bit bi-directional I/O port P5.0-P5.1 2-bit bi-directional I/O port...
  • Page 9 SH79F6441 (continue) PCA Controller P0CEX0 Input/output pin for PCA0 module 0 P0CEX1 Input/output pin for PCA0 module 1 ECI0 The external clock input for PCA0 P1CEX0 Input/output pin for PCA1 module 0 P1CEX1 Input/output pin for PCA1 module 1 ECI1...
  • Page 10 SH79F6441 6. SFR Mapping The SH79F6441 contains a 256-byte direct-addressed register, including general-purpose data memory and special function registers (SFR). The SH79F6441 has the following SFR: CPU Core Registers: ACC, B, PSW, SP, DPL, DPH Enhanced CPU Core Registers: AUXC, DPL1, DPH1, INSCON, XPAGE...
  • Page 11 SH79F6441 Table 6.1 C51 Core SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 /PIN Reset Value Accumulator 00000000 ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 B Register 00000000 AUXC C Register 00000000 Program Status Word...
  • Page 12 SH79F6441 Table 6.3 Flash Control SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 /PIN Reset Value IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF Offset Register for Programming 00000000 Bank0 SET.7 SET.6 SET.5 SET.4 SET.3 SET.2...
  • Page 13 SH79F6441 Table 6.6 Interrupt SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 /PIN Reset Value IEN0 Interrupt Enable Control 0 00000000 EADC EPCA1 EPCA0 Bank0 IEN1 Interrupt Enable Control 1 00000000 ESCM ELPD EPWM1 EPWM0 ETWI...
  • Page 14 SH79F6441 Table 6.8 Port SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 /PIN Reset Value 8-bit Port0 00000000 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 Bank0 8-bit Port1 00000000 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1...
  • Page 15 SH79F6441 Table 6.9 Timer SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 /PIN Reset Value T3CON Timer/Counter3 control 0-00-000 T3PS.1 T3PS.0 T3CLKS.1 T3CLKS.0 Bank1 Timer/Counter3 low byte 00000000 TL3.7 TL3.6 TL3.5 TL3.4 TL3.3 TL3.2 TL3.1 TL3.0...
  • Page 16 SH79F6441 (continue) SBRTL1 EUART1 baud rate generator low 00000000 SBRT1.7 SBRT1.6 SBRT1.5 SBRT1.4 SBRT1.3 SBRT1.2 SBRT1.1 SBRT1.0 Bank1 EUART1 baud rate generator SFINE1 ----0000 BFINE1.3 BFINE1.2 BFINE1.1 BFINE1.0 Bank1 fine tuning PCON1 Serial control register 1 00------ SMOD1 SSTAT1 Bank1...
  • Page 17 SH79F6441 Table 6.12 ADC SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 /PIN Reset Value —---—-----— ADCON1 ADC control1 00000000 ADON ADCIF REFC XTRGEN GO/DONE Bank0 TRGEN TRGEN TRGEN ADCON2 ADC control2 0000-000 GRP2 GRP1 GRP0...
  • Page 18 SH79F6441 (continue) Duty control high byte of PWM0DH ----0000 PWM0D.11 PWM0D.10 PWM0D.9 PWM0D.8 Bank0 12 byte PWM0 Duty control high byte of PWM0DL 00000000 PWM0D.7 PWM0D.6 PWM0D.5 PWM0D.4 PWM0D.3 PWM0D.2 PWM0D.1 PWM0D.0 Bank0 12 byte PWM0 Duty control high byte of...
  • Page 19 SH79F6441 (continue) PCA1 Capture/ P1CPM1 00000000 P1SMP1 P1SMN1 P1FSP1 P1FSN1 P1ECOM1 P1TCP1 P1MAT1 P1ECCF1 Bank1 Compare Module 1 register P1TOPL PCA1 Count Maximum Low Byte 11111111 P1TOPL.7 P1TOPL.6 P1TOPL.5 P1TOPL.4 P1TOPL.3 P1TOPL.2 P1TOPL.1 P1TOPL.0 Bank1 P1TOPH 11111111 P1TOPH.7 P1TOPH.6 P1TOPH.5 P1TOPH.4...
  • Page 20 SH79F6441 Table 6.15 LPD SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 /PIN Reset Value LPDCON LPD control register 00000--- LPDEN LPDF LPDV LPDIF LPDMD Bank0 LPDSEL LPD level selection register ----0000 LPDS3 LPDS2 LPDS1 LPDS0 Bank0 Table 6.16 CRC SFRs...
  • Page 21 SH79F6441 SFR Map Bank0 Non Bit addressable addressable SPSTA IB_OFFSET IB_DATA AUXC IB_CON1 IB_CON2 IB_CON3 IB_CON4 IB_CON5 XPAGE EXF0 P0PCR P1PCR P2PCR P3PCR P4PCR P0CR P1CR P2CR P3CR P4CR TWITOUT EXF1 PIMS1 PIMS2 CRCSTOL CRCSTOH TWISTA PIMS0 CRCSTAL CRCSTAH TWICON...
  • Page 22 SH79F6441 7. Normal Function 7.1 CPU 7.1.1 CPU Core Special Function Register Feature  CPU core registers: ACC, B, PSW, SP, DPL, DPH Accumulator Accumulator ACC is a commonly used special register. A is used as an mnemonic for the accumulator in the instruction system.
  • Page 23 Enhanced CPU core registers: AUXC, DPL1, DPH1, INSCON The SH79F6441 has modified 'MUL' and 'DIV' instructions. These instructions support 16 bits operand. A new register - the register is applied to hold the upper part of the operand/result. The AUXC register is used during 16 bits operand multiply and divide operations.
  • Page 24 256 bytes RAM; MOVX A, @DPTR or MOVX @DPTR, A also to access external 2816 bytes RAM. In SH79F6441 the user can also use XPAGE register to access external RAM only with MOVX A, @Ri or MOVX @Ri, A instructions.
  • Page 25 0000H Program Memory Block Information Block The SH79F6441 embeds 64K flash program memory for program code. The flash program memory provides electrical erasure and programming and supports In-Circuit Programming (ICP) mode and Self-Sector Programming (SSP) mode.Every sector is 512 bytes.
  • Page 26 SH79F6441 (2) Mass Erase Regardless of the state of the code protection control mode, the overall erasure operation will erase all programs, code options, the code protection bit, but they will not erase EEPROM-like memory block. The user must use the following way to complete the overall erasure: Flash programmer in ICP mode send overall erasure instruction to run overall erasure.
  • Page 27 SH79F6441 7.3.2 Flash Operation in ICP Mode Single Line Simulation Model ICP mode is to program MCU through Flash programmer, which can be programmed after MCU is welded to the user board. In ICP mode, the user system must be power-off, and the programmer can refresh the program memory through ICP programming interface.
  • Page 28 SH79F6441 7.3.3 Register Table 7.4 Access Control Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 FLASHCON CRC_FAC Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Reserved CRC access control CRC_FAC 0: CRC verification of MAIN Block area 1: CRC verification of EEPROM-like area...
  • Page 29 The SH79F6441 builds in a complex control flow to prevent the code from carelessly modification.To enter the SSP mode, IB_CON2-5 must meet certain conditions. If the dedicated conditions are not met (IB_CON2-5), the SSP will be terminated.
  • Page 30 SH79F6441 Table 7.8 Programming Data Register FCH, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IB_DATA IB_DATA.7 IB_DATA.6 IB_DATA.5 IB_DATA.4 IB_DATA.3 IB_DATA.2 IB_DATA.1 IB_DATA.0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description IB_DATA[7:0] Data to be programmed Table 7.9 SSP Operation select Register...
  • Page 31 SH79F6441 Table 7.12 SSP Flow Control Register3 F5H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IB_CON4 IB_CON4.3 IB_CON4.2 IB_CON4.1 IB_CON4.0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description IB_CON4[3:0] Must be 09H, otherwise Flash Programming will terminate Table 7.13 SSP Flow Control Register4...
  • Page 32 SH79F6441 7.4.2 Flash Control Flow Set IB_OFFSET Set XPAGE Set IB_DATA Set IB_CON1 IB_CON2[3:0]≠5H Set IB_CON2[3:0]=5H IB_CON2≠5H IB_CON3≠AH IB_CON2≠5H Set IB_CON3=AH ELSE IB_CON3≠AH Set IB_CON4=9H IB_CON4≠9H Reset IB_CON1-5 Set IB_CON5=6H Sector Erase IB_CON1=E6H &IB_CON2[3:0]=5H &IB_CON3=AH &IB_CON4=9H &IB_CON5=6H IB_CON1=6EH &IB_CON2[3:0]=5H &IB_CON3=AH &IB_CON4=9H...
  • Page 33 SH79F6441 7.4.3 SSP Programming Note To successfully complete SSP programming, the user’s software must following the steps below: (1) Code/DataProgramming: 1. Disable interrupt; 2. Fill in the XPAGE, IB_OFFSET for the corresponding address; 3. Fill in IB_DATA if programming is needed;...
  • Page 34 7.4.4 Readable Identificantion Code Each chip of the SH79F6441 is factory-hardened with a 40-bit readable identification code. Its value is a random value of 0 - 0xffffffffff. It cannot be erased (stored in the address information memory area 0x127b - 127f) and can be read by program and program tool.
  • Page 35 (24MHz/128KHz), External Clock (128kHz - 16MHz), which is selected by code option OP_OSC (Refer to code option section for details). SH79F6441 has 2 Oscillator pins (XTAL1, XTAL2), which can generates one or two clock sources from three oscillator types. It is selected by code option OP_OSC (Refer to code option section for details). The oscillator generates the basic clock pulse that provides the system clock to supply CPU and on-chip peripherals.
  • Page 36 SH79F6441 7.5.4 Register Table 7.15 System Clock Control Register B2H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CLKCON 32k_SPDUP CLKS1 CLKS0 SCMIF HFON AHUM Reset Value OP_AHRV (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description 32.768kHz oscillator speed up mode control bit 0: 32.768kHz oscillator normal mode, cleared by software.
  • Page 37 SH79F6441 7.5.5 Oscillator Type (1) OP_OSC = 0000, 0011: Internal 24M/128K RC, XTAL shared with IO. XTAL1 XTAL2 (2) OP_OSC = 1010: 32.768kHz Crystal Oscillator from XTAL input, internal 24M RC Oscillator can be enabled. XTAL1 32.768kHz XTAL2 (3) OP_OSC = 1110: 2M - 16M Crystal/Ceramic Oscillator input from XTAL.
  • Page 38 The SH79F6441 internal resonator drive circuit uses the industry-standard Pierce oscillator. It has the features of low power consumption, low cost, and good stability, so it is common in common applications. The equivalent circuit is shown below:...
  • Page 39 The resonator constants in the above table are based on the resonator model parameters referenced in the design of the SH79F6441 internal resonator drive circuit. In practical applications, this parameter can be used as a reference for selecting a resonator, and the resonator manufacturer is invited to evaluate the circuit design.
  • Page 40 7.5.9 Reminder Peripheral Circuit Design Considerations (1) When choosing a crystal resonator and a ceramic resonator, ask the resonator manufacturer to confirm whether the resonator constant matches the resonator constant verified by the SH79F6441 design simulation. (2) The value of C...
  • Page 41 7.6 System Clock Monitor (SCM) In order to enhance the reliability of the system, SH79F6441 contains a system clock monitoring (SCM) module. If the system clock fails (for example, external oscillator stops, etc.), the built-in SCM module will automatically switch OSCSCLK to the internal clock and the system clock monitor flag (SCMIF) will be set.
  • Page 42  Share with alternative functions The SH79F6441 has 42/30/26 bi-directional I/O ports. The PORT data is put in Px register. The PORT control register (PxCRy) controls the PORT as input or output. Each I/O port has an internal pull-high resistor, which is controlled by PxPCRy when the PORT is used as input (x = 0-5, y = 0-7).
  • Page 43 SH79F6441 Table 7.19 Port Data Register 80H - C0H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 P0 (80H, Bank0) P1 (90H, Bank0) P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 P2 (A0H, Bank0) P2.7...
  • Page 44 SH79F6441 Table 7.21 Port Input Mode Select Register (PIMS1) D9H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PIMS1 P27S P26S P25S P24S P43S P42S P34S P33S Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description P2.7 input level logic control bit (not including port data register input) * 0: input high level threshold of 0.8V...
  • Page 45 SH79F6441 7.7.3 Port Diagram SFEN PxPCRy Output Mode Input Mode 0 = ON (Pull-up) PxCRy 1 = OFF I/O Pad Write Data Data Bus Register Read Port Data Register Read Read Data Register/Pad Selection 0: From Pad 1: From data register...
  • Page 46 SH79F6441 (continue) The CH0 bit in the ADCH1 register and the ADON bit in the ADCON1 register are both set to 1, and the corresponding bit in SEQCHX[3:0] is set to 1 P0.2 None of the above The CH1 bit in the ADCH1 register and the ADON bit in the ADCON1...
  • Page 47 SH79F6441 (continue) Single-wire emulation communication pin Debug interface The CH4 bit in the ADCH1 register and the ADON bit in the ADCON1 register are both set to 1, and the corresponding bit in SEQCHX[3:0] is set to 1 The EX4 bit of the IEN1 register and the EXS43 bit of the IENC register INT43 are set to 1.
  • Page 48 SH79F6441 PORT2: - P1CEX1: PCA1 Compare Capture Pin 1 (P2.0) -SCK: SPI Serial Clock (P2.0) - TXD2: EUART data output (P2.1) - MISO: SPI Master Input Slave Output (P2.1) - RXD2: EUART data input (P2.2) - MOSI: SPI Master Output Slave Input (P2.2) - VIN: LPD detection voltage input (P2.3)
  • Page 49 SH79F6441 PORT3: ——— - SS : SPI subordination (P3.0) - AN9: ADC Input Channel (P3.0) - ECI0: PCA0 clock input (P3.1) - INT0: External Interrupt Input (P3.1) - P1CEX0: PCA1 Compare Capture Pin 0 (P3.2) - XTAL2: Resonator output (P3.3) - XTAL1: Resonator input (P3.4)
  • Page 50 SH79F6441 7.8 Timer 7.8.1 Timer3 Timer 3 is a 16-bit auto-reload timer accessed via two data registers, TH3 and TL3, controlled by the T3CON register. Setting the ET3 bit of the IEN0 register allows Timer 3 interrupts (see the Interrupts section for details).
  • Page 51 SH79F6441 7.8.2 Register Table 7.28 Timer3 Control Register 88H, Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 T3CON T3PS.1 T3PS.0 T3CLKS.1 T3CLKS.0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Timer3 overflow flag bit 0: No overflow (cleared by hardware)
  • Page 52 7.9 Programmable Counter Array (PCAx (x = 0、1、2)) 7.9.1 Feature  SH79F6441 has three 16-bit timer PCA, PCA0 - 2 has two independent comparison capture module  Can achieve phase correction, phase frequency correction The Programmable Counter Array (PCAx) provides enhanced timer functionality while requiring less CPU intervention than the standard 8051 counter/timers.The PCAx consists of a dedicated 16-bit counter/timer and two 16-bit capture/compare modules.
  • Page 53 SH79F6441 The 16-bit PCAx counter/timer has an integrated 16-bit counter. The 16-bit counter overflow register consists of PxTOPH and PxTOPL. The user can freely configure the PxTOP (x = 0, 1, 2) register to define the counter overflow value. The initial value of the PxTOP register is 0xFFFF.
  • Page 54 SH79F6441 The working methods are selected as shown in the following table: PCAx Mode Select Table Mode PxSDEN PxSMPn PxSMNn PxFSPn PxFSNn Function Capture triggered by positive edge (singleslope) Mode0 Capture triggered by negative edge on (singleslope) Capture triggered by transition (singleslope)
  • Page 55 SH79F6441 7.9.2 Mode0: Edge-triggered Capture Mode In this mode, a valid transition on the PxCEXn pin causes the PCAx to capture the value of the PCAx counter/timer and load it into the corresponding module's 16-bit capture/compare register (PxCPLn and PxCPHn). The PxFSPnand PxFSNnbits in...
  • Page 56 SH79F6441 7.9.3 Mode1: Software Timer Mode The software timer mode is also referred to as the compare output mode (this mode is enabled by configuring PxSMPn:PxSMNn = 01). In this mode, PxFSPn:PxFSNn = 0x, which enables continuous software timing. PCAx compares the counter/timer count value with the module's 16-bit capture/compare registers (PxCPHn and PxCPLn).
  • Page 57 SH79F6441 7.9.4 Mode2: Frequency Output Mode The frequency output mode generates a square wave of programmable frequency on the module's PxCEXn pin (configure PxSMPn:P0SMNn = 10 to enable this mode, in which the update of the PxCPn register does not use the double buffering mechanism).
  • Page 58 SH79F6441 7.9.5 Mode3: PWM Mode Each PCAx module can be used independently to generate a pulse width modulated (PWM) output. Configuring PxSMPn:PxSMNn = 11 will enable compare/capture module n to operate in PWM mode. In this mode, configuring the PxFSPn and PxFSNn bits enables the compare/capture module n to operate in one of four PWM functions.
  • Page 59 SH79F6441 As shown in Figure 7.9-9 below, period 1 is the default value of PxCEXn pin.when period 1 is PxCPLn = 00H, PxCEXn pin output level; when the period 2-4 is PxCPLn = 01H, 80H and FEH respectively, the waveform of corresponding duty ratio of PxCEXn pins.
  • Page 60 SH79F6441 Duty Ratio Duty = (PxTOP - PxCPn)/(PxTOP + 1) for 16-Bit PWM Mode The output waveform is shown in Figure 7.9-11. The period 1 is the default value of the PxCEXn pin.When period 1 is PxCPn = 0000H, PxCEXn pin output level; The waveform of corresponding duty ratio of PxCEXn pins when period 2-4 is PxCPn = 0001H, 8000H and FFFEH respectively;...
  • Page 61 SH79F6441 Compared to single ramp operation, the maximum frequency available for double ramp operation is smaller. However, Its symmetrycharacteristics areverysuitable formotor control. The PWM resolution of phase-corrected PWM mode can be defined by PxTOP. The minimum resolution is 2 bits (PxTOP is set to 0x0003) and the maximum resolution is 16 bits.
  • Page 62 SH79F6441 The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The main difference between the phasefrequency correction PWM mode and the phase correction PWM mode is the update time of the PxCPn and PxTOP registers.
  • Page 63 SH79F6441 7.9.6 Register Table 7.30 PCAx Flag Register Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P0CF (98H) P0CCF1 P0CCF0 P1CF (C0H) P1CCF1 P1CCF0 P2CCF1 P2CCF0 P2CF (C8H) RESET Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description PCAx Counter/Timer Overflow Flag Set by hardware when the PCAx Counter/Timer overflows from 0xFFFF to 0x0000.
  • Page 64 SH79F6441 Table 7.32 PCAx Mode Register Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P0CMD (99H) ECF0 P0SDEN P0CPS2 P0CPS1 P0CPS0 P1CMD (C1H) ECF1 P1SDEN P1CPS2 P1CPS1 P1CPS0 P2CMD (C9H) ECF2 P2SDEN P2CPS2 P2CPS1 P2CPS0 RESET Value (POR/WDT/LVR/PIN) Bit Number...
  • Page 65 SH79F6441 (continue) PxSMPn: PxSMNn = 00: capture mode select 0X: The compare/capture module n work in the positive edge triggered mode 10: The compare/capture module n work in the negative edge triggered mode PxFSPn 11: The compare/capture module n work in any edge triggered mode...
  • Page 66 SH79F6441 Table 7.34 PxFORCE Forced Output Control Register Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P0FORCE (DCH) P0OSC1 P0OSC0 P0FCO1 P0FCO0 P1FORCE (BDH) P1OSC1 P1OSC0 P1FCO1 P1FCO0 P2FORCE (BEH) P2OSC1 P2OSC0 P2FCO1 P2FCO0 RESET Value (POR/WDT/LVR/PIN) Bit Number...
  • Page 67 SH79F6441 Table 7.36 PCAx Count Maximum High Byte Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P0TOPH (9EH) P0TOPH.7 P0TOPH.6 P0TOPH.5 P0TOPH.4 P0TOPH.3 P0TOPH.2 P0TOPH.1 P0TOPH.0 P1TOPH (C6H) P1TOPH.7 P1TOPH.6 P1TOPH.5 P1TOPH.4 P1TOPH.3 P1TOPH.2 P1TOPH.1 P1TOPH.0 P2TOPH (CEH) P2TOPH.7 P2TOPH.6 P2TOPH.5 P2TOPH.4 P2TOPH.3 P2TOPH.2 P2TOPH.1 P2TOPH.0...
  • Page 68 1 timer interrupts (Timer3), 3 PCA0-2 interrupts, 3 EUART interrupts, SCM interrupt, 1 SPI interrupt, 1 ADC interrupt, 3 PWM interrupts, 1 TWI interrupt, 1 CRC interrupt, 1 LPD interrupt. The SH79F6441 have 4 interrupt priority levels, which make operating 21 interrupt sources becoming flexible.
  • Page 69 SH79F6441 Table 7.41 Interrupt Enable Register 1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IEN1 ESCM ELPD EPWM1 EPWM0 ETWI Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description SCM interrupt enable bit ESCM 0: Disable SCM interrupt 1: Enable SCM interrupt...
  • Page 70 SH79F6441 Table 7.42 Interrupt Enable Register2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IEN2 EPCA2 ESPI EPWM2 ECRC Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description PCA2 interrupt enable bit EPCA2 0: Disable PCA2 interrupt 1: Enable PCA2 interrupt...
  • Page 71 SH79F6441 7.10.3 Interrupt Flag Each Interrupt source has its own interrupt flag, when interrupt occurs, corresponding flag will be set by hardware, the interrupt flag bits are listed in Table bellow. For external Interrupt INT0/1, When External Interrupt INTx (x = 0, 1) is generated, if the interrupt is edge triggered, the CPU clears the flag IEx (x = 0, 1) if the interrupt is acknowledged by the CPU;...
  • Page 72 SH79F6441 Table 7.44 External Interrupt Flag Register E8H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EXF0 IT4.1 IT4.0 IT3.1 IT3.0 IT2.1 IT2.0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description External interrupt4 trigger mode selection bits 00: Low Level trigger...
  • Page 73 SH79F6441 7.10.4 Interrupt Vector When an interrupt occurs, the program counter is pushed onto the stack and the corresponding interrupt vector address is loaded into the program counter. The interrupt vector addresses are listed in Interrupt Summary table. 7.10.5 Interrupt Priority Each interrupt source can be individually programmed to one of four priority levels by setting or clearing corresponding bits in the interrupt priority control registers IPL0, IPH0, IPL1, and IPH1.
  • Page 74 SH79F6441 7.10.6 Interrupt Handling The interrupt flags are sampled and polled at the fetch period of each machine period. All interrupts are sampled at the rising edge of the clock. If one of the flags was set, the CPU will find it and the interrupt system will generate a LCALL to the appropriate service routine, provided this hardware-generated LCALL is not blocked by any of the following conditions: An interrupt of equal or higher priority is already in progress.
  • Page 75 7.10.8 External Interrupt Input The SH79F6441 has 5 external interrupt inputs. External interrupt 0-3 every has one vector address. External interrupt 4 has 8 inputs, all of them share one vector address. External interrupt 0/1 can be selected as a level trigger or an edge trigger by setting the IT1, IT0 bits in the TCON register.
  • Page 76 SH79F6441 Table 7.47 External Interrupt Sample Times Control Registrer 8BH, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EXCON I1PS1 I1PS0 I1SN1 I1SN0 I0PS1 I0PS0 I0SN1 I0SN0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description INT4 sample clock Prescaler Select bits...
  • Page 77 SH79F6441 7.10.9 Interrupt Summary Source Vector Address Enable bits Flag bits Polling Priority Interrupt No. (C51) Reset 0000H 0 (Highest) INT0 0003H PCA0 000BH ECF0 INT1 0013H PCA1 001BH ECF1 EUART0 0023H RI+TI Timer3 002BH 0033H EADC ADCIF 003BH ETWI...
  • Page 78  Selectable output polarity The SH79F6441 has three 12-bit PWM module. Which can provide three channel pulse width modulation waveform with the period and the duty being controlled individually by corresponding register. PWMxEN (x = 0-2) used to enable PWM modules.
  • Page 79 SH79F6441 Table 8.2 PWMx Period Register PWMxPH/L (x = 0-2) Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWM0PH (CDH) PWM0P.11 PWM0P.10 PWM0P.9 PWM0P.8 PWM0PL (CCH) PWM0P.7 PWM0P.6 PWM0P.5 PWM0P.4 PWM0P.3 PWM0P.2 PWM0P.1 PWM0P.0 PWM1PH (AFH) PWM1P.11 PWM1P.10 PWM1P.9 PWM1P.8...
  • Page 80 The mode provides synchronous communication with external devices. In this mode serial data is transmitted and received on the RXDx line. TXDx is used to output the shift clock. The TXDx clock is provided by the SH79F6441 whether the device is transmitting or receiving.
  • Page 81 SH79F6441 Any instruction that uses SBUFxas a destination register (“write to SBUFx” signal) will start the transmission. The next system clock tells the Tx control block to commence a transmission. The data shift occurs at the falling edge of the SHIFT CLOCK, and the contents of the transmit shift register is shifted one position to the right.
  • Page 82 SH79F6441 Transmission begins with a “write to SBUFx” signal, and it actually commences at the next system clock following the next rollover in the divide-by-16 counter (divide baud-rate by 16), thus, the bit times are synchronized to the divide-by-16 counter, not to the “write to SBUFx”...
  • Page 83 SH79F6441 Mode2: 9-Bit EUARTx, Fixed Baud Rate, Asynchronous Full-Duplex The mode provides the 11 bits full duplex asynchronous communication. The 11 bits consists of one start bit (logical 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logical 1). Mode 2 supports multiprocessor communications and hardware address recognition (Refer to Multiprocessor Communication Section for details).
  • Page 84 SH79F6441 Reception is enabled only if RXDx is high. The serial port actually starts the receiving of serial data, with the detection of a falling edge on the RXDxpin. For this purpose RXDx is sampled at the rate of 16 times baud rate. When a falling edge is detected, the divide-by-16 counter is immediately reset.
  • Page 85 SH79F6441 8.2.3 Baud Rate Generate EUARTx with own baud rate generator, the baud rate generator is an 15-bit up-counting timer. Overflow 15-bit timer To EUART Fsys From 7FFFH to 0000H SBRTEN=1 SBRTH[14:8],SBRTL7:0] Baudrate Generator for EUART The overflow rate of baud rate generator can be calculated as follow:...
  • Page 86 SH79F6441 8.2.4 Multi-Processor Communication Software Address Recognition Modes 2 and 3 of the EUARTx have a special provision for multi-processor communication. In these modes, 9 data bits are received. The 9th bit goes into RB8. Then a stop bit follows. The EUARTx can be programmed such that when the stop bit is received, the EUARTx interrupt will be activated (i.e.
  • Page 87 SH79F6441 8.2.5 Error Detection Error detection is available when the SSTAT bit in register PCON is set to logic 1. All the 3 bits should be cleared by software after they are set, even when the following frames received without any error will not be cleared automatically.
  • Page 88 SH79F6441 Table 8.5 EUART0 Control and Status Register 98H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCON /RXOV /TXCOL Reset Value (POR/WDT/LVR/PIN) Bit Mnemonic Description EUART0 Serial mode control bits, when SSTAT = 0 00: Mode 0, Synchronous Mode, fixed baud rate...
  • Page 89 SH79F6441 Table 8.6 EUART0 Data Buffer Register 99H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SBUF SBUF.7 SBUF.6 SBUF.5 SBUF.4 SBUF.3 SBUF.2 SBUF.1 SBUF.0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description This SFR accesses two registers; a transmit shift register and a receive latch...
  • Page 90 SH79F6441 Table 8.10 EUART1 Control & Status Register A0H, Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SM10 SM11 SM12 SCON1 REN1 TB81 RB81 /FE1 /RXOV1 /TXCOL1 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description EUART1 Serial mode control bits, when SSTAT1 = 0...
  • Page 91 SH79F6441 Table 8.11 EUART1 Data Buffer Register A7H, Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PCON1 SMOD1 SSTAT1 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description EUART1 Baud rate doubler SMOD1 0: In Mode2, the baud-rate of EUART is 1/64 of the system clock...
  • Page 92 SH79F6441 Table 8.14 EUART1 Baudrate Generator Register A5H-A4H, Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SBRTH1 (A5H) SBRTEN1 SBRT1.14 SBRT1.13 SBRT1.12 SBRT1.11 SBRT1.10 SBRT1.9 SBRT1.8 SBRT1.7 SBRT1.6 SBRT1.5 SBRT1.4 SBRT1.3 SBRT1.2 SBRT1.1 SBRT1.0 SBRTL1 (A4H) Reset Value (POR/WDT/LVR/PIN)
  • Page 93 SH79F6441 (continue) EUART2 Multi-processor communication enable bit (9 bit ‘1’ checker), when SSTAT2 = 0 0: In Mode0, baud-rate is 1/12 of system clock In Mode1, disable stop bit validation check, any stop bit will set RI2 to generate interrupt SM22 In Mode2 &...
  • Page 94 SH79F6441 Table 8.18 EUART2 data buffer register 91H, Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SBUF2 SBUF2.7 SBUF2.6 SBUF2.5 SBUF2.4 SBUF2.3 SBUF2.2 SBUF2.1 SBUF2.0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description This register addresses two registers: a shift register and a receive latch register...
  • Page 95  System in Idle state can be Wake-up  Programmable Slave Address The TWI Interface complete the transition with SDA and SCL, between Master and Slaver.SH79F6441 has the ability to process and transmit byte, and track the serial transaction automaticly, which conforms to TWI protocol.
  • Page 96 STOP SH79F6441 generates an ACK by pulling the SDA line low. After the interrupt flag be set, SH79F6441 pulls the SCL line low, and releases SDA line.When the interrupt process has completed, SCL line should be released and TWINT flag should be...
  • Page 97 SH79F6441 Data Arbitration A master may start a transfer only if the bus is free. Two or more masters may generate a START condition within the minimum hold time(tHOLD:STA)of the START condition which results in a defined START condition to the bus.
  • Page 98 /2)as idle mode, releasing the Bus. The function is only used in the transmission process of one packet (8 + 1 bit). When SH79F6441 is in slave transfer mode and the first byte of transferred message is low, the function can be used. STA and RSTA is not situable for this function. If SH79F6441 generates interrupt, TFREE bit in TWICON regiser will be set (if control bit EFREE bit has been set).
  • Page 99 SH79F6441 Master Transmitter Mode In the Master transmitter mode, a number of data bytes are transmitted to a slave receiver. In order to enter a master mode, a START condition must be transmitted.Then if SLA+W is transmitted, MT mode is entered.
  • Page 100 Arbitration lost in slave Ack or Nack Ack or Nack address or data byte Other Master Other Master Continue Continue Arbitration lost and addressed as slave To Corresponding state in slave mode 68H/78H/B0H Other Device Actions SH79F6441 Actions...
  • Page 101 SH79F6441 Master Receiver Mode In the Master transmitter mode, a number of data bytes are transmitted to a slave receiver. In order to enter a master mode, a START condition must be transmitted.Then if SLA+R is transmitted, MR mode is entered.
  • Page 102 Transmitter after a data byte Arbitration lost in slave Ack or address or not acknowledged Nack Other Master Other Master Continue Continue Arbitration lost and addressed as slave To Corresponding state in slave mode Other Device Actions 68H/78H/B0H SH79F6441 Actions...
  • Page 103 STA, STO, and TWINT; the upper 7 bits of the address register TWIADR prepare the corresponding address for SH79F6441. If GC is set, SH79F6441 will also respond to the general address (00H); otherwise it will not respond to the general address.
  • Page 104 STA, STO and TWINT; the upper 7 bits of the address register TWIADR prepare the corresponding address for SH79F6441. If GC is set, SH79F6441 will also respond to the general address (00H); otherwise it will not respond to the general address.
  • Page 105 SH79F6441 (continue) Arbitration lost in SLA + Receive data byte; Transmit NACK R/W as master; General No TWIDAT address has been action received; Receive data byte; Transmit ACK ACK has been received Previously addressed Receive data byte; Transmit NACK with own SLA address;...
  • Page 106 TWINT is set. You can restore normal communication by setting STO and clearing the TWINT flag. The SH79F6441 will enter the non-addressable slave mode and automatically clear the STO flag. The data and clock lines will be released, and there is no stop condition on the line.
  • Page 107 SH79F6441 8.3.5 Register Table 8.22 TWI Control Register C8H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TWICON TOUT ENTWI TWINT TFREE EFREE Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Bus timeout flag 0: No timeout occurred TOUT 1: Set when the TWI bus low level exceeds N X T .
  • Page 108 SH79F6441 Table 8.23 TWI Bus Timeout Count Register E6H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TWITOUT CNT1 CNT0 TWIPCR Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Bus Timeout Count 00:N = 25000 01:N = 50000 CNT[1:0]...
  • Page 109 Bit Number Bit Mnemonic Description TWI address configuration bit TWIADR[6:0] Address when SH79F6441 is configured as a slave General Address Enable Bit 0: Disable response to general address 1: Enable response to general address Table 8.28 TWI Data Register 8DH, Bank0...
  • Page 110 SH79F6441 8.4 Serial External Device Interface (SPI) 8.4.1 Features  Full-duplex, three-wire synchronous transmission  Master and slave operation  8 programmable master clock frequencies  Polar phase programmable serial clock  Main mode failure error flag with MCU interrupt ...
  • Page 111 SH79F6441 8.4.3 Baud Rate In master mode, the baud rate of the SPI has six selectable frequencies, which are 4, 8, 16, 32, 64, or 128 divisions of the internal clock, which can be set via the SPR[2:0] of the SPCON register bit to choose.
  • Page 112 SH79F6441 8.4.5 Work Mode The SPI can be configured as one of master mode or slave mode. The configuration and initialization of the SPI module is done by setting the SPCON register (serial peripheral control register) and SPSTA (serial peripheral status register). After the configuration is completed, data transmission is completed by setting SPCON, SPSTA, and SPDAT (Serial Peripheral Device Data Registers).
  • Page 113 SH79F6441 8.4.6 Transmission Form By setting the CPOL bit and CPHA bit in the SPCON register using software, the user can select four combinations of SPI clock polarity and phase. The CPOL bit defines the polarity of the clock, It is the idle state, which has little effect on the SPI transmission format.
  • Page 114 SH79F6441 8.4.7 Error Detection The flag in the SPSTA register indicates an error condition in SPI communication: (1) Mode Failure (MODF) A mode fault error in SPI master mode indicates that the level state on the SS pin is inconsistent with the actual device mode.
  • Page 115 SH79F6441 8.4.9 Register Table 8.30 SPI Control Register A2H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SPCON MSTR CPHA CPOL SSDIS SPR2 SPR1 SPR0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Direction of transmission selection 0: MSB first sent...
  • Page 116 SH79F6441 Table 8.31 SPI Status Register F8H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SPSTA SPEN SPIF MODF WCOL RXOV Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description SPI control bit SPEN 0: Disable SPI interface 1: Enable SPI interface...
  • Page 117 SH79F6441 8.5 Logic Configurable Module(LCM) 8.5.1 Features  Though the Logic Configurable Module 12 kinds of Logic function port can be remap to I/O, and each function can choose one of the eight IO to map. The Logic Configurable Module( LCM) used to realize the remap of some logic function port, and keep the one-to-one match between logic and hardware.
  • Page 118 SH79F6441 Function UART0 UART1 PWM0 PWM1 PCA0 INT2 RXD0 TXD0 RXD1 TXD1 PWM0 PWM1 P0CEX0 P0CEX1 ECI0 INT2 ● ● ■ P0.0 ● ● P0.1 ● ● ● ● P0.2 ● ● ● P0.3 ● ■ ● P0.4 ■ ●...
  • Page 119 SH79F6441 8.5.2 Register Table 8.33 TXD0 and RXD0 Selection Register C4H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 UART0CR TX0CR2 TX0CR1 TX0CR0 RX0CR2 RX0CR1 RX0CR0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description TXD0 Selection Bits 000: TXD0 map to P0.0 001: TXD0 map to P0.1...
  • Page 120 SH79F6441 Table 8.35 SCK and SDA selection register C6H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TWICR SCKCR2 SCKCR1 SCKCR0 SDACR2 SDACR1 SDACR0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description SCK Selection Bits 000: SCL map to P0.2 001: SCL map to P0.3...
  • Page 121 SH79F6441 Table 8.37 P0CEX1 and P0CEX0 Selection Register CBH, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CEXCR CE1CR2 CE1CR1 CE1CR0 CE0CR2 CE0CR1 CE0CR0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description P0CEX1 Selection Bits 000: P0CEX1 map to P0.3 001: P0CEX1 map to P1.6...
  • Page 122  INT2 (rising-edge, falling-edge, double-edge), the overflow of PCA0, PWM1 or Timer3 can trigger an ADC conversion.  ADC conversion rate up to 1MSPS The SH79F6441 includes a single ended, 12-bit SAR Analog to Digital Converter (ADC Analog-to-Digit Converter). Moduleas shown in Figure 8.6-1. After reset, the default reference voltage of ADC is V .
  • Page 123 SH79F6441 8.6.2 ADC Diagram Software Trigger Event Trigger sequence mode SEQCH0 State pointer GRP[2:0] SEQCHn SEQCH7 Mode Arbiter ADD0L/H CH13 12-Bits ADDnL/H ADD7L/H (1.20V) CH8/VREF ADC_Clk Time Gap Refc Logic Pre-Counter for ADC clock,4-bit ADCON1[REFC] SOC Stands for Start of Convertion...
  • Page 124 SH79F6441 8.6.3 ADC Register The registers of ADC moldule are as follows: Function Name Register Description ADC Clock Register Configuration of ADC clock, sample time Enable of ADC module, start a conversion, reference voltage selection, ADCON1 trigger mode and sources, interrupt flag...
  • Page 125 SH79F6441 For Example: System Clock TADC[2:0] TS[3:0] Sample Time Conversion Time SYSCLK 0000 0.083*1=0.083us 0000 2*0.083=0.166us 14*0.083+0.166=1.328us 0000 0.083*1=0.083us 0111 8*0.083=0.664us 14*0.083+0.664=1.826us 0000 0.083*1=0.083us 1111 15*0.083=1.245us 14*0.083+1.245=2.407us 12MHz 1111 0.083*192=15.936us 0000 2*15.936=31.872us 14*15.936+31.872=254.976us 1111 0.083*192=15.936us 0111 8*15.936=127.488us 14*15.936+127.488=350.592us 1111 0.083*192=15.936us 1111 15*15.936=239.04us...
  • Page 126 SH79F6441 (continue) TIMER3 Overflow Trigger Sequence Enable Bit TIMTRGEN 0: Disable the function 1: Enable Timer3 overflow trigger conversion ADC Status Flag bit 0: Automatically cleared by hardware when AD convert is completed. Clearing —---—-----— this bit during converting time will stop current conversion.
  • Page 127 SH79F6441 Table 8.42 Map Control Register 91H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SEQCON REG2 REG1 REG0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description ADC result left & right aligned selection bit 0: The 12-bits result stored in result register ADDxL/H (x = 0 - 7) are stored in left aligned.
  • Page 128 SH79F6441 Table 8.44 ADC Channel Configure Register 2 A6H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADCH2 CH13 CH12 CH11 CH10 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Channel Configuration bit CH[13:8] 1: P1.6, P3.0, P3.5 - P3.7, P5.0 as ADC input port 0: P1.6, P3.0, P3.5 - P3.7, P5.0 as I/O port...
  • Page 129 SH79F6441 Table 8.46 ADC Result Rgister x (x = 0 - 7) Left Alignment Mode: 96H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADDxL Reset Value (POR/WDT/LVR/PIN) 97H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADDxH...
  • Page 130 SH79F6441 The Approach for AD Conversion by software: (1) Select referent voltage; (2) Set sequence, including the number of channels and analog input channel; (3) Enable ADC module; ———— (4) Set GO/DONE to1,start ADC conversion; ———— (5) Wait until GO/DONE = 0 or ADCIF = 1, if the ADC interrupt is enabled, the ADC interrupt will occur, user need clear ADCIF by software;...
  • Page 131 SH79F6441 8.6.4 Sequence Conversion Mode The ADC sequence consist of one or more channels, the conversion of sequence is to convert the channels in the sequence one by one. It makes multiple signals to convert at the same time become possible in hardware. (the minmum sampling gap between two channels is 1us,so it can be regard as at the same time approximately) The conversion result is stored in the corresponding result register ADDxL/H (x = 0 - 7), the result register is read only register.
  • Page 132 SH79F6441 GRP[2:0]=2 Result SEQCH0 =5 ADD0L/H SEQCH1= 2 ADD1L/H SEQCH2 = 8 ADD2L/H SEQCH3 = x ADD3L/H sequencer SEQCH6 = x ADD6L/H SEQCH7 = x ADD7L/H Figure 8.6-4 The Configuration of Gap Time between Adjacent Channel During Sequence Conversion During sequence conversion, the time between last channel finished conversion and next channel start sampling can be set by TGAP bit in ADCON2 register.
  • Page 133 SH79F6441 8.6.5 The Configuration of ADC Conversion Time The ADC clock and sampling time can be set through ADT register. By setting the TADC[3:0] bits in the ADT can set the ADC clock. The TS[3:0] bits in the register ADT can be used to set the sampling time (t...
  • Page 134 SH79F6441 8.7 Low Power Detect (LPD) 8.7.1 Features  Low voltage detection and interrupt generation  LPD detect voltage is selectable  LPD debounce time TLPD is 30-60us Low Power Detect (LPD) function is used to monitor the supply voltage and generate an internal flag if the voltage decreasebelow the specified value.It is used to inform CPU whether the power is shut off or the battery is used out, so the...
  • Page 135 SH79F6441 Table 8.48 LPD Voltage Selection Register BBH, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LPDSEL LPDS3 LPDS2 LPDS1 LPDS0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description LPD Voltage Select Bit 0000: 2.85V 0001: 2.85V 0010: 2.85V 0011: 2.85V...
  • Page 136 SH79F6441 8.8 Low Voltage Reset (LVR) 8.8.1 Features  Enabled by the code option and V is 2.8V or 4.1V  LVR debounce timer T is about 30-60us  When the supply voltage is lower than the set voltage V...
  • Page 137 OVL Reset To enhance the anti-noise ability, SH79F6441 built in Program Counter (PC) over range detect circuit, if program counter value is larger than flash romsize, or detect operation code equal to A5H which is not exist in 8051 instruction set, a OVL reset will be generate to reset CPU, and set WDOF bit.
  • Page 138  CRC generator polynomial adopt the CRC-CCITT Standard: X +1,high bit first. To improve the system reliability, the SH79F6441 has one CRC verification module built-in, CRC check code can be used to generate real-time code, using the generation polynomial: X +1, which adopt the CRC-CCITT Standard.Users can...
  • Page 139 SH79F6441 By setting the CRC_FAC bit, the CRC check area can be selected as the Main Block or EEPROM-like area. The related registers are described as follows: Table 8.52 Flash Access Control Register A7H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3...
  • Page 140 (2) After the reset signal is generated (low level appears on the reset pin, WDT reset, LVR reset). The CPU recovers the clock, the SUSLO register and the IDL bit in the PCON register are cleared by hardware, and finally the SH79F6441 is reset, and the program starts execution at address bit 0000H.
  • Page 141 SH79F6441 8.11.4 Register Table 8.55 Power control register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PCON SMOD SSTAT Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description SMOD EUART Baud rate doubler SSTAT SCON[7:5] function select bit GF[1:0] General purpose flags for software use...
  • Page 142 Power-on reset, Pin reset, LVR reset, Watchdog Reset and Wake up from Power-down mode. After power-on, SH79F6441 will warm up the counting process after the power is turned on and wait for the overflow to perform the oscillator warm-up counting process. After the overflow, the program will run.
  • Page 143 SH79F6441 8.13 Code Option OP_WDT: 0101: Disable WDT function other: Enable WDT function (default) OP_WDTPD: 0: Disable WDT function in Power-Down mode (default) 1: Enable WDT function in Power-Down mode OP_RST: 0: Enable P1.7 pin reset(default) 1: Select P1.7 as IO...
  • Page 144 SH79F6441 OP_AHRV: 0: 32.768khz crystal resonator anti-humidity function control position AHUM reset value is 0 (default) 1: 32.768khz crystal resonator anti-humidity function control position AHUM reset value is 1 OP_P0DRV: 00: The driving current capacity of Port0 remains unchanged (default)
  • Page 145: Arithmetic Operations

    SH79F6441 9. Instruction Set ARITHMETIC OPERATIONS Opcode Description Code Byte Cycle ADD A, Rn Add register to accumulator 0x28-0x2F ADD A, direct Add direct byte to accumulator 0x25 ADD A, @Ri Add indirect RAM to accumulator 0x26-0x27 ADD A, #data...
  • Page 146: Logic Operations

    SH79F6441 LOGIC OPERATIONS Opcode Description Code Byte Cycle ANL A, Rn AND register to accumulator 0x58-0x5F ANL A, direct AND direct byte to accumulator 0x55 ANL A, @Ri AND indirect RAM to accumulator 0x56-0x57 ANL A, #data AND immediate data to accumulator...
  • Page 147: Data Transfers

    SH79F6441 DATA TRANSFERS Opcode Description Code Byte Cycle MOV A, Rn Move register to accumulator 0xE8-0xEF MOV A, direct Move direct byte to accumulator 0xE5 MOV A, @Ri Move indirect RAM to accumulator 0xE6-0xE7 MOV A, #data Move immediate data to accumulator...
  • Page 148: Program Branches

    SH79F6441 PROGRAM BRANCHES Opcode Description Code Byte Cycle ACALL addr11 Absolute subroutine call 0x11-0xF1 LCALL addr16 Long subroutine call 0x12 Return from subroutine 0x22 RETI Return from interrupt 0x32 AJMP addr11 Absolute jump 0x01-0xE1 LJMP addr16 Long jump 0x02 SJMP rel...
  • Page 149 SH79F6441 BOOLEAN MANIPULATION Opcode Description Code Byte Cycle CLR C Clear carry flag 0xC3 CLR bit Clear direct bit 0xC2 SETB C Set carry flag 0xD3 SETB bit Set direct bit 0xD2 CPL C Complement carry flag 0xB3 CPL bit...
  • Page 150 SH79F6441 10. Electrical Characteristics Absolute Maximum Ratings* *Comments DC Supply Voltage....-0.3V to +6.0V Stresses exceed those listed under “Absolute Maximum Ratings” may cause permanent damage to this device.
  • Page 151 SH79F6441 (continue) ——-------—— , T3, INT0/1/2/3/4, PxCEX0-1 (x = 0-2), ECI0-2, ——— MISO, MOSI, SDA, SCL, SCK, SS , 18 I/O ports Input High Voltage2 0.8 X V select, schmidt input (Note 3). = 2.7V-5.5V Select TTL input for 18 I/O ports (Note 3) (input high/low voltage window 0.4V)
  • Page 152 SH79F6441 (continue) I/O Port (P0, P1, P2, P4, P3, P5), (need OP_P35、P32-P30/OP_P23-P20/OP_P27-P24 to select sink current as a larger gear) = 0.6V, V = 5.0V I/O Port (P0, P1, P2, P4, P3, P5), (need OP_P35、P32-P30/OP_P23-P20/OP_P27-P24 OL1MAX to select sink current as a larger gear) = 5.0V, T...
  • Page 153 SH79F6441 A/D Converter Electrical Characteristics (The conversion rate of 1M SPS: 1LSB = V /4096 (V = 2.7 - 5.5V, GND = 0V, TA = +25°C, unless otherwise specified) Parameter Symbol Min. Max. Unit Condition Operating voltage range = 5.0V...
  • Page 154 SH79F6441 AC Electrical Characteristics (V = 2.7 - 5.5V, GND = 0V, T = +25°C, f = 24MHz, unless otherwise specified) Parameter Symbol Min. Max. Unit Condition = 32.768kHz Oscillator start time = 16MHz Crystal µs RESET pulse width RESET...
  • Page 155 SH79F6441 11. Ordering Information Part No. Package SH79F6441M/028MU SOP28 SH79F6441Q/032QR QFN32 (4 X 4) SH79F6441Q/032QY QFN32 (4 X 4) SH79F6441P/032PR LQFP32 SH79F6441P/044PR LQFP44...
  • Page 156 SH79F6441 12. Product Naming Rules SH 79 F 64 41 P / 044 P R R: Tray packing U: Tube packing Y: Tape & Reel packing P: LQFP Package Q: QFN Package M: SOP Package 044:Package pins is 44 032:Package pins is 32...
  • Page 157: Package Information

    SH79F6441 13. Package Information LQFP44L Outline Dimensions unit: inches/mm θ2 See Detail F DETAIL F Seating Plane Dimensions in inches Dimensions in mm Symbol 0.057 0.065 1.45 1.65 0.000 0.001 0.01 0.21 0.051 0.059 0.388 0.400 9.85 10.15 0.388 0.400 9.85...
  • Page 158 SH79F6441 LQFP32L Outline Dimensions unit: inches/mm θ2 See Detail F DETAIL F Dimensions in inches Dimensions in mm Symbol 0.057 0.065 1.45 1.65 0.000 0.008 0.01 0.21 0.051 0.059 1.30 1.50 0.268 0.281 6.80 7.15 0.268 0.281 6.80 7.15 0.346 0.362...
  • Page 159 SH79F6441 QFN 32L - B (4 X 4) (P0.40 T 0.75) Outline Dimensions unit: mm Top View Bottom View Side View Dimensions in mm Symbol 0.70 0.80 0.05 0.20REF 4.00BSC 4.00BSC 2.50 2.80 2.50 2.80 0.20 0.15 0.25 0.40BSC 0.27...
  • Page 160 SH79F6441 SOP28L Outline Dimensions unit: inches/mm θ2 Detail F See Detail F Seating Plane Dimensions in inches Dimensions in mm Symbol 0.085 0.104 2.15 2.65 0.004 0.012 0.10 0.30 0.081 0.098 2.05 2.50 0.013 0.02 0.33 0.51 0.006 0.014 0.15 0.36...
  • Page 161 SH79F6441 14. Product SPEC. Change Notice Version Record Data 1. Correct several clerical errors Jan. 2022 1. Correct several clerical errors 2. Increase the electrical characteristics of IO port output current and perfusion current Nov. 2021 3. Add power on reset electrical characteristics 4.
  • Page 162: Important Notice

    SH79F6441 IMPORTANT NOTICE This manual is the property of Sino Wealth Electronic Ltd. and its affiliates ("Company"). This manual, including all of the Company's products ("Products") described herein, is owned by the Company according to relevant laws or treaties. The Company reserves all rights under such laws and treaties, and does not grant you any license to use its patents, copyrights, trademarks and other intellectual property rights.
  • Page 163 SH79F6441 Directory FEATURES ...................................... 1 GENERAL DESCRIPTION ................................1 BLOCK DIAGRAM ..................................2 PIN CONFIGRATION ................................... 3 4.1 LQFP44 P ....................................3 ACKAGE 4.2 LQFP32 P ....................................4 ACKAGE 4.3 QFN32 P ....................................5 ACKAGE 4.4 SOP28 P ....................................6 ACKAGE PIN DESCRIPTION ..................................
  • Page 164 SH79F6441 7.10.1 Features ....................................68 7.10.2 Interrupt Enable Control ................................68 7.10.3 Interrupt Flag ................................... 71 7.10.4 Interrupt Vector ..................................73 7.10.5 Interrupt Priority ..................................73 7.10.6 Interrupt Handling ..................................74 7.10.7 Interrupt Response Timing ............................... 74 7.10.8 External Interrupt Input ................................75 7.10.9 Interrupt Summary ..................................
  • Page 165 SH79F6441 8.11.1 Features ....................................140 8.11.2 Idle Mode ....................................140 8.11.3 Power-Down Mode ................................. 140 8.11.4 Register ....................................141 8.12 W .................................... 142 IMER 8.12.1 Features ....................................142 8.13 C ....................................143 PTION INSTRUCTION SET ................................... 145 ELECTRICAL CHARACTERISTICS ............................. 150 ORDERING INFORMATION ..............................