1. Manuals
  2. Brands
  3. Sino Wealth Manuals
  4. Microcontrollers
  5. SH79F166A
  6. Manual

Sino Wealth SH79F166A Manual

Enhanced 8051 microcontroller with 10bit adc
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual

1. Features

8bits micro-controller with Pipe-line structured 8051
compatible instruction set
Flash ROM: 16K Bytes
RAM: internal 256 Bytes, external 256 Bytes, LCD RAM
19Bytes
EEPROM-like: 1K Bytes
Operation Voltage:
f
= 32.768kHz - 12MHz, V
OSC
Oscillator (code option)
- Crystal oscillator: 32.768kHz
- Crystal oscillator: 2MHz - 12MHz
- Ceramic oscillator: 2MHz - 12MHz
- Internal RC: 12MHz (±2%)/128K
41 CMOS bi-directional I/O pins
Built-in pull-up resistor for input pin
Four 16-bit timer/counters T2, T3,T4 and T5
One 12-bit PWM
Powerful interrupt sources:
- Timer2, 3, 4, 5
- INT0, 1, 2, 3
- INT40, INT41, INT42, INT43
- ADC，EUART，SCM
- PWM

2. General Description

The SH79F166A is a high performance 8051 compatible micro-controller, regard to its build-in Pipe-line instruction fetch
structure, that helps the SH79F166A can perform more fast operation speed and higher calculation performance, if compare
SH79F166A with standard 8051 at same clock speed.
The SH79F166A retains most features of the standard 8051. These features include internal 256 bytes RAM, UART and
Int0-3.In addition, the SH79F166A provides external 256 bytes RAM, It also contains 16K bytes Flash memory block both for
program and data. Also the ADC and PWM timer functions are incorporated in SH79F166A.
For high reliability and low cost issues, the SH79F166A builds in Watchdog Timer, Low Voltage Reset function. And
SH79F166A also supports two power saving modes to reduce power consumption.
Enhanced 8051 Microcontroller with 10bit ADC
= 2V - 5.5V
DD
EUART
8channels 10-bits Analog Digital Converter (ADC),
with comparator function built-in
Buzzer
LED driver:
- 8 X 8 dots (1/8 duty)
- 4 X 8 dots (1/4 duty)
LCD driver:
- 8 X 19 dots (1/8 duty 1/4 bias)
- 4 X 19 dots (1/4 duty 1/3 bias)
Low Voltage Reset (LVR) function (enabled by
code option)
- LVR voltage level 1: 4.3V
- LVR voltage level 2: 2.1V
CPU Machine cycle:
1 oscillator clock
Watch Dog Timer (WDT)
Warm-up Timer
Support Low power operation modes:
- Idle Mode
- Power-Down Mode
Flash Type
Package: QFP44/LQFP44
1
SH79F166A
V2.2

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the SH79F166A and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for Sino Wealth SH79F166A

Summary of Contents for Sino Wealth SH79F166A

  • Page 1: Features

    The SH79F166A retains most features of the standard 8051. These features include internal 256 bytes RAM, UART and Int0-3.In addition, the SH79F166A provides external 256 bytes RAM, It also contains 16K bytes Flash memory block both for program and data. Also the ADC and PWM timer functions are incorporated in SH79F166A.

  • Page 2: Block Diagram

    SH79F166A 3. Block Diagram Reset circuit Pipelined 8051 architecture Power Watch Dog 16K Bytes Flash ROM Port 5 Configuration I/Os P5.0 - P5.3 Internal 256 Bytes External 256 Bytes (Exclude System Port 4 Register) Configuration I/Os P4.0 - P4.4 Port 3...

  • Page 3: Pin Configuration

    SH79F166A 4. Pin Configuration QFP44: 30 29 28 27 25 24 23 LED_S8/SEG8/P1.7 P3.4/COM5/LED_C5/AN4 RXD/SEG9/P2.0 P3.5/COM6/LED_C6/AN5 TXD/SEG10/P2.1 P3.6/COM7/LED_C7/AN6 SEG11/P2.2 P3.7/COM8/LED_C8/AN7 SEG12/P2.3 P4.0/INT40/AN0 SH79F166AF SEG13/P2.4 P4.1/INT41/AN1 FLT/SEG14/P2.5 P4.2/INT42/AN2 P4.3/INT43/AN3 SEG15/P2.6 SEG16/P2.7 P4.4/AVREF SEG17/P0.0 SEG18/P0.1 QFP44 Pin Configuration Diagram...
  • Page 4 SH79F166A LQFP44: 30 29 28 27 25 24 23 LED_S8/SEG8/P1.7 P3.4/COM5/LED_C5/AN4 RXD/SEG9/P2.0 P3.5/COM6/LED_C6/AN5 TXD/SEG10/P2.1 P3.6/COM7/LED_C7/AN6 SEG11/P2.2 P3.7/COM8/LED_C8/AN7 SEG12/P2.3 P4.0/INT40/AN0 SH79F166AP SEG13/P2.4 P4.1/INT41/AN1 FLT/SEG14/P2.5 P4.2/INT42/AN2 SEG15/P2.6 P4.3/INT43/AN3 SEG16/P2.7 P4.4/AVREF SEG17/P0.0 SEG18/P0.1 LQFP44 Pin Configuration Diagram Note: The out most pin function has the highest priority, and the inner most pin function has the lowest priority (Refer to Pin Configuration Diagram.
  • Page 5 SH79F166A Table 4.1 Pin Function Pin No. Pin Name Default function Pin No. Pin Name Default function PWM01/SEG19/P0.2 P0.2 LED_C4/COM4/P3.3 P3.3 PWM0/T4/P0.3 P0.3 LED_C3/COM3/P3.2 P3.2 T2EX/INT0/P0.4 P0.4 LED_C2/COM2/P3.1 P3.1 T2/INT1/P0.5 P0.5 LED_C1/COM1/P3.0 P3.0 XTALX2/INT2/P0.6 P0.6 LED_S1/SEG1/P1.0 P1.0 XTALX1/INT3/P0.7 P0.7 LED_S2/SEG2/P1.1 P1.1...

  • Page 6: Pin Description

    SH79F166A 5. Pin Description Pin No. Type Description I/O PORT P0.0 - P0.7 8 bit General purpose CMOS I/O P1.0 - P1.7 8 bit General purpose CMOS I/O P2.0 - P2.7 8 bit General purpose CMOS I/O P3.0 - P3.7 8 bit General purpose CMOS I/O P4.0 - P4.4...
  • Page 7 SH79F166A (continue) Pin No. Type Description Buzzer Buzzer output pin Programmer TDO (P1.0) Debug interface: Test data out TMS (P1.1) Debug interface: Test mode select TDI (P1.2) Debug interface: Test data in TCK (P1.3) Debug interface: Test clock in ：...

  • Page 8: Sfr Mapping

    SH79F166A 6. SFR Mapping The SH79F166A provides 256 bytes of internal RAM to contain general-purpose data memory and Special Function Register (SFR). The SFR of the SH79F166A fall into the following categories: CPU Core Registers: ACC, B, PSW, SP, DPL, DPH...
  • Page 9 SH79F166A Table 6.1 CPU Core SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 /PIN Reset Value Accumulator 00000000 ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 B Register 00000000 AUXC C Register 00000000 Program Status Word...
  • Page 10 SH79F166A Table 6.3 Flash control SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 /PIN Reset Value IB_OFF Low byte offset of flash memory IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF 00000000 Bank0 for programming SET.7 SET.6...
  • Page 11 SH79F166A Table 6.6 Interrupt SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 /PIN Reset Value IEN0 Interrupt Enable Control 0 0000-000 EADC Bank0 IEN1 Interrupt Enable Control 1 0000000- ESCM/ELPD EPWM Bank0 IENC Interrupt 4channel enable control...
  • Page 12 SH79F166A Table 6.7 Port SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 /PIN Reset Value 8-bit Port 0 00000000 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 Bank0 8-bit Port 1 00000000 P1.7 P1.6 P1.5 P1.4 P1.3...
  • Page 13 SH79F166A Table 6.8 Timer SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 /PIN Reset Value TCON Timer/Counter Control ----0000 Bank0 ---- ---- ---- ---- ---- T2CON Timer/Counter 2 Control 00000000 EXF2 RCLK TCLK EXEN2 CP/R Bank0...
  • Page 14 SH79F166A Table 6.9 EUART SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 /PIN Reset Value SCON Serial Control 00000000 SM0/FE SM1/RXOV SM2/TXCOL Bank0 SBUF Serial Data Buffer 00000000 SBUF.7 SBUF.6 SBUF.5 SBUF.4 SBUF.3 SBUF.2 SBUF.1 SBUF.0...
  • Page 15 SH79F166A Table 6.12 LCD SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 /PIN Reset Value DISPCON LCD Control 00000000 DISPSEL LCDON ELCC DUTY VOL3 VOL2 VOL1 VOL0 Bank0 DISPCON1 LCD Control 1 ---00000 RLCD FCCTL1 FCCTL0...
  • Page 16 SH79F166A Table 6.14 PWM SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 /PIN Reset Value PWMEN PWM timer enable -0--0--0 EFLT EPWM01 EPWM0 Bank0 PWMEN1 PWM output enable -------0 PWM0 Bank0 PWMLO PWM register Lock 00000000 PWMLO.7...
  • Page 17 SH79F166A SFR Map Bank0 Non Bit addressable addressable IB_OFFSET IB_DATA AUXC IB_CON1 IB_CON2 IB_CON3 IB_CON4 IB_CON5 XPAGE EXF0 P0PCR P1PCR P2PCR P3PCR P4PCR P0OS P0CR P1CR P2CR P3CR P4CR PWMLO EXF1 PWM0DT PWM0C PWM0PL PWM0PH PWM0DL PWM0DH T2CON T2MOD RCAP2L...

  • Page 18: Normal Function

    SH79F166A 7. Normal Function 7.1 CPU 7.1.1 CPU Core SFR Feature  CPU core registers: ACC, B, PSW, SP, DPL, DPH Accumulator ACC is the Accumulator register. The mnemonics for accumulator-specific instructions, however, refer to the Accumulator simply as A.

  • Page 19: Enhanced Cpu Core Sfrs

     Dual Data Pointer  Enhanced CPU core registers: AUXC, DPL1, DPH1, INSCON The SH79F166A has modified 'MUL' and 'DIV' instructions. These instructions support 16 bit operand. A new register - the register is applied to hold the upper part of the operand/result.

  • Page 20: Ram

    256 bytes RAM; MOVX A, @DPTR or MOVX @DPTR, A also to access external 256 bytes RAM. In SH79F166A the user can also use XPAGE register to access external RAM only with MOVX A, @Ri or MOVX @Ri, A instructions.

  • Page 21: Flash Program Memory

    Program Memory Block 0000H 0000H Information Block Program Memory Block The SH79F166A embeds 16K flash program memory for program code. The flash program memory provides electrical erasure and programming and supports In-Circuit Programming (ICP) mode and Self-Sector Programming (SSP) mode.

  • Page 22: Flash Operation In Icp Mode

    The ICP mode supports the following operations: (1) Code-Protect Control mode Programming SH79F166A implements code-protect function to offer high safeguard for customer code. Two modes are available for each sector. Code-protect control mode 0: Used to enable/disable the write/read operation (except mass erase) from any programmer.
  • Page 23 SH79F166A In ICP mode，all the flash operations are completed by the programmer through 6-wire interface. Since the program timing is very sensitive, five jumpers are needed (V , TDO, TDI, TCK, TMS) to separate the program pins from the application circuit as the following diagram.

  • Page 24: Ssp Function

    But once sector has been programmed, it cannot be reprogrammed before sector erase. The SH79F166A builds in a complex control flow to prevent the code from carelessly modification. If the dedicated conditions are not met (IB_CON2-5), the SSP will be terminated.
  • Page 25 SH79F166A Table 7.7 SSP Type select Register F2H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IB_CON1 IB_CON1.7 IB_CON1.6 IB_CON1.5 IB_CON1.4 IB_CON1.3 IB_CON1.2 IB_CON1.1 IB_CON1.0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description SSP Type select IB_CON1[7:0] 0xE6: Sector Erase 0x6E: Sector Programming Table 7.8 SSP Flow Control Register1...

  • Page 26: Flash Control Flow

    SH79F166A 7.4.2 Flash Control Flow Set IB_OFFSET Set XPAGE Set IB_DATA Set IB_CON1 IB_CON2[3:0]≠5H Set IB_CON2[3:0]=5H IB_CON2≠5H IB_CON3≠AH IB_CON2≠5H Set IB_CON3=AH ELSE IB_CON3≠AH Set IB_CON4=9H IB_CON4≠9H Reset IB_CON1-5 Set IB_CON5=6H Sector Erase IB_CON1=E6H &IB_CON2[3:0]=5H &IB_CON3=AH &IB_CON4=9H &IB_CON5=6H IB_CON1=6EH &IB_CON2[3:0]=5H &IB_CON3=AH &IB_CON4=9H...

  • Page 27: Ssp Programming Notice

    SH79F166A 7.4.3 SSP Programming Notice To successfully complete SSP programming, the user’s software must following the steps below: (1) For Code/Data Programming: 1. Disable interrupt; 2. Fill in the XPAGE, IB_OFFSET for the corresponding address; 3. Fill in IB_DATA if programming is wanted;...

  • Page 28: System Clock And Oscillator

    (2MHz-12MHz) and internal RC (12MHz,), which is selected by code option OP_OSC (Refer to code option section for details). SH79F166A have 4 Oscillator pin (XTAL1, XTAL2, XTALX1, XTALX2) and can generates one or two clock sources from four oscillator types. It is selected by code option OP_OSC (Refer to code option section for details). The oscillator generates the...

  • Page 29: Register

    SH79F166A 7.5.4 Register Table 7.13 System Clock Control Register B2H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CLKCON 32k_SPDUP CLKS1 CLKS0 SCMIF HFON Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description 32.768kHz oscillator speed up mode control bit 0: 32.768kHz oscillator normal mode, cleared by software.

  • Page 30: Oscillator Type

    SH79F166A 7.5.5 Oscillator Type (1) OP_OSC = 0000, 0011: internal RC, XTAL and XTALX are shared with IO XTALX1 XTALX2 XTAL1 XTAL2 (2) OP_OSC = 1010: 32.768kHz Crystal Oscillator at XTAL, Internal RC can be enabled, XTALX shared with I/O...

  • Page 31: Capacitor Selection For Oscillator

    SH79F166A 7.5.6 Capacitor Selection for Oscillator Ceramic Resonators Frequency 3.58MHz 4MHz Crystal Oscillator Frequency 32.768kHz 10 - 12pF 10 - 12pF 4MHz 8 - 15pF 8 - 15pF 12MHz 8 - 15pF 8 - 15pF Notes: (1) Capacitor values are used for design guidance only! (2) These capacitors were tested with the crystals listed above for basic start-up and operation.

  • Page 32: System Clock Monitor (Scm)

    7.6 System Clock Monitor (SCM) In order to enhance the system reliability, SH79F166A contains a system clock monitor (SCM) module. If the system clock fails (for example the oscillator stops oscillating), the built-in SCM will switch the OSCCLK to the internal 32k WDTCLK and set system clock monitor bit (SCMIF) to 1.

  • Page 33: I/O Port

    PORT is used as input (x = 0-5, y = 0-7). For SH79F166A, some I/O pins can share with alternative functions. There exists a priority rule in CPU to avoid these functions be conflict when all the functions are enabled. (Refer to Port Share Section for details).
  • Page 34 SH79F166A Table 7.17 Port Data Register 80H - C0H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P0 (80H, Bank0) P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 P1 (90H, Bank0) P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 P2 (A0H, Bank0) P2.7...

  • Page 35: Port Diagram

    SH79F166A 7.7.3 Port Diagram SFEN PxPCRy Output Mode Input Mode 0 = ON (Pull-up) PxCRy 1 = OFF I/O Pad Write Data Data Bus Register Read Port Data Register Read Read Data Register/Pad Selection 0: From Pad 1: From data register...
  • Page 36 SH79F166A Table 7.19 PORT0 Share Table Pin No. Priority Function Enable bit Clear DISPSEL bit in DISPCON register and set P0S0 bit in P0SS register SEG17 P0.0 Above condition is not met SEG18 Clear DISPSEL bit in DISPCON register and set P0S1 bit in P0SS register P0.1...
  • Page 37 SH79F166A PORT2: - RXD: EUART data input (P2.0) - TXD: EUART data output (P2.1) - FLT: Fault input pin (P2.5) - LCD Segment 9-16 (P2.0-P2.7) Table 7.21 PORT2 Share Table Pin No. Priority Function Enable bit Set REN bit in SCON Register (Auto Pull up)
  • Page 38 SH79F166A PORT4: - INT40-INT43 (P4.0-P4.3): External interrupt input - AN0-AN3 (P4.0-P4.3): ADC input channel - AVREF (P4.4): ADC reference voltage Table 7.23 PORT4 Share Table Pin No. Priority Function Enable bit AVREF Set REFC bit in ADCON register P4.4 Above condition is not met...

  • Page 39: Timer

    7.8 Timer 7.8.1 Features  The SH79F166A has four timers (Timer2, 3, 4, 5)  Timer2 is compatible with the standard 8052 and has up or down counting and programmable clock output function  Timer3 is a 16-bit auto-reload timer and can operate even in Power-Down mode ...
  • Page 40 SH79F166A Mode1: 16 bit auto-reload Timer Timer2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit in T2MOD. After reset, the DCEN bit is set to 0 so that Timer2 will default to count up. When DCEN is set, Timer2 can count up or down, depending on the value of the T2EX pin.
  • Page 41 SH79F166A Mode2: Baud-Rate Generator Timer2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON. The baud rates for transmit and receive can be different if Timer2 is used for the receiver or transmitter and Timer4 is used for the other.
  • Page 42 SH79F166A Mode3: Programmable Clock Output ——— A 50% duty cycle clock can be programmed to come out on P0.5. To configure the Timer2 as a clock generator, bit C/T2 must be cleared and bit T2OE must be set. Bit TR2 starts and stops the timer.
  • Page 43 SH79F166A Registers Table 7.26 Timer2 Control Register C8H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ——— ———— T2CON EXF2 RCLK TCLK EXEN2 CP/RL2 C/T2 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Timer2 overflow flag bit 0: No overflow 1: Overflow (Set by hardware if RCLK = 0 &...
  • Page 44 SH79F166A Table 7.27 Timer2 Mode Control Register C9H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 T2MOD T2OE DCEN Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Timer2 Output Enable bit T2OE 0: Set P0.5/T2 as clock input or I/O port 1: Set P0.5/T2 as clock output (Baud-Rate generator mode)

  • Page 45: Timer3

    SH79F166A 7.8.3 Timer3 Timer3 is a 16-bit auto-reload timer. It is accessed as two cascaded Data Registers: TH3 and TL3. It is controlled by the T3CON register. The Timer3 interrupt can be enabled by setting ET3 bit in IEN1 register (Refer to Interrupt Section for details).
  • Page 46 SH79F166A Registers Table 7.29 Timer3 Control Register 88H, Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 T3CON T3PS.1 T3PS.0 T3CLKS.1 T3CLKS.0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Timer3 overflow flag bit 0: No overflow (cleared by hardware)

  • Page 47: Timer4

    SH79F166A 7.8.4 Timer4 Timer4 is a 16-bit auto-reload timer. It is accessed as two cascaded data registers: TH4 and TL4. It is controlled by the T4CON register. The Timer 4 interrupt can be enabled by setting ET4 bit in IEN1 register (Refer to interrupt Section for details).
  • Page 48 SH79F166A Mode2: 16 bit Auto-Reload Timer with T4 Edge Trig Timer4 operates as 16-bit timer in Mode2. The TH4 register holds the high eight bits of the 16-bit counter/timer, TL4 holds the low eight bits. As the 16-bit timer register increments and overflows from 0xFFFF to 0x0000, the timer overflow flag TF4 (T4CON.7) is set and the 16-bit value in timer load register are reloaded into timer counter register, and an interrupt will occur if...
  • Page 49 SH79F166A Registers Table 7.32 Timer4 Control Register C8H, Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 T4CON T4PS1 T4PS0 T4M1 T4M0 T4CLKS Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Timer4 overflow flag bit 0: No overflow (cleared by hardware)

  • Page 50: Timer5

    SH79F166A 7.8.5 Timer5 Timer5 is a 16-bit auto-reload timer. It is accessed as two cascaded data registers: TH5 and TL5. It is controlled by the T5CON register. The interrupt can be enabled by setting ET5 bit in IEN0 register (Refer to interrupt Section for details).
  • Page 51 SH79F166A Registers Table 7.34 Timer5 Control Register C0H, Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 T5CON T5PS1 T5PS0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Timer5 overflow flag bit 0: No overflow (cleared by hardware) 1: Overflow (Set by hardware)

  • Page 52: Interrupt

     4 interrupt priority levels The SH79F166A provides total 14 interrupt sources: 5 external interrupts (INT0/1/2/3/4; INT4 including INT40-43, which share the same vector address), 4 timer interrupts (Timer2, 3, 4, 5), one EUART interrupt, ADC Interrupt, PWM interrupts, SCM interrupt and LPD interrupt.
  • Page 53 SH79F166A Table 7.38 Secondary Interrupt Enable Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IEN1 ESCM/ELPD EPWM Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description SCM/LPD interrupt enable bit ESCM/ELPD 0: Disable SCM/LPD interrupt 1: Enable SCM/LPD interrupt Timer4 overflowinterrupt enable bit...
  • Page 54 SH79F166A Table 7.39 Interrupt channel Enable Register BAH, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IENC EXS43 EXS42 EXS41 EXS40 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description External interrupt4 channel select bit (x = 3-0) EXS4x 0: Disable external interrupt 4x...

  • Page 55: Interrupt Flag

    SH79F166A 7.9.3 Interrupt Flag Each Interrupt source has its own interrupt flag, when interrupt occurs, corresponding flag will be set by hardware, the interrupt flag bits are listed in Table bellow. For external interrupt (INT0/1/2/3), when an external interrupt0/1/2/3 is generated, if the interrupt was edge trigged, the flag (IE0-3 in TCON) that generated this interrupt is cleared by hardware when the service routine is vectored.
  • Page 56 SH79F166A Table 7.42 External Interrupt Flag Register E8H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EXF0 IT4.1 IT4.0 IT3.1 IT3.0 IT2.1 IT2.0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description External interrupt4 trigger mode selection bit 00: Low Level trigger...

  • Page 57: Interrupt Vector

    SH79F166A 7.9.4 Interrupt Vector When an interrupt occurs, the program counter is pushed onto the stack and the corresponding interrupt vector address is loaded into the program counter. The interrupt vector addresses are listed in Interrupt Summary table. 7.9.5 Interrupt Priority Each interrupt source can be individually programmed to one of four priority levels by setting or clearing corresponding bits in the interrupt priority control registers IPL0, IPH0, IPL1, and IPH1.

  • Page 58: Interrupt Handling

    SH79F166A 7.9.6 Interrupt Handling The interrupt flags are sampled and polled at the fetch cycle of each machine cycle. All interrupts are sampled at the rising edge of the clock. If one of the flags was set, the CPU will find it and the interrupt system will generate a LCALL to the appropriate service routine, provided this hardware-generated LCALL is not blocked by any of the following conditions: An interrupt of equal or higher priority is already in progress.

  • Page 59: External Interrupt Inputs

    If an external interrupt is enabled when the SH79F166A is put into Power down or Idle mode, the interrupt occurrence will cause the processor to wake up and resume operation.

  • Page 60: Enhanced Function

    75/300K. Therefore, SH79F166A provides both the low power consumption and display effect of the display mode:fast charge mode. Set MOD[1:0] = 10 to select this mode. When refresh the display data 20k bias resistors are selected to provide larger current.When keep the display data 75/300K bias resistors are selected to save drive current.
  • Page 61 SH79F166A LCD Waveform (1/4duty, 1/3bias)
  • Page 62 SH79F166A COM8 COM1 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM2 COM3 COM4 SEGn SEGn COM1- SEGn - V1 - V2 - V3 LCD waveform (1/8duty, 1/4bias)

  • Page 63: Registers

    = 0.906 V 1101: V = 0.938 V 1111/1110: V = 1.000 V Note: SH79F166A has LCD and LED driver, but can not work in the same time. When DISPSEL = 1, LCD is disable, DISPSEL = 0, LED is disable.
  • Page 64 SH79F166A Table 8.2 LCD Control Register1 ADH, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DISPCON1 RLCD FCCTL1 FCCTL2 MOD1 MOD0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description LCD Drive mode control bit 00: traditional mode, bias resistor sum is 225K/900K...
  • Page 65 SH79F166A Table 8.4 P0 Mode Select Register B6H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P0SS P0S2 P0S1 P0S0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description P0 mode select P0S[2:0] 0: P0.0-P0.2 is I/O 1: P0.0-P0.2 is Segment (Segment17-19) Table 8.5 P1 Mode Select Register...

  • Page 66: Configuration Of Lcd Ram

    SH79F166A 8.1.2 Configuration of LCD RAM LCD 1/4 duty, 1/3 bias (COM1 - 4, SEG1 - 19) Address COM4 COM3 COM2 COM1 1E0H SEG1 SEG1 SEG1 SEG1 1E1H SEG2 SEG2 SEG2 SEG2 1E2H SEG3 SEG3 SEG3 SEG3 1E3H SEG4 SEG4...

  • Page 67: Led Driver

    0: 1/4 duty 1: 1/8 duty Note: SH79F166A has LCD and LED driver,but can not work in the same time.When DISPSEL = 1, LCD is disable, DISPSEL = 0, LED is disable. Table 8.9 LED Clock Control Register ACH, Bank0...

  • Page 68: Configuration Of Led Ram

    SH79F166A Table 8.10 P1 Mode Select Register 9CH, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P1SS P1S7 P1S6 P1S5 P1S4 P1S3 P1S2 P1S1 P1S0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description P1 mode select (x = 0-7) P1S[7:0] 0: P1.0-P1.7 are I/O...
  • Page 69 SH79F166A LED Waveform (1) OP_LEDCOM = 0 1/8 DUTY 1/4 DUTY COM1 COM1 COM2 COM2 SEG1 SEG1 SEG2 SEG2 SEG1& SEG1& COM1 COM1 UNSELECT SELECT SELECT UNSELECT (2) OP_LEDCOM [1] = 1 1/8 DUTY 1/4 DUTY COM1 COM1 COM2 COM2...

  • Page 70: Pwm (Pulse Width Modulation)

     Lock register provided to avoid PWM control register to be unexpected change The SH79F166A has one 12-bit PWM module. Which can provide the pulse width modulation waveform with the period and the duty being controlled individually by corresponding register.

  • Page 71: Pwm Timer Lock Register

    PWM dead time control register. Only when the data in this register is #55h, it is possible to change these register. Otherwise they cannot be changed. This register is to enhance the anti-noise ability of SH79F166A. Table 8.14 PWM Timer Lock Register...

  • Page 72: 12-Bit Pwm Timer

    8.3.4 12-bit PWM Timer The SH79F166A has one 12-bit PWM module. The PWM module can provide the pulse width modulation waveform with the period and the duty being controlled, individually. The PWMC is used to control the PWM module operation with proper clocks.
  • Page 73 SH79F166A Table 8.16 PWM Period Control Register (PWM0PL) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWM0PL PP0.7 PP0.6 PP0.5 PP0.4 PP0.3 PP0.2 PP0.1 PP0.0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description PP0[7:0] 12-bit PWM period low 8 nibble registers Table 8.17 PWM Period Control Register (PWM0PH)

  • Page 74: Pwm01

    SH79F166A Programming Note: (1) Set PWMLO register to 55H and select the PWM module system clock. (2) Set the PWM period/duty cycle by writing proper value to the PWM period control register (PWMP) or PWM duty control register (PWMD). First set the low Byte, then the high Byte.

  • Page 75: Dead Time

    SH79F166A 8.3.6 Dead Time The SH79F166 provides dead time control function on-chip. When PWM0S = 0, the dead time is generated as below. PWM int PWM int period PWM0S=0 duty cycle PWM0 PWM01 dead time dead time dead time Reload...

  • Page 76: Euart

    This mode provides synchronous communication with external devices. In this mode serial data is transmitted and received on the RxD line. TxD is used to output the shift clock. The TxD clock is provided by the SH79F166A whether the device is transmitting or receiving.
  • Page 77 SH79F166A Any instruction that uses SBUF as a destination register (“write to SBUF” signal) will start the transmission. The next system clock tells the Tx control block to commence a transmission. The data shift occurs at the falling edge of the SHIFT CLOCK, and the contents of the transmit shift register is shifted one position to the right.
  • Page 78 SH79F166A Transmission begins with a “write to SBUF” signal, and it actually commences at the next system clock following the next rollover in the divide-by-16 counter (divide baud-rate by 16), thus, the bit times are synchronized to the divide-by-16 counter, not to the “write to SUBF”...
  • Page 79 SH79F166A Mode2: 9-Bit EUART, Fixed Baud Rate, Asynchronous Full-Duplex This mode provides the 11 bits full duplex asynchronous communication. The 11 bit consists of one start bit (logical 0), 8 data bits (LSB first), a programmable 9 data bit, and a stop bit (logical 1). Mode 2 supports multiprocessor communications and hardware address recognition (Refer to Multiprocessor Communication Section for details).
  • Page 80 SH79F166A Reception is enabled only if REN is high. The serial port actually starts the receiving of serial data, with the detection of a falling edge on the RxD pin. For this purpose RxD is sampled at the rate of 16 times baud rate. When a falling edge is detected, the divide-by-16 counter is immediately reset.

  • Page 81: Baud Rate Generate

    SH79F166A 8.4.3 Baud Rate Generate In Mode0, the baud rate is programmable to either 1/12 or 1/4 of the system frequency. This baud rate is determined by SM2 bit. When set to 0, the serial port runs at 1/12 of the system clock. When set to 1, the serial port runs at 1/4 of the system clock.

  • Page 82: Error Detection

    SH79F166A Slave 1 Slave 2 SADDR 10100100 10100111 SADEN (0 mask) 11111010 11111001 Given Address 10100x0x 10100xx1 Broadcast Address (OR) 1111111x 11111111 The Given address for slave 1 and 2 differ in the LSB. For slave 1, it is a don’t care, while for slave 2 it is 1. Thus to communicate only with slave 1, the master must send an address with LSB = 0 (10100000).

  • Page 83: Register

    SH79F166A 8.4.6 Register Table 8.21 EUART Control & Status Register 98H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCON /RXOV /TXCOL Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description EUART Serial mode control bit, when SSTAT = 0...
  • Page 84 SH79F166A Table 8.22 EUART Data Buffer Register 99H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SBUF SBUF.7 SBUF.6 SBUF.5 SBUF.4 SBUF.3 SBUF.2 SBUF.1 SBUF.0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description This SFR accesses two registers; a transmit shift register and a receive latch register...
  • Page 85 SH79F166A Table 8.25 Rxd Pin Schmidt Voltage Control Register 9FH, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RxCON RxCON1 RxCON0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Rxd pin Schmidt voltage control 00: input low voltage is 0.2 V RxCON[1:0] 01: input low voltage is 0.4 V...

  • Page 86: Analog Digital Converter (Adc)

     Selectable external or built-in V  8 Multiplexed Input Channels The SH79F166A include a single ended, 10-bit SAR Analog to Digital Converter (ADC) with build in reference voltage connected to the V , users also can select the V pin input reference voltage.

  • Page 87: Adc Register

    SH79F166A 8.5.3 ADC Register Table 8.26 ADC Control Register 93H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 —---—-----— ADCON ADON ADCIF REFC SCH2 SCH1 SCH0 GO/DONE Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description ADC Enable bit ADON...
  • Page 88 SH79F166A Table 8.27 ADC定时控制寄存器 94H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TADC2 TADC1 TADC0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description ADC Clock Period Select bits 000: ADC Clock Period t = 2 t 001: ADC Clock Period t...
  • Page 89 SH79F166A Table 8.28 ADC Channel Configure Register 95H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADCH Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Channel Configuration bits 0: P4.0-P4.3，P3.4-P3.7 are I/O port CH[7:0] 1: P4.0-P4.3，P3.4-P3.7 are ADC input port Table 8.29 AD Converter Data Register (Compare Value Register)

  • Page 90: Buzzer

    SH79F166A 8.6 Buzzer 8.6.1 Feature  Output a signal (square wave) used for tones such as a confirmation tone  Selectable whether to output one of 8 output frequencies or to disable the output 8.6.2 Register Table 8.30 Buzzer Output Control Register...

  • Page 91: Low Power Detect (Lpd)

    SH79F166A 8.7 Low Power Detect (LPD) 8.7.1 Feature  An internal flag indicates low power is detected  LPD detect voltage is selectable  LPD de-bounce timer T is about 30-60µs The low power detect (LPD) is used to monitor the supply voltage and generate an internal flag if the voltage decrease below the specified value.

  • Page 92: Low Voltage Reset (Lvr)

    SH79F166A 8.8 Low Voltage Reset (LVR) 8.8.1 Feature  Enabled by the code option and VLVR is 4.3V or 2.1V  LVR de-bounce timer T is about 30-60µs  An internal reset flag indicates low voltage reset generates The LVR function is used to monitor the supply voltage and generate an internal reset in the device when the supply voltage below the specified value V .

  • Page 93: Watchdog Timer (Wdt) And Reset State

    OVL Reset To enhance the anti-noise ability, SH79F166A built in Program Counter (PC) over range detect circuit, if program counter value is larger than flash romsize, or detect operation code equal to A5H which is not exist in 8051 instruction set, a OVL reset will be generate to reset CPU, and set WDOF bit.

  • Page 94: Register

    SH79F166A 8.9.2 Register Table 8.32 Reset Control Register B1H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RSTSTAT WDOF PORF LVRF CLRF WDT.2 WDT.1 WDT.0 Reset Value (POR) Reset Value (WDT) Reset Value (LVR) Reset Value (PIN) Bit Number...

  • Page 95: Power Management

    The setting of PD bit will be the last instruction that CPU executed. Note: If IDL bit and PD bit are set simultaneously, the SH79F166A enters Power-Down mode. The CPU will not go in Idle mode when exiting from Power-Down mode, and the hardware will clear both IDL & PD bit after exit form Power-Down mode.

  • Page 96: Register

    SH79F166A 8.10.4 Register Table 8.33 Power Control Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PCON SMOD SSTAT Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description SMOD Baud rate double bit SSTAT SCON[7:5] function selection bit GF[1:0] General purpose flags for software use...

  • Page 97: Warm-Up Timer

     Built-in oscillator warm-up counter to eliminate unstable state when oscillation startup SH79F166A has a built-in power warm-up counter; it is designed to eliminate unstable state after power on or to do some internal initial operation such as read customer option etc.

  • Page 98: Code Option

    SH79F166A 8.12 Code Option OP_SCM: 0: SCM is invalid in warm up period 1: SCM is valid in warm up period OP_LEDCOM: 0: LED common signal is normal (default) 1: LED common signal is inverted OP_WDTPD: 0: Disable WDT function in Power-Down mode...

  • Page 99: Instruction Set

    SH79F166A 9. Instruction Set ARITHMETIC OPERATIONS Opcode Description Code Byte Cycle ADD A, Rn Add register to accumulator 0x28-0x2F ADD A, direct Add direct byte to accumulator 0x25 ADD A, @Ri Add indirect RAM to accumulator 0x26-0x27 ADD A, #data...
  • Page 100 SH79F166A LOGIC OPERATIONS Opcode Description Code Byte Cycle ANL A, Rn AND register to accumulator 0x58-0x5F ANL A, direct AND direct byte to accumulator 0x55 ANL A, @Ri AND indirect RAM to accumulator 0x56-0x57 ANL A, #data AND immediate data to accumulator...
  • Page 101 SH79F166A DATA TRANSFERS Opcode Description Code Byte Cycle MOV A, Rn Move register to accumulator 0xE8-0xEF MOV A, direct Move direct byte to accumulator 0xE5 MOV A, @Ri Move indirect RAM to accumulator 0xE6-0xE7 MOV A, #data Move immediate data to accumulator...
  • Page 102 SH79F166A PROGRAM BRANCHES Opcode Description Code Byte Cycle ACALL addr11 Absolute subroutine call 0x11-0xF1 LCALL addr16 Long subroutine call 0x12 Return from subroutine 0x22 RETI Return from interrupt 0x32 AJMP addr11 Absolute jump 0x01-0xE1 LJMP addr16 Long jump 0x02 SJMP rel...
  • Page 103 SH79F166A BOOLEAN MANIPULATION Opcode Description Code Byte Cycle CLR C Clear carry flag 0xC3 CLR bit Clear direct bit 0xC2 SETB C Set carry flag 0xD3 SETB bit Set direct bit 0xD2 CPL C Complement carry flag 0xB3 CPL bit...

  • Page 104: Electrical Characteristics

    SH79F166A 10. Electrical Characteristics Absolute Maximum Ratings* *Comments DC Supply Voltage....-0.3V to +6.0V Stresses exceed those listed under “Absolute Maximum Ratings” may cause permanent damage to this device.

  • Page 105: A/D Converter Electrical Characteristics (Vdd = 3V, Gnd = 0V, T A = 25℃, Unless Otherwise Specified )

    SH79F166A (continue) Parameter Symbol Min. Max. Unit Condition Typ.∗ ——-------—— , T2, T3, T4, INT0/1/2/3/4, T2EX, 0.2 X V RXD (RxCON[1:0] = 00), TXD, FLT, = 2.4 - 5.5V Input Low Voltage 2 0.4 X V RXD (RxCON[1:0] = 01), V = 2.4 - 5.5V...

  • Page 106: Ac Electrical Characteristics

    SH79F166A AC Electrical Characteristics (V = 2.0V - 5.5V, GND = 0V, T = 25°C, f = 12MHz, unless otherwise specified) Parameter Symbol Min. Typ. Max. Unit Condition = 32.768kHz Oscillator start time = 12MHz µs RESET pulse width Low active...

  • Page 107: Application

    SH79F166A 11. Application 4 X 12 LCD Display Power Supply +12V 7805 4X12 47uF/16V COM1-4 0.1uF SEG1-12 0.1uF 100uF INT0 IR RECEIVER 12pF OSCXI DRIVER SH79F166A DRIVER 12pF OSCXO P0.1 32.768kHz P0.0 to relay P5.0 P2.7 to relay P5.1 P2.6 P5.2...

  • Page 108: Ordering Information

    SH79F166A 12. Ordering Information Part No. Package SH79F166AF/044FR QFP44 SH79F166AP/044PR LQFP44...

  • Page 109: Package Information

    SH79F166A 13. Package Information QFP 44 Outline Dimensions (BODY SIZE: 10*10) unit: inch/mm See Detail F DETAIL F Seating Plane Symbol Dimensions in inches Dimensions in mm 0.106 Max. 2.70 Max. 0.012 Max. 0.3 Max. 0.079 ± 0.004 2.00 ± 0.10 0.134 ±...
  • Page 110 SH79F166A LQFP 44 Outline Dimensions unit: inch/mm See Detail F DETAIL F Seating Plane Dimensions in inches Dimensions in mm Symbol 0.057 0.065 1.45 1.65 0.000 0.001 0.01 0.21 0.051 0.059 0.388 0.400 9.85 10.15 0.388 0.400 9.85 10.15 0.465 0.48...

  • Page 111: Product Spec. Change Notice

    SH79F166A 14. Product SPEC. Change Notice Version Content Date Update Package Information Jul. 2015 Add LQFP44 package information Modify the corresponding description of Baudrate including its computational formula Dec. 2013 Modify clerical error Add the description about using High frequency oscillator Code option update May.

  • Page 112: Table Of Contents

    SH79F166A Content FEATURES ..................................1 GENERAL DESCRIPTION .............................. 1 BLOCK DIAGRAM ................................2 PIN CONFIGURATION ..............................3 PIN DESCRIPTION ................................. 6 SFR MAPPING ................................8 NORMAL FUNCTION ..............................18 7.1 CPU ........................................18 7.1.1 CPU Core SFR .................................... 18 7.1.2 Enhanced CPU core SFRs ................................19 7.1.3 Register ......................................
  • Page 113 SH79F166A 8.3.3 PWM Timer Lock Register ................................71 8.3.4 12-bit PWM Timer ..................................72 8.3.5 PWM01 ......................................74 8.3.6 Dead Time ....................................75 8.4 EUART ....................................... 76 8.4.1 Feature ......................................76 8.4.2 EUART Mode Description ................................76 8.4.3 Baud Rate Generate ..................................81 8.4.4 Multi-Processor Communication ..............................

Table of Contents

Save PDF