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Sino Wealth SH61F83 Manual

Low speed usb micro-controller

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Features
 8-bit CMOS Micro-Processor (uP) core
- Instruction set is compatible with standard 8051
- Build-in 6MHz RC Oscillator for USB and MCU
 Memory
- 14K Bytes MTP (Multiple Times Programmable) Rom,
endure 8 write/erase cycles
- The last 16 bytes (37F0H-37FFH) are reserved and not
supposed to be used
- 256 bytes internal data memory
 Operation voltage 4.4V - 5.25V
 One set of Time Capture Circuit (Rising and Falling edge)
 Build-in 32KHz oscillator for programmable wake up timer
 3.3V regulator output
- Maximum driving current 20mA
 Up to 37 general purpose I/O ports in 48 pin QFN
package
 Interrupt
- 11 vectors interrupt structure
- 2 programmable priority levels
 Two 8-Bit auto-reloadable Base Timer
General Description
The SH61F83 is designed for high performance, high integrated Low-speed USB devices and capable of USB
In-System-Programming. It contains an 8051 micro-controller, Low-Speed USB SIE, Transceiver and data FIFO, build-in 3.3V
regulator, on-chip 14K bytes MTP program memory and internal 256 bytes data memory, Two 8-Bit auto-reloadable Base
Timer, programmable Watch-dog timer and Wake-up timer, 37 selectable GPIO in 48 pin QFN package, build-in 6MHz
oscillator to eliminate external crystal, POR and LVR circuit saving your external components cost. The SH61F83 is a highly
integrated MCU designed for cost effective applications. Application can cover such items as Keyboards and others.
Low Speed USB Micro-controller
 USB Specification Compliance
- Complies with USB specification 1.1
- Support one Low-Speed USB Device Address with
3 endpoints (endpoint 0, 1, and 2)
- Built-in 1.5Kohms USB pull-up resistor
 Built-in Watch Dog Timer (WDT)
 Two blue LED port
 Reset
- Hardware reset
- External reset, Power-on reset, Low-voltage reset
- USB reset
- Watch-Dog reset
- Resume reset
 Two power-reducing modes:
- Idle mode
- Power-Down mode
 Package:
- 52 pad Chip Form
- 48 pin QFN (6 X 6)
1
SH61F83
V2.0

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Summary of Contents for Sino Wealth SH61F83

  • Page 1 Timer, programmable Watch-dog timer and Wake-up timer, 37 selectable GPIO in 48 pin QFN package, build-in 6MHz oscillator to eliminate external crystal, POR and LVR circuit saving your external components cost. The SH61F83 is a highly integrated MCU designed for cost effective applications. Application can cover such items as Keyboards and others.
  • Page 2: Pin Configuration

    Pin Configuration 48 47 46 45 44 43 42 41 40 39 38 37 P46/VDM/EXT0 SH61F83Q P36/BLED0 P37/BLED1 RSTB P15/TC0 13 14 15 16 17 18 19 20 21 22 23 24 SH61F83 48-Pin (QFN) Package Pad Configuration VCDRIN SH61F83 REST...
  • Page 3: Block Diagram

    SH61F83 Block Diagram VDP/P45 1.8V USB Transceiver 6MHz OSC REGULATOR VDM/P46/EXT0 8051 Power Down Mode USB SIE Controller Serial Bus Interrupt Controller Manager Wake-up Timer 14K Bytes MTP Program Memory USB Data FIFO 32KHz OSC 256 Bytes DATA RAM Low Voltage Reset...
  • Page 4 SH61F83 Pin and Pad Description PIN No. PAD No. Designation Description P46/VDM/EXT0 Bi-directional I/O pin shared with VDM Bi-directional I/O pin Bi-directional I/O pin Bi-directional I/O pin Bi-directional I/O pin Bi-directional I/O pin Bi-directional I/O pin P36/BLED0 Bi-directional I/O pin...
  • Page 5: Functional Description

    1.3. Data Memory The SH61F83 provides additional Bytes of RAM space for increased data parameter handling, high level language usage. The SH61F83 has internal data memory that is mapped into three separate segments. The Three segments are: 1.
  • Page 6 SH61F83 1.4. Registers System Registers Address Name Init. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00E0H ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 00F0H 00D0H 0081H 0082H DPL7 DPL6 DPL5 DPL4 DPL3 DPL2 DPL1 DPL0 0083H DPH7 DPH6...
  • Page 7 SH61F83 Registers (continued) Interrupt Control Register Addr. Name Init. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00A8H ETC0 EEXT0 00A9H EFUN ESIE EOUT0 EIN0 EOT0ERR EOWSTUP ESTUP 00B8H PTC0 PEXT0 00B9H PFUN PSIE POUT0 PIN0 POT0ERR POWSTUP PSTUP 00DAH...
  • Page 8 SH61F83 2. Interrupt and Reset Vectors  External Interrupt 0  OT0ERR Interrupt  Base Timer 0  IN0 Interrupt  Base Timer 1  OUT0 Interrupt  Time Capture Interrupt 0  SIE Interrupt (NAKT0, NAKR0, T0STL, R0STL, NAK1,NAK2, IN1, IN2) ...
  • Page 9 3.2. Special Function Registers (SFRs) The SH61F83 has a total of 63 SFRs, as shown in the figure below - SFR Map for SH61F83. Note that not all the addresses are occupied by SFR’s. The unoccupied addresses are not implemented and should not be used by the customer. Read access from these unoccupied locations will return unpredictable data, while write accesses will have no effect on the chip.
  • Page 10 SH61F83 3.2.1. Accumulator (ACC) ACC is the accumulator register used for most of the arithmetic and logical instructions. Its initial value is 00h. 3.2.2. B Register (B) The B register is an SFR which is used primarily in the multiply and divide instructions. It can also be used as a temporary scratch pad register for the other instructions and its initial value is 00h.
  • Page 11 SH61F83 3.3. Instruction Set List Arithmetic Instructions Opcode Bytes Cycles Meaning A, Rn Add reg to acc A, @Ri Add indir byte to acc A, direct Add dir byte to acc A, #data Add imm. Data to acc A, Rn...
  • Page 12 SH61F83 Instruction Set List (continued) Rotate acc left Rotate acc left through the carry Rotate acc right Rotate acc right throught the carry SWAP Swap nibbles within the acc Data Transfer Opcode Bytes Cycles Meaning A, Rn Move reg to acc...
  • Page 13 SH61F83 Instruction Set List (continued) Program Branching Opcode Bytes Cycles Meaning (not taken) Jump if carry is set Jump if less than (taken) (not taken) Jump if carry is not set Jump if greater than or equal (taken) (not taken)
  • Page 14 5.1.1. Power-On Reset (POR) and LVRA When power is first applied to the SH61F83, the internal Power-On Reset will be generated and reset the whole chip. This process is fulfilled by a power-on reset circuit and an auxiliary Lower-voltage reset circuit (LVRA) monitoring V .
  • Page 15 SH61F83 5.1.2. Low Voltage Reset (LVR) (1) Low Voltage Reset 1 (LVR1) 00AFH PRCON Initial Value Power-reducing Control Register Bit[7:3] 00000b Reserved 1: Enable Watch-Dog timer under idle mode Bit2 ENWDT 0: Disable Watch-Dog timer under idle mode Reset source: Hardware reset, USB reset, or Resume Reset...
  • Page 16 SH61F83 (2) Low Voltage Reset (LVR2) The embedded Low-Voltage Reset (LVR2) circuit monitors the 3.3V regulator output Voltage. It will generate an internal reset to the whole chip while heavy loads at 3.3V regulator output switched on which cause the regulator output voltage temporarily fall below the minimum specified operating voltage.
  • Page 17 SH61F83 5.2. Watch-dog Timer Reset The SH61F83 implements a Watchdog timer to avoid system stop or malfunction. The clock source of the WDT is F . The time-out interval of Watchdog timer is selected by PREWDT[1:0]. The Watchdog timer must be cleared within time-out period;...
  • Page 18 5.3.1. IDLE Mode Two continuous instructions that set PCON.0 to ‘1’ and set SUSLO to ‘55H’ let the SH61F83 enter IDLE mode. In IDLE mode, the internal clock signal is gated off to the CPU only. The CPU status is preserved in its entirety: the Stack Pointer, Program Counter, Program Status Word, Accumulator, and all other registers maintain their value during IDLE mode.
  • Page 19 SH61F83 00A2H P0WK Initial Value Port0 Resume Enable Register 1: Enable wake-up function of PORT0’s pins (Low level trigger) Bit[7:0] P0WK[7:0] 0: Disable wake-up function of PORT0’s pins (Low level trigger) Reset source: Hardware reset 00A3H P1WK Initial Value Port1 Resume Enable Register 1: Enable wake-up function of PORT1’s pins (Low level trigger)
  • Page 20 SH61F83 5.3.2. Power-down Mode Method of entering Power-down mode: set PCON.1 = 1 and set SUSLO = 55h  In the Power- down mode, the on-chip oscillator stops.  With the clock frozen, all functions are stopped, but the on-chip RAM and Special function Registers are held.
  • Page 21 SH61F83 Port resume reset example 2: Assume that PORT2 is resume source and F/W issues K-State when Resume Reset occurs. PWRDN_FW: PORT2 #FFH ; initialize PORT2 resume source to be high. P2WK #FFH ; Enable PORT2 resume ability. PORT0 #00H ; Pull low PORT0.
  • Page 22 SH61F83 Wake-up Timer Time out Resume Reset Power-down Mode Wake-up Timer Timeout Period[1:0] Reset Figure 5-9. Wake-up Timer Time Out Waveform USB Bus Non-idle State Resume Reset  Resume reset after Non-idle event Power-down Mode Non-idle event 2.7ms Reset Figure 5-10. USB Non-idle Resume Reset Waveform ...
  • Page 23 SH61F83 5.4. Wake-up Timer  The SH61F83 has a Built-in 32KHz Ring-Oscillator. It is the clock source of wake-up timer. The 32KHz Ring-Oscillator will start when the control register WKT[3:2] was not equal to #00b.  The wake-up timer can only be enabled/disabled by WKT[3:0] (WKT[3:0] not equal to 00xxb).
  • Page 24 SH61F83 Hardware Resume USB Reset Reset Routine Reset Reset Clear Register Clear Register Clear Register Next instruction Clear Register with USB with H/W with Resume with WDT Reset follows idle Reset Reset Source Source mode Source Source Normal Run (PC=0000H)
  • Page 25 SH61F83 6. Input/Output Ports 6.1. Port-0 Configuration: (Reset source: Hardware reset) Control Bits I/O Port Function Circuit Structure Description P0.x P0CON.x Output Low (0.4V, min: 4mA) Port0[7:0] Port0 Shown in Figure 6-1 Output High (2.4V, min: -50uA) HI-Z Note: P02 and P03 have the Schmitt trigger functions.
  • Page 26 SH61F83 Figure 6-1. PORT Configuration-1 Weakly Weakly Disable Pull Up Pull Up Output Port PnSELx Output Data (I/O Port Reg) Read in Data Input Select Figure 6-2. PORT Configuration-2...
  • Page 27 SH61F83 6.6. USB VDM/P46 Configuration: (Reset source: Hardware reset) USB_CON PULL_UP VPCON P4CON6 Description P46 output in Hi-Z mode, Read P46 will get the value on pad P46 1.5K ohm pull-up resistor active when bit “PULL_UP” = “1”, P46 in Hi-Z mode, Read P46 will get the value on pad P46 Output Low (0.4V, min: 8mA)
  • Page 28 Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the SFR named IE, IE2, IRQEN, IRQEN2. The register IE also contains a global disable bit, which can be cleared to disable all interrupts at once. Figure 7-1 shows the interrupt register for the SH61F83. Interrupt Enable Register...
  • Page 29 SH61F83 00DCH IRQEN Initial Value SIE Interrupt Enable Register Bit7 EIN2 R/W IN2 interrupt Bit6 EIN1 R/W IN1 interrupt Bit5 ER0STL R/W R0 stall interrupt Bit4 ET0STL R/W T0 stall interrupt Bit3 ENAK2 R/W T2 NAK interrupt Bit2 ENAK1 R/W T1 NAK interrupt...
  • Page 30 SH61F83 (IE) Interrupt EEXT0 (0003H) Event ET0 (000BH) (TCCON) ET1 (001BH) TC0F_INT TC0R_INT ETC0 (0023H) (IRQEN) EIN2 EIN1 ENAKT0 ENAKR0 ENAK1 ENAK2 ESTUP (0043H) ET0STL EOWSTUP (004BH) EOT0ERR (0053H) ER0STL EIN0 (005BH) EOUT0 (0063H) ESIE (006BH) ESUSP EOVL EFUN (0073H)
  • Page 31  Each interrupt source can also be individually programmed to one of the two priority levels by setting or clearing a bit in the SFR named IP (Interrupt Priority) and IP2. The Following figure shows the IP & IP2 register in the SH61F83.
  • Page 32 SH61F83 7.3. Interrupt Flag 00DAH Initial Value Interrupt Control Flag Bit[7:5] Reserved Time Capture 0 Interrupt flag. Set by hardware when the eight bits are received or end condition is detected. Cleared by hardware when interrupt is Bit4 processed. Write “0” to clear, write “1” no effect.
  • Page 33 When IN token for endpoint 1 is done, it will set the IN1 flag. Bit6 Write “0” to clear, write “1” no effect. Reset Source: Hardware reset or USB reset When SH61F83 responds STALL to OUT0 tokens, R0_STL will be set. Bit5 R0STL Write “0” to clear, write “1” no effect.
  • Page 34 SH61F83 8. Base Timer  The Timer-x is an 8-bit counter with a programmable clock source selection and the value of Base Timer-x counter can be read out any time.(x = 0, 1)  The Base Timer-x can be enabled/disabled by the CPU. After reset, the Base Timer-x is disabled and cleared.
  • Page 35 9. Time Capture 0 The SH61F83 provide one set of Time Capture I/O pins, TC0, the Time Capture input provides both rising and falling edge 8 bits time register. A PreScaler allows TCAP0 to select 8 types of time capture tick size (From 2us to 16us).
  • Page 36 SH61F83 00C9H TCCON Initial Value Time Capture Control Register Bit[7:6] Reserved Enable force clear TCAP0 free-run counter control bit 0: TCAP0 free-run counter is continued. 1: Enable force clear TCAP0 free-run counter function. Bit5 TC_CLREN When force clear function enable, TCAP0 free-run counter is clear when a rising or falling edge is detected on TC0 pad.
  • Page 37 SH61F83 Following figures show how Time Capture function works on TC0 input signal with different H/W setting condition TC_CLREN = 0, EA = 1, ETC0 = 1, TC0F_INT = 0, TC0R_INT = 1 TC0 Input 8 bit Free Run D9 DA...
  • Page 38 SH61F83 TC_CLREN = 1, TC_OVLEN = 0 TC0F_INT = 0, TC0R_INT = 1, EA = 1, ETC0 = 1, TC0 Input 8 bit Free Run D0 D1 Counter TCAP0R Register TCAP0F Register TC0R_FULL TC0F_FULL TC0_OVL ETC0 IRQ (F/W read TCAP0R & TCAP0F register) (F/W read TCAP0R &...
  • Page 39 SH61F83 10. USB Control Register 10.1. DADDR USB Device Address Register 00F2H DADDR Initial Value Device Address Register Bit7 Reserved USB Device address Reset Source: Hardware reset (External reset, Power-on reset and Bit[6:0] DADDR[6:0] 0000000B Low-Voltage reset) or USB reset) 10.2.
  • Page 40 SH61F83 10.3. TXDATx USB Transmit FIFO Data Register, x = 0/1/2 for Endpoint 0/1/2. The byte count of the transmitted data must be equal to or less than 8. 00EAH TXDAT0 Initial Value USB TX FIFO 0 Data Register Transmit FIFO 0...
  • Page 41 SH61F83 00E4H TXFLG1 Initial Value USB TX FIFO 1 Flag/Control Register Bit[7:4] 0000B Reserved This bit is used to enable/disable the endpoint 1 1: Enable endpoint 1 Bit3 T1EPE 0: Disable, the corresponding endpoint does not respond to a valid IN Token...
  • Page 42 SH61F83 The TX FIFO operational model refers to Figure10-1. In the following, the related F/W procedures and H/W actions are described. (1) After Hardware Reset or USB Reset, the TxFULL bit in TXFLGx will reset to 0 to announce no data in FIFOs (x = 0/1/2).
  • Page 43 ACK if no bit stuffing error or CRC error. Bit2 OUT0ENB 1: The SH61F83 will respond OUT0 token with NAK. Reset Source: Hardware reset or USB reset Pipe 0 stall bits. STLR0 bit is used to stall the pipe 0 OUT token.
  • Page 44 SH61F83 CRSEQ STLCR STLCW Valid OUT0 Data 0 Valid OUT0 Data 1 Valid IN0 Token Note STLT0 = 0 & STLR0 = xx STLT0 = 0 & STLR0 = xx STLT0 = xx & STLR0 = 0 STLT0 = 0 & STLR0 = xx STLT0 = 0 &...
  • Page 45 11. MTP (Multiple Times Programmable) Program Memory The SH61F83 embeds 14K MTP program memory for program code, which endure 8 write/erase cycles. The MTP program memory can be electrical erased and programmed by HidUpdate4.exe. The erasure and programming steps as follows: Note: 37F0H - 37FFH bytes are reserved and not supposed to be used.
  • Page 46 8. If fails, wait for another 5 seconds, and Click WRITE IC again to do Erase/Program/Verify 9. After the software shows being finished, click EXIT 10. Reconnect the USB Cable (or Scroll On/Off), SH61F83 will run with the new User Program...
  • Page 47 SH61F83 12. Electrical Characteristics Absolute Maximum Ratings* *Comments DC Supply Voltage ....-0.3V to +7.0V Stresses above those listed under "Absolute Maximum Ratings"...
  • Page 48 SH61F83 (continued) Reset (DC) Power-on Reset Level Auxiliary Lower-voltage Reset Level LVRA Low Voltage Reset 1 Level LVR1 Low Voltage Reset 2 Level LVR2 Upper Threshold Voltage for external Reset UT(RESET) Lower Threshold Voltage for external Reset LT(RESET) AC Electrical Characteristics (V = 5V, GND = 0V, T = 25°C, f...
  • Page 49 SH61F83 USB DC/AC Specifications  Please refer to the UNIVERSAL SERIAL BUS specification Version 1.1 Chapter 7.  Some items are listed in the following table.  In addition, the crossover point voltage should meet the following specifications. PARAMETER SYMBOL MIN.
  • Page 50 SH61F83 Application Circuit (For Reference Only) Optional (depend on application) SH61F83 LED0 Scroll Lock LED1 Num Lock LED2 Caps Lock RSTB 0.1 m F Optional (depend on application) Optional (depend on application) to PC 4.7 m F K133 & <...
  • Page 51 SH61F83 Ordering Information Part No. Package SH61F83H-HAxxx Chip Form SH61F83Q/048QR-HAxxx QFN48 (6 X 6) Note: ‘xxx’ is the code number assigned by Sinowealth.
  • Page 52 SH61F83 Package Information QFN 48L (6 X 6) Outline Dimensions unit: inches/mm...
  • Page 53: Bonding Diagram

    SH61F83 Bonding Diagram VCDRIN SH61F83 RSTB REST unit: μm Pad Location Pad NO. Pad Name 48QFN Pad NO. Pad Name 48QFN PORT4[6] 674.32 -288.9 PORT1[6] -633.24 691.78 PORT3[0] 674.32 -207.9 PORT1[7] -674.32 73.37 PORT3[1] 674.32 -126.9 PORT2[0] -674.32 -7.63 PORT3[2] 674.32...
  • Page 54 SH61F83 Data Sheet Revision History Revision No. History Date Add notice, P20, P39 Feb. 2018 Original Jun. 2013...