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Sino Wealth SH69P561 Manual

Otp/mask 4k 4-bit micro-controller with lcd driver & 8-bit sar adc

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OTP/MASK 4K 4-bit Micro-controller With LCD Driver & 8-bit SAR ADC
Features
SH6610D-Based Single-Chip 4-bit Micro-Controller With
LCD Driver & 8-bit SAR ADC
OTP ROM: 4K X 16 bits (SH69P561)
MASK ROM: 4K X 16 bits (SH69K561)
RAM: 274 X 4bits
- 58 System control register
- 216 Data memory
- 72 bits LCD RAM
Operation Voltage:
- f
= 32.768kHz - 4MHz, V
OSC
- f
= 4MHz - 8MHz, V
OSC
15 CMOS Bi-directional I/O Pins
8-Level Stack (Including Interrupts)
Two 8-bit Auto Re-Loaded Timer/Counter
Warm-Up Timer
Powerful Interrupt Sources:
- A/D Interrupt
- Timer0 Interrupt
- Timer1 Interrupt
- External Interrupts: PORTB (Rising/Falling Edge)
2 Clock Oscillator
OSC:
- Crystal Oscillator: 32.768kHz
- RC Oscillator: 262kHz
OSCX:
- Ceramic/Crystal Oscillator: 400kHz - 8MHz
- RC Oscillator: 400kHz - 8MHz
General Description
SH69P561/69K561 is a single-chip 4-bit micro-controller. This device integrates a SH6610D CPU core, RAM, ROM, timer, LCD
driver, I/O ports, EL-light driver, watchdog timer, 5 channels 8-bit ADC, alarm generator, low voltage reset, 2 channels 10-bit
high speed PWM output, zero cross detect function. This chip builds in a dual-oscillator to enhance the total chip performance.
SH69P561/69K561 is suitable for the home appliance application.
= 2.4V - 5.5V
DD
= 4.5V - 5.5V
DD
Instruction Cycle Time (4/f
Two Low Power Operation Modes: HALT And STOP
Reset
- Built-in Watchdog Timer (WDT) (Code Option)
- Built-in Power-on Reset (POR)
- Built-in Low Voltage Reset (LVR) (Code Option)
LCD Driver:
18SEG X 4COM (1/4 duty, 1/3 bias)
2 Channels 10-bit PWM output
5 Channels 8-bit Resolution Analog/Digital Converter
(ADC)
Built-in Pull-high/Pull-low Resistor for PORTA - PORTE
Built-in Alarm Generator
Built-in Electroluminescent Light (EL-light) Driver
ROM Data Read Table function
Zero Cross Detect function for AC Power Line
LCD shared as LED matrix (Code Option)
LCD SEG 9-28 shared with scan output
OTP type & Code Protect (SH69P561)
MASK type (SH69K561)
44-pin QFP package
1
SH69P561/K561
)
OSC
V2.1

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Summary of Contents for Sino Wealth SH69P561

  • Page 1 - RC Oscillator: 400kHz - 8MHz General Description SH69P561/69K561 is a single-chip 4-bit micro-controller. This device integrates a SH6610D CPU core, RAM, ROM, timer, LCD driver, I/O ports, EL-light driver, watchdog timer, 5 channels 8-bit ADC, alarm generator, low voltage reset, 2 channels 10-bit high speed PWM output, zero cross detect function.
  • Page 2 SH69P561/K561 Pin Configuration (44 QFP Package) 30 29 SEG19 TEST SEG18 RESET SEG17 OSCI SEG16 OSCO SEG15 SH69P561/K561 SEG14 SEG13 PORTE.3/SEG8 OSCXO PORTE.2/SEG7 OSCXI PORTE.1/SEG6 PORTE.0/SEG5 10 11...
  • Page 3 , AV Programming Power supply (+5.5V) Programming high voltage Power supply (+11.0V) RESET AGND, GND Ground OSCI Programming Clock input Pin/Pad PORTA.0 Programming Data Pin/Pad *: Only SH69P561 has the OTP Program Mode, SH69K561 has not the OTP Program Mode...
  • Page 4: Block Diagram

    SH69P561/K561 Block Diagram OSCI/SCK WDT RC OSCO RESET Reset Circuit Oscillator OSCXI Watchdog OSCXO Timer PORTA.2 - 0 58 X 4 bits PORTA.2 - 0 System Register 8 bits ADC Circuit ADC V AN2 - AN0 216 X 4 bits Data Memory PORTB.3 - 0...
  • Page 5: Functional Descriptions

    SH69P561/K561 Functional Descriptions 1. CPU The CPU contains the following functional blocks: Program 1.4. Table Branch Register (TBR) Counter (PC), Arithmetic Logic Unit (ALU), Carry Flag (CY), Table Data can be stored in program memory and can be Accumulator, Table Branch Register, Data Pointer (INX, referenced by using Table Branch (TJMP) and Return DPH, DPM, and DPL) and Stacks.
  • Page 6 SH69P561/K561 2.2. Configuration of System Register: Address Bit 3 Bit 2 Bit 1 Bit 0 Remarks IEAD IET0 IET1 IEPB R/W Interrupt enable flags register IRQAD IRQT0 IRQT1 IRQPB R/W Interrupt request flags register T0M.2 T0M.1 T0M.0 R/W Bit2-0: Timer0 Mode register T1M.2...
  • Page 7 SH69P561/K561 Configuration of System Register (Continued) Address Bit 3 Bit 2 Bit 1 Bit 0 Remarks Bit0: EL-light on/off control register ELPF ELON Bit1: EL-light driver charge frequency control register Bit2: EL-light driver discharge frequency control register WDT.2 WDT.1 WDT.0...
  • Page 8 SH69P561/K561 3. ROM The ROM can address 4096 X 16 bits of program area from $000 to $FFF. 3.1. Vector Address Area ($000 to $004) The program is sequentially executed. There is an area address $000 through $004 that is reserved for a special interrupt service routine such as starting vector address.
  • Page 9 SH69P561/K561 4. Initial State 4.1. System Register State: Power On Reset Address Bit 3 Bit 2 Bit 1 Bit 0 /Pin Reset WDT Reset /LVR IEAD IET0 IET1 IEPB 0000 0000 IRQAD IRQT0 IRQT1 IRQPB 0000 0000 T0M.2 T0M.1 T0M.0...
  • Page 10 SH69P561/K561 System Register States (continued) Power On Reset Address Bit 3 Bit 2 Bit 1 Bit 0 /Pin Reset WDT Reset /LVR xxxx uuuu xxxx uuuu LCDON RLCD1 RLCD0 -000 -uuu LPS1 LPS0 00xx uuxx O/S2 O/S1 000x u00x $380...
  • Page 11 (5) 4/8MHz (= 0.5µs) for 8MHz oscillator. 5.2. Circuit Configuration SH69P561/69K561 has two on-chip oscillation circuits: the OSC and the OSCX. The OSC is a low frequency crystal (Typ. 32.768kHz) or RC (Typ.262kHz) determined by the code option. This is designed for low frequency operation.
  • Page 12 SH69P561/K561 5.3. OSC Oscillator The OSC generates the basic clock pulses that provide the CPU and peripherals (Timer0, Timer1) with an operating clock. (1) OSC Crystal Oscillator (2) OSC RC Oscillator OSCI OSCI 32.768kHz OSCO External R 5.4. OSCX Oscillator OSCX has two clock oscillators.
  • Page 13 SH69P561/K561 5.6. Capacitor Selection for Oscillator Ceramic Resonators Recommend Type Manufacturer Frequency ZTB 455KHz Vectron International 455kHz 47 - 100pF 47 - 100pF ZT 455E Shenzhen DGJB Electronic Co., Ltd. ZTT 3.580M Vectron International 3.58MHz ZT 3.58M* Shenzhen DGJB Electronic Co., Ltd.
  • Page 14 SH69P561/K561 6. I/O Ports The MCU provides 15 bi-directional I/O ports. The PORT data is put in register $08 - $0C The PORT control register ($18 - $1C) controls the PORT as input or output. Each I/O port has an internal pull-high/pull-low resistor, which is controlled by PULLEN, PH/PL of $0D and the data of the port, when the PORT is used as input.
  • Page 15 SH69P561/K561 System Register $0D Address Bit3 Bit2 Bit1 Bit0 Remarks Bit0: Turn on OSCX oscillator control register Bit1: System clock control register Bit2: Port pull-high and falling edge interrupt or pull-low PULLEN PH/PL OXON and rising edge interrupt control register...
  • Page 16 SH69P561/K561 7. PORTB Interrupt The PORTB is used as port interrupt sources. Since PORTB I/O is bit programmable I/O, so only the digital input port can generate a port interrupt. The analog input can’t generate an interrupt request (when PORTB0, PORTB1 used as AN4, AN5).
  • Page 17 SH69P561/K561 8. Timer SH69P561/69K561 has two 8-bit timers. The timer/counter The low-order digit should be written first, and then the has the following features: high-order digit. The timer/counter is automatically loaded with the contents of the load register when the high-order - 8-bit up-counting timer/counter.
  • Page 18 SH69P561/K561 System Register $02: Timer0 Mode Register, when T0S0 = 1 T0M.2 T0M.1 T0M.0 Prescaler Clock Source System Register $02: Timer0 Mode Register, when T0S0 = 0 T0M.2 T0M.1 T0M.0 Prescaler Clock Source External Clock/Event T0 as Timer0 Source When external clock/event T0 input as Timer0 source, PORTC.3 is shared as T0 input and it is synchronized with OSC clock.
  • Page 19 SH69P561/K561 System Register $03: Timer1 Mode Register T1M.2 T1M.1 T1M.0 Prescaler Clock Source System clock /T0 System clock /T0 System clock /T0 System clock /T0 System clock /T0 System clock /T0 System clock /T0 System clock /T0 External Clock/Event T0 as Timer1 Source When external clock/event T0 input as Timer1 source, PORTC.3 is shared as T0 input and it is synchronized with the CPU...
  • Page 20 (4096). 11. HALT and STOP Mode After the execution of HALT instruction, SH69P561/69K561 will enter the HALT mode. In the HALT mode, CPU will stop operating. But peripheral circuit (Timer0, Timer1, ADC) will keep status. After the execution of STOP instruction, SH69P561/69K561 will enter the STOP mode. The whole chip (including oscillator) will stop operating.
  • Page 21 12. Pulse Width Modulation (PWM) The SH69P561/69K561 consists of two 10-bit PWM modules. The PWM module can provide the pulse width modulation waveform with the period and the duty being controlled, individually. The PWMC is used to control the PWM module operation with proper clocks.
  • Page 22: Programming Notes

    SH69P561/K561 Programming Notes: a. Select the PWM module system clock. b. Set the PWM period cycle by writing proper value to the PWM period control register (PWMP). First set the high nibble, then the middle nibble and the last set the low nibble.
  • Page 23 SH69P561/K561 13. Analog/Digital Converter (ADC) The 5 channels and 8-bit resolution ADC are implemented in this micro-controller. The ADC control registers can be used to define the A/D channel number, select analog channel, reference voltage and conversion clock, start A/D conversion, and set the end of A/D conversion flag. The A/D conversion result register byte is read-only.
  • Page 24 - ADC could keep on working in the HALT mode, and would stop automatic when execute “STOP” instruction. - ADC could wake-up SH69P561/69K561 from the HALT mode (if the ADC interrupt is enabled).
  • Page 25 SH69P561/K561 14. Alarm Output Alarm Output Configuration: Address Bit 3 Bit 2 Bit 1 Bit 0 Remarks Bit0: Alarm output enable control register ALMF1 ALMF0 PAM0 Bit2-1: Alarm carrier frequency control register R/W PORTC.2 is shared as I/O port (Power on initial) R/W PORTC.2 is shared as Alarm output...
  • Page 26 SH69P561/K561 15. EL-LIGHT System Register $1D: Address Bit 3 Bit 2 Bit 1 Bit 0 Remarks Bit0: EL-light on/off control register ELPF ELON Bit1: EL-light driver charge frequency control register Bit2: EL-light driver discharge frequency control register R/W EL-light driver turn off (Power on initial)
  • Page 27 SH69P561/K561 16. LCD Driver The LCD driver contains a controller, a voltage generator, 4 common and 18 segment driver pins. The driving mode is controlled by the system register $26. The LCD SEG13 - SEG26 can also be used as output port which is selected by the Bit2 of the system register $27. When SEG13 - SEG26 are selected to be output ports, the user should write data to bit x at the same addresses (35CH-369H).
  • Page 28 SH69P561/K561 16.2. Configuration of LCD RAM LCD 1/4 duty, 1/3 bias (COM1 - COM4, SEG5 - SEG8, SEG13 - SEG26) Bit3 Bit2 Bit1 Bit0 Bit3 Bit2 Bit1 Bit0 Address Address COM4 COM3 COM2 COM1 COM4 COM3 COM2 COM1 $304 SEG5...
  • Page 29 SH69P561/K561 16.4. Select Different Divider Resistance Address Bit 3 Bit 2 Bit 1 Bit 0 Remarks Bit1-0: Set LCD bias resistor register LCDON RLCD1 RLCD0 Bit2: Turn on LCD control register R/W R1 = R2 = R3 = 270k (Power on initial)
  • Page 30 SH69P561/K561 16.5. LCD Waveform 1/4 DUTY 1/3 BIAS SELECT UNSELECT V1 = V , V2 = 2/3V , V3 = 1/3V SELECT UNSELECT LCD Waveform of Different Duty and Bias CO M4 C O M1 C O M3 C O M2...
  • Page 31 SH69P561/K561 16.6. LCD shared to LED Application User can use SEG & COM in the application of LED matrix by code option and configuration of LED RAM is the same as LCD RAM. If LCD is off and LCD is shared to LED application, COM output V and SEG output GND.
  • Page 32 SH69P561/K561 COM1 COM2 COM1' COM3 COM2' COM4 COM3' SEG1 COM4' SEG2 SEG3 SEG1' SEG2' SEG3' SEG4'SEG5' SEG6' SEG7' SEG8' SEG9' SEG10' SEG4 SEG5 COMx' & SEGx'refer to the driving-amplified output of COMx & SEGx. SEG6 SEG7 SEG8 SEG9 SEG10 Example of 1/4 Duty 4 X 10 Dots 17.
  • Page 33: Interrupt Nesting

    SH69P561/K561 18. Interrupt Four interrupt sources are available on SH69P561/69K561: - A/D interrupt - Timer0 interrupt - Timer1 interrupt - PORTB interrupt Interrupt Control Bits and Interrupt Service The interrupt control flags are mapped on $00, $01, $14 and $15 of the system register. They can be accessed or tested by the program.
  • Page 34 SH69P561/K561 19. Code Option (a) OSC Type: 0 = 32.768kHz Crystal oscillator (Default) 1 = 262kHz RC oscillator (b) OSCX Type: 0 = Ceramic/Crystal oscillator (Default) 1 = RC oscillator (c) OSCX Range Select: 0 = 400kHz - 2MHz (Default)
  • Page 35 SH69P561/K561 Instructions All instructions are one cycle and one-word instructions. The characteristic is memory-oriented operation. 1. Arithmetic and Logical Instruction 1.1. Accumulator Type Mnemonic Instruction Code Function Flag Change ← Mx + AC + CY X (, B) 00000 0bbb xxx xxxx AC, Mx ←...
  • Page 36 SH69P561/K561 2. Transfer Instruction Mnemonic Instruction Code Function Flag Change ← Mx X (, B) 00111 0bbb xxx xxxx ← AC X (, B) 00111 1bbb xxx xxxx AC, Mx ← I X, I 01111 iiii xxx xxxx 3. Control Instruction...
  • Page 37: Electrical Characteristics

    SH69P561/K561 Electrical Characteristics Absolute Maximum Rating* *Comments Stresses exceed those listed under “Absolute Maximum DC Supply Voltage ....-0.3V to +7.0V Ratings” may cause permanent damage to this device.
  • Page 38 SH69P561/K561 DC Electrical Characteristics (continued) (V = 2.4 - 5.5V GND = 0V, T = 25 ℃ , unless otherwise specified) Parameter Symbol Min. Typ. Max. Unit Conditions X 0.3 PORTA - PORTE, V = 2.4V - 5.5V Input Low Voltage X 0.2...
  • Page 39 SH69P561/K561 AC Electrical Characteristics = 5.0V, GND = 0V, T = +25°C, f = 30kHz - 8MHz, unless otherwise specified. Parameter Symbol Min. Typ. Max. Unit Condition µs Instruction cycle time 133.4 T0 input width + 40)/N N = Prescaler divide ratio Input pulse width = 2.4V - 5.5V, GND = 0V, T...
  • Page 40 SH69P561/K561 RC Oscillator Characteristics Graphs Typical External Oscillator (OSC) Frequency vs. Operating Voltage: (for reference only) (R = 242 KΩ) R = 242kΩ 275.0 270.0 265.0 260.0 255.0 250.0 245.0 Typical External RC Oscillator (OSC) Resistor vs. Frequency: (for reference only) = 5.0V...
  • Page 41 SH69P561/K561 Typical External RC oscillator (OSCX) Frequency vs. Operating Voltage: (for reference only) (R = 12.9 KΩ) R = 12.9kΩ Typical External RC Oscillator (OSCX) Resistor vs. Frequency: (for reference only) = 5.0V 10.0 10.0 100.0 1000.0 R (kΩ)
  • Page 42 SH69P561/K561 Timing Waveform (a) System Clock Timing Waveform: System Clock (b) T0 Input Waveform: IPW(L) IPW(H) T0 input signal...
  • Page 43 SH69P561/K561 In System Programming Notes for OTP The In System Programming technology is valid for OTP chip. The Programming Interface of the OTP chip must be set on user’s application PCB, and users can assemble all components including the OTP chip in the application PCB before programming the OTP chip. Of course, it’s accessible bonding OTP chip only first, and then programming code and finally assembling other components.
  • Page 44 SH69P561/K561 Application Circuit (for reference only) Ap1: (1) Operating voltage: 5.0V (2) OSC: Crystal oscillator 32.768kHz (code option) OSCX: Ceramic oscillator 455kHz (code option) (3) PORTA - PORTB: PORTC.2: Alarm ouput (4) LCD: 1/4 duty, 1/3 bias 4 X 18...
  • Page 45: Ordering Information

    SH69P561/K561 Ordering Information Part No. Package SH69P561F 44 QFP SH69K561F 44 QFP...
  • Page 46: Package Information

    SH69P561/K561 Package Information QFP 44 Outline Dimensions unit: inch/mm See Detail F DETAIL F Seating Plane Symbol Dimensions in inches Dimensions in mm 0.106 Max. 2.70 Max. 0.01 Min. 0.02Max. 0.25 Min. 0.50Max. 0.079+0.008 2.00+0.2 -0.004 -0.1 0.012 Typ. 0.30 Typ.
  • Page 47: Data Sheet Revision History

    SH69P561/K561 Data Sheet Revision History Version Content Date Package information update Dec.2008 Revise the Timer0 clock source from “System clock” to “f /4” Jul. 2006 Original Mar. 2006...

This manual is also suitable for:

Sh69k561