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Sino Wealth SH79F1622 Manual

8051 microcontroller with 20 channels touch-key input and tone
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8051 Microcontroller with 20 channels Touch-key input and TONE
1.

Features

8bits micro-controller with Pipe-line structured 8051
compatible instruction set
Flash ROM: 16K Bytes
RAM: internal 256 Bytes, external 1280 Bytes
Operation Voltage: 2.7V - 5.5V
Oscillator:
- Internal RC: 27MHz (±2%)
- External crystal oscillator: 32.768kHz
28pin: 25 CMOS bi-directional I/O pins
20pin: 17 CMOS bi-directional I/O pins
Built-in pull-up resistor for input pin
Three 16-bit timer/counters T2, T3 & T4
20 channels Touch Key input
Built-in Touch Key comparison voltage:
1V, 1.5V, 2V, 2.5V
7 COM 16 SEG LED drive

2. General Description

The SH79F1622 is a high performance 8051 compatible micro-controller, regard to its build-in Pipe-line instruction fetch
structure, that helps the SH79F1622 can perform more fast operation speed and higher calculation performance, if compare
SH79F1622 with standard 8051 at same clock speed.
The SH79F1622 retains most features of the standard 8051. These features include internal 256 bytes RAM, three 16-bit
Timer/Counter. In addition, SH79F1622 provides external 1280 bytes RAM, It also contains 16K bytes Flash memory block for
storing programs.
SH79F1622 also integrate double channels tone generation module, LVR, TWI and Touch Key sharing with LED for saving pins.
SH79F1622 is very suitable for the application and control of Touch Key.
Also WDT and EUART are incorporated in SH79F1622.
Touch Key sharing with LED drive
Powerful interrupt sources:
- Timer2, 3, 4
- INT0, INT1, INT2, INT4
- EUART
- Touch Key
- TWI
EUART with Baud-rate generator
TWI communication interface
Built-in 2 channels programmable tone generator
CPU Machine cycle: 1 oscillator cycle
Watch Dog Timer (WDT)
Flash Type
Package: SOP28
SOP20
SOP16
1
SH79F1622
V2.2

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Summary of Contents for Sino Wealth SH79F1622

  • Page 1: Features

    Timer/Counter. In addition, SH79F1622 provides external 1280 bytes RAM, It also contains 16K bytes Flash memory block for storing programs. SH79F1622 also integrate double channels tone generation module, LVR, TWI and Touch Key sharing with LED for saving pins. SH79F1622 is very suitable for the application and control of Touch Key.

  • Page 2: Block Diagram

    SH79F1622 3. Block Diagram Reset circuit Pipelined 8051 architecture Power Watch Dog 16K Bytes Flash ROM Touch key channel TK1-TK20 Internal 256 Bytes External 1280 Bytes (Exclude System Port 3 Register) Configuration I/Os P3.0 ` Port 2 Timer 2 (16bit)

  • Page 3: Pin Configuration

    SH79F1622 4. Pin Configuration SOP 28 TK4/SEG3/P0.3 P0.4/SEG4/TK5/TCK TK3/SEG2/P0.2 P0.5/SEG5/TK6/TDI XTAL2/TK2/SEG1/P0.1 P0.6/SEG6/TK7/TMS XTAL1/TK1/SEG0/P0.0 P0.7/SEG7/TK8/TDO P2.0/SEG8/TK9 P2.1/SEG9/TK10 79F1622 P2.2/SEG10/TK11 T4/COM1/P1.0 P2.3/SEG11/TK12 T2EX/TK17/COM2/P1.1 P2.4/SEG12/TK13 TK18/COM3/P1.2 P2.5/INT2/SEG13/TK14 TK19/COM4/P1.3 P2.6/INT1/SEG14/TK15 TK20/COM5/P1.4 P2.7/INT0/SEG15/TK16 P3.0/INT43/SDA/RXD T2/TONE/COM6/INT40/P1.5 P1.7/INT42/SCK/TXD RST/T3/COM7/INT41/P1.6 Pin Configuration Diagram SOP 28 SOP 20 TK4/SEG3/P0.3 P0.4/SEG4/TK5/TCK...
  • Page 4 Note: 1. SH79F1622 (SOP16) I/O (20PIN P0.3, P1.2, P1.6, P1.1), which is set to output low level, to avoid functional conflicts. 2. The out most pin function has the highest priority, and the inner most pin function has the lowest priority (Refer to Pin Configuration Diagram).
  • Page 5 T2/TONE/COM6/INT40/P1.5 P1.5 XTAL1/TK2/SEG0/P0.0 P0.0 TXD/SCK/INT42/P1.7 P1.7 ---- RXD/SDA/INT43/P3.0 P3.0 ---- TDO/TK8/SEG7/P0.7 P0.7 ---- TMS/TK7/SEG6/P0.6 P0.6 T4/COM1/P1.0 P1.0 TDI/TK5/SEG5/P0.5 P0.5 ： Note SH79F1622 (SOP16) I/O (20PIN P0.3, P1.2, P1.6, P1.1), which is set to output low level, to avoid functional conflicts.

  • Page 6: Pin Description

    SH79F1622 5. Pin Description Pin No. Type Description I/O PORT P0.0 - P0.7 8 bit General purpose CMOS I/O P1.0 - P1.7 8 bit General purpose CMOS I/O P2.0 - P2.7 8 bit General purpose CMOS I/O P3.0 General purpose CMOS I/O...

  • Page 7: Sfr Mapping

    SH79F1622 6. SFR Mapping The SH79F1622 provides 256 bytes of internal RAM to contain general-purpose data memory and Special Function Register (SFR). The SFR of the SH79F1622 fall into the following categories: CPU Core Registers: ACC, B, PSW, SP, DPL, DPH...
  • Page 8 SH79F1622 Table 6.1 CPU Core SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 /PIN Reset Value Accumulator 00000000 ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 B Register 00000000 AUXC C Register 00000000 Program Status Word...
  • Page 9 SH79F1622 Table 6.3 Flash control SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 /PIN Reset Value IB_OFF Low byte offset of flash memory IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF 00000000 for programming SET.7 SET.6 SET.5...
  • Page 10 SH79F1622 Table 6.5 CLKCON SFR POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 /PIN Reset Value CLKCON System Clock Control Register 111-00-- 32k_SPDUP CLKS1 CLKS0 OSC2ON Table 6.6 Interrupt SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4...
  • Page 11 SH79F1622 Table 6.7 Port SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 /PIN Reset Value 8-bit Port 0 00000000 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 8-bit Port 1 00000000 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2...
  • Page 12 SH79F1622 Table 6.8 Timer SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 /PIN Reset Value TCON Timer/Counter Control ----0000 ---- ---- ---- ---- ---- T2CON Timer/Counter 2 Control 00000000 EXF2 RCLK TCLK EXEN2 CP/R T2MOD Timer/Counter 2 Mode...
  • Page 13 SH79F1622 Table 6.9 EUART SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 /PIN Reset Value SCON Serial Control 00000000 SM0/FE SM1/RXOV SM2/TXCOL SBUF Serial Data Buffer 00000000 SBUF.7 SBUF.6 SBUF.5 SBUF.4 SBUF.3 SBUF.2 SBUF.1 SBUF.0 SADEN...
  • Page 14 SH79F1622 Table 6.11 TK SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 /PIN Reset Value TKGO/ TKCON1 Touch Key Control 0-000000 TKCON SHARE MODE OVDD FSW1 FSW0 ---- ---- ---- ---- TKF0 Touch Key interrupt flag Register...
  • Page 15 SH79F1622 Table 6.12 LED SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 /PIN Reset Value DISPCON LED Control -0----00 LEDON DUTY1 DUTY0 SEG01 SEG function selection Register 00000000 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0...
  • Page 16 SH79F1622 SFR Map Bank0 Non Bit addressable addressable TWICON IB_OFFSET IB_DATA AUXC IB_CON1 IB_CON2 IB_CON3 IB_CON4 IB_CON5 XPAGE EXF0 P0PCR P1PCR P2PCR P3PCR P1OS P0CR P1CR P2CR P3CR TWISTA TWIADR EXF1 P0SS P1SS P2SS TWIDAT TVCR2 TGCR11 TGCR12 TGCR21 TGCR22...

  • Page 17: Normal Function

    SH79F1622 7. Normal Function 7.1 CPU 7.1.1 CPU Core SFR Feature  CPU core registers: ACC, B, PSW, SP, DPL, DPH Accumulator ACC is the Accumulator register. Instruction system adopts A as mnemonic symbol of accumulator. B Register The B register is used during multiply and divide operations. For other instructions it can be treated as another scratch pad register.

  • Page 18: Enhanced Cpu Core Sfrs

     Enhanced CPU core registers: AUXC, DPL1, DPH1, INSCON The SH79F1622 has modified 'MUL' and 'DIV' instructions. These instructions support 16 bit operand. A new register - the register AUXC is applied to hold the upper part of the operand/result.

  • Page 19: Ram

    7.2 RAM 7.2.1 Features SH79F1622 provides both internal RAM and external RAM for random data storage. The internal data memory is mapped into four separated segments:  The Lower 128 bytes of RAM (addresses 00H to 7FH) are directly and indirectly addressable ...

  • Page 20: Flash Program Memory

    The SH79F1622 embeds 16K flash program memory for program code. The flash program memory supports In-Circuit Progra- mming (ICP) mode and Self-Sector Programming (SSP) mode. Every sector is 1024 bytes. The SH79F1622 also embeds 2048 bytes EEPROM-like memory block for storing user data. Every sector is 256 bytes.It has 8 sectors.
  • Page 21 SH79F1622 (2) Mass Erase The mass erase operation will erase all the contents of program code, code option, code protect bit and customer code ID, regardless the status of code-protect control mode. (The Flash Programmer supplies customer code ID setting function for customer to distinguish their product.)

  • Page 22: Flash Operation In Icp Mode

    SH79F1622 7.3.2 Flash Operation in ICP Mode ICP mode is performed without removing the micro-controller from the system. In ICP mode, the user system must be power-off, and the programmer can refresh the program memory through ICP programming interface. The ICP programming interface consists of 6 pins (V , GND, TCK, TDI, TMS, TDO).

  • Page 23: Ssp Function

    SH79F1622 7.4 SSP Function 7.4.1 SSP Register (1) Memory Page Register for Programming The register is used to select area code which will be erased or programmed, using IB_OFFSET register to show the address offset of bytes which is waiting for programming in the sector.
  • Page 24 SH79F1622 Table 7.6 Offset of Flash Memory for Programming Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF IB_OFFSET SET.7 SET.6 SET.5 SET.4 SET.3 SET.2 SET.1 SET.0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic...
  • Page 25 SH79F1622 Table 7.10 SSP Flow Control Register2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IB_CON3 IB_CON3.3 IB_CON3.2 IB_CON3.1 IB_CON3.0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description IB_CON3[3:0] Must be 0AH, otherwise Flash Programming will terminate Table 7.11 SSP Flow Control Register3...

  • Page 26: Flash Control Flow

    SH79F1622 7.4.2 Flash Control Flow Set IB_OFFSET Set XPAGE Set IB_DATA Set IB_CON1 IB_CON2[3:0]≠5H Set IB_CON2[3:0]=5H IB_CON2≠5H IB_CON3≠AH IB_CON2≠5H Set IB_CON3=AH ELSE IB_CON3≠AH Set IB_CON4=9H IB_CON4≠9H Reset IB_CON1-5 Set IB_CON5=6H Sector Erase IB_CON1=E6H &IB_CON2[3:0]=5H &IB_CON3=AH &IB_CON4=9H &IB_CON5=6H IB_CON1=6EH &IB_CON2[3:0]=5H &IB_CON3=AH &IB_CON4=9H...

  • Page 27: Ssp Programming Notice

    SH79F1622 7.4.3 SSP Programming Notice To successfully complete SSP programming, the user’s software must be set as the following the steps: (1) For Code/Data Programming: Note: must close Code-protect control mode 1 and Code-protect control mode 2. 1. Disable interrupt;...

  • Page 28: System Clock And Oscillator

     Built-in 32.768kHz speed up circuit  Built-in system clock prescaler 7.5.2 Clock Definition SH79F1622 have several internal clocks defined as below: (Refer to the diagram) 32KCRYCLK: the oscillator clock is from 32.768kHz crystal which is input from XTAL. f is defined as the 32KCRYCLK 32KCRY frequency.

  • Page 29: Description

    7.5.3 Description SH79F1622 provides 2 oscillator types: 32.768kHz crystal, 27MHz internal RC. The clock source of OSC1CLK and OSC2CLK can be selected from the two oscillator types by configuring OP_OSC in code option (refer to “Code Option” sector for details).

  • Page 30: Oscillator Type

    SH79F1622 7.5.5 Oscillator Type (1) OP_OSC = 000: internal RC, XTAL and XTALX share with I/O ports XTAL1 XTAL2 (2) OP_OSC = 011: 32.768kHz from XTAL, internal RC, XTALX share with I/O port XTAL1 32.768kHz XTAL2 7.5.6 Capacitor Selection for Oscillator...

  • Page 31: I/O Port

    PORT is used as input (x = 0-5, y = 0-7). For SH79F1622, some I/O pins can share with alternative functions. There exists a priority rule in CPU to avoid these functions conflicts when all the functions are enabled. (Refer to Port Share Section for details).
  • Page 32 SH79F1622 Table 7.17 Port Data Register 80H - C0H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P0 (80H) P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 P1 (90H) P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 P2 (A0H) P2.7 P2.6...

  • Page 33: Port Diagram

    SH79F1622 7.6.3 Port Diagram SFEN PxPCRy Output Mode Input Mode 0 = ON (Pull-up) PxCRy 1 = OFF I/O Pad Write Data Data Bus Register Read Port Data Register Read Read Data Register/Pad Selection 0: From Pad 1: From data register...
  • Page 34 SH79F1622 PORT1: - TXD: EUART data output (P1.7) - T3: Timer3 external input (P1.6) - T4: Timer4 external input (P1.0) - T2EX: Timer2 external input (P1.1) - INT41-INT42: External interrupt input (P1.5-P1.7) - RST: Reset pin (P1.6) - TK17-20: Touch Key channel (P1.1-P1.4) - COM1-7: LED COM1-7 output (P1.0-P1.6)
  • Page 35 SH79F1622 PORT2: - TK8-TK16: Touch Key channel 8-16 (P2.0-P2.7) - SEG8-15: SEG output - INT0, 1, 2: External interrupt 0, 1, 2 input Table 7.21 PORT2 Share Table Pin No. Priority Function Enable bit TK9-TK13 Set P2SS.0-P2SS.4 bit in P2SS register...

  • Page 36: Timer

    7.7 Timer 7.7.1 Features  The SH79F1622 has three timers (Timer2, 3, 4)  Timer2 is compatible with the standard 8052 and has up or down counting and programmable clock output function  Timer3 is a 16-bit auto-reload timer and can operate even in Power-Down mode ...
  • Page 37 SH79F1622 Mode1: 16 bit auto-reload Timer Timer2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit in T2MOD. After reset, the DCEN bit is set to 0 so that Timer2 will default to count up. When DCEN is set, Timer2 can count up or down, depending on the value of the T2EX pin.
  • Page 38 SH79F1622 Mode2: Programmable Clock Output ——— A 50% duty cycle clock can be programmed to come out on P0.5. To configure the Timer2 as a clock generator, bit C/ T2 must be cleared and bit T2OE must be set. Bit TR2 starts and stops the timer.
  • Page 39 SH79F1622 Registers Table 7.24 Timer2 Control Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ——— ———— T2CON EXF2 EXEN2 C/T2 CP/RL2 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Timer2 overflow flag bit 0: No overflow (must be cleared by software)
  • Page 40 SH79F1622 Table 7.25 Timer2 Mode Control Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 T2MOD TCLKP2 T2OE DCEN Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Timer 2 Clock Source Control bit TCLKP2 0: Select the clock source of system clock/12 as the Timer2 clock source...

  • Page 41: Timer3

    SH79F1622 7.7.3 Timer3 Timer3 is a 16-bit auto-reload timer. It is accessed as two cascaded Data Registers: TH3 and TL3. It is controlled by the T3CON register. The Timer3 interrupt can be enabled by setting ET3 bit in IEN1 register (Refer to Interrupt Section for details).
  • Page 42 SH79F1622 Registers Table 7.27 Timer3 Control Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 T3CON T3PS.1 T3PS.0 T3CLKS.1 T3CLKS.0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Timer3 overflow flag bit 0: No overflow (cleared by hardware) 1: Overflow (Set by hardware)

  • Page 43: Timer4

    SH79F1622 7.7.4 Timer4 Timer4 is a 16-bit auto-reload timer. It is accessed as two cascaded data registers: TH4 and TL4. It is controlled by the T4CON register. The Timer 4 interrupt can be enabled by setting ET4 bit in IEN1 register (Refer to interrupt Section for details).
  • Page 44 SH79F1622 Mode2: 16 bit Auto-Reload Timer with T4 Edge Trig Timer4 operates as 16-bit timer in Mode1. T4CLKS bit in T4CON.0 will be 0 always. Timer4 can select system clock as clock source.Other setting accords with mode 0. In Mode1, After Setting the TR4 bit (T4CON.1), Timer4 does not start counting but waits the trig signal (rising or falling edge controlled by T4M[1:0]) from T4.
  • Page 45 SH79F1622 Registers Table 7.29 Timer4 Control Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 T4CON T4PS1 T4PS0 T4M1 T4M0 T4CLKS Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Timer4 overflow flag bit 0: No overflow (cleared by hardware) 1: Overflow (Set by hardware)

  • Page 46: Interrupt

    7.8.1 Features  9 interrupt sources  4 interrupt priority levels The SH79F1622 provides total 9 interrupt sources: 4 external interrupts (INT0/1/2/4), 3 timer interrupts (Timer2, 3, 4), one EUART interrupt, TWI interrupt, TK interrupt. 7.8.2 Interrupt Enable Control Each interrupt source can be individually enabled or disabled by setting or clearing the corresponding bit in the interrupt enable registers IEN0 or IEN1.
  • Page 47 SH79F1622 Table 7.32 Secondary Interrupt Enable Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IEN1 ETWI Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Timer3 overflow interrupt enable bit 0: Disable timer3 overflow interrupt 1: Enable timer3 overflow interrupt...

  • Page 48: Interrupt Flag

    SH79F1622 7.8.4 Interrupt Flag Each Interrupt source has its own interrupt flag, when interrupt occurs, corresponding flag will be set by hardware, the interrupt flag bits are listed in Table bellow. For external interrupt (INT0/1/2/4) is generated, if the interrupt was edge trigged, the flag IEx (x = 0-2, 4) that generated this interrupt is cleared by hardware when the service routine is vectored.
  • Page 49 SH79F1622 Table 7.35 External Interrupt Flag Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EXF0 IT4.1 IT4.0 IT2.1 IT2.0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description External interrupt4 trigger mode selection bit 00: Low Level trigger 01: Trigger on falling edge...

  • Page 50: Interrupt Vector

    SH79F1622 7.8.5 Interrupt Vector When an interrupt occurs, the program counter is pushed onto the stack and the corresponding interrupt vector address is loaded into the program counter. The interrupt vector addresses are listed in Interrupt Summary table. 7.8.6 Interrupt Priority Each interrupt source can be individually programmed to one of four priority levels by setting or clearing corresponding bits in the interrupt priority control registers IPL0, IPH0, IPL1, and IPH1.

  • Page 51: Interrupt Handling

    SH79F1622 7.8.7 Interrupt Handling The interrupt flags are sampled and polled at the fetch cycle of each machine cycle. All interrupts are sampled at the rising edge of the clock. If one of the flags was set, the CPU will find it and the interrupt system will generate a LCALL to the appropriate service routine, provided this hardware-generated LCALL is not blocked by any of the following conditions: An interrupt of equal or higher priority is already in progress.

  • Page 52: External Interrupt Inputs

    External interrupt2, 4 have more interrupt trigger modes, the operation of External interrupt2, 4 is similar to external interrupt0, 1. When SH79F1622 is in IDLE mode or Power-Down mode, interrupt will cause the processor to wake up and resume operation, refer to “Power Management”...

  • Page 53: Interrupt Summary

    SH79F1622 Table 7.38 External interrupt Sampling time Control Register ADH-AEH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EXCON0 (ADH) I2P1 I2P0 I1P1 I1P0 I0P1 I0P0 EXCON1 (AEH) I43P1 I43P0 I42P1 I42P0 I41P1 I41P0 I40P1 I40P0 Reset Value (POR/WDT/LVR/PIN) Bit Number...

  • Page 54: Enhanced Function

    SH79F1622 8. Enhanced Function 8.1 Touch Key Function TKU1：TKU4 Key0 Key1 Key2 OPInput Key3 VREF[0:1] VTK[0:1] Key4 Key5 Key6 Touch Key Key7 Logic Circuit D15-D0 Data Output Key8 Key9 Key10 Key11 Key12 10nF - 47nF Key13 Key14 Key15 Key16 Key17...
  • Page 55 Functional Description SH79F1622 built-in Touch Key function module, which can connect at most 20 keys . SH79F1622 built-in simplified operating circuit in Touch Key function module, the application of it only need to use a external connected C capacitor. The value of C capacitor choose 22 nF - 44nF, must use polyester capacitor of 10% or more accuracy, X7R capacitor or NPO capacitor.
  • Page 56 SH79F1622 Operating Flow START TKCON = 1 CHOSE CHANNELS REGISTER： TKU1~TKU3 FUNCTION REGISTER: VREF[0:1] ,VTK[0:1] ,CMPD[0:1] ,VTK[0:1] ,RANDOM [0:1] ,TKST[0:7],FSW[0:1],TKRANDOM[0:7] 28Bit AMPLIFICATION FACTOR REGISTER: TKDIV01~TKDIV04 DELAY 10uS TKGO=1 WATING FOR THE TOUCH-KEY INTERRUPT PRODUCE OR SCANNING TKIF. TOUCH KEY INTERRUPT...

  • Page 57: Register

    SH79F1622 8.1.1 Register Table 8.1 Touch Key Functional Control Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TKGO TKCON1 TKCON SHARE MODE OVDD FSW1 FSW0 ---- ---- ---- ---- Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Touch Key Enable bit...
  • Page 58 SH79F1622 Table 8.3 Touch Key Frequency Random Setting Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TKRANDOM TKRADON TKOFFSET TKVDD TKOUT RANDOM1 RANDOM0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Touch Key Random Frequency Enable bit TKRADON 0: Disable Touch Key random frequency function...
  • Page 59 SH79F1622 Table 8.4 Touch Key Interrupt Flag Register (The register only can be cleared) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TKF0 IFERR IFGO IFAVE IFCOUNT IFTKOV Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Calculated Result Overflow Interrupt Flag bit IFERR 0: Calculated result high-bit don’t overflow...
  • Page 60 SH79F1622 Table 8.6 Port Function Control Register D9H - DBH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P0SS(D9H) P0SS.7 P0SS.6 P0SS.5 P0SS.4 P0SS.3 P0SS.2 P0SS.1 P0SS.0 P1SS(DAH) P1SS.4 P1SS.3 P1SS.2 P1SS.1 P2SS(DBH) P2SS.7 P2SS.6 P2SS.5 P2SS.4 P2SS.3 P2SS.2 P2SS.1 P2SS.0...
  • Page 61 SH79F1622 Table 8.8 Key Scan Error Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TW.4 TW.3 TW.2 TW.1 TW.0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Key Scan Error Display: When TKW[4-0] = 00000b, Key 1 When TKW[4-0] = 00001b, Key 2...
  • Page 62 SH79F1622 C:1.525ms COM1 T:8ms L:7.625ms COM2 ALL:15.625ms COM3 SEG1 SEG2 TK & LED (SHARE) 01 C:1.525ms COM1 T:4ms L:11.625ms COM2 ALL:15.625ms COM3 SEG1 SEG2 TK & LED (SHARE) 02 SEG output Touch Key waveform in diagram: ALL width = LED frame frequency width, T width is setting width of Touch Key, L width is width of LED scan, C width is width of LED COM.
  • Page 63 SH79F1622 Table 8.9 Reference Voltage Selection Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TKVREF VREF1 VREF0 CMPD1 CMPD0 VTK1 VTK0 TUNE1 TUNE0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Internal Reference Voltage Selection bit 00: V = 2.5V...
  • Page 64 SH79F1622 Table 8.10 Key Scan Sequence Register A4H - A6H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TKU1 (A4H) TKU2 (A5H) TK16 TK15 TK14 TK13 TK12 TK11 TK10 TKU3 (A6H) TK20 TK19 TK18 TK17 Reset Value (POR/WDT/LVR/PIN) Note: When share bit is set, TK17 - 20 wil be used as COM output, key scan is invalid. When some bit of TKU1 - TKU3 is cleared, starting key scan will skip the channel of this key.
  • Page 65 SH79F1622 (continue) 51AH TK014L 51BH TK014H 51CH TK015L 51DH TK015H 51EH TK016L 51FH TK016H 520H TK017L 521H TK017H 522H TK018L 523H TK018H 524H TK019L 525H TK019H 526H TK020L 527H TK020H Note: (1) OP output voltage is supply voltage of Touch Key, Vref is reference voltage source of Touch Key.

  • Page 66: Led Driver

    SH79F1622 8.2 LED Driver LED dirver contains a controller, 7 COM output pins and 16 SEG output pins, supporting 1/4 - 1/7 duty voltage drive mode. When DISPSEL bit is set, LED function is enable. Controller consists of display data RAM storage area and a duty generator.
  • Page 67 SH79F1622 Note: LED clock frequency = system clock frequency/8/DISPCLK: system clock frequency is 27M. One COM scan width = LED clock frequency/DISCOM The current LED scan is (5) COM scan mode. LED ALL: 64HZ = 1/64 = 15.625 C:15.625/(5) = 3.125ms = 1/0.003125 = 320Hz...
  • Page 68 SH79F1622 Table 8.15 SEG Mode Selection Register 8AH-8BH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SEG01 (8AH) SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 SEG02 (8BH) SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 Reset Value (POR/WDT/LVR/PIN) Bit Number...

  • Page 69: Configuration Of Led Ram

    SH79F1622 8.2.2 Configuration of LED RAM Table 8.18 LED 1/5 Duty (LED_C1-C7, LED_S1-16) Address 530H COM1L SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 531H COM1H SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 532H COM2L SEG8 SEG7 SEG6 SEG5...
  • Page 70 SH79F1622 COM1 COM2 COM3 COM4 COM5 COM waveform, under the condition of LED and Touch Key in SHARE mode, CC[3:1] = 111, brightness is 100% COM1 COM2 COM3 COM4 COM5 COM waveform, under the condition of LED and Touch Key in SHARE mode, CC[3:1] = 010, brightness is 50%...

  • Page 71: Touch Key Function And Led Share Function

    SH79F1622 8.3 Touch Key Function and LED SHARE Function START SETUP LED FREQUENCY AND LIGHTENESS AND DISPLAY PROPERTIES TKCON = 1 SHARE=1 LEDON=1 CHOSE CHANNELS REGISTER ： TKU1~TKU3 FUNCTION REGISTER: VREF[0:1] ,VTK[0:1] ,CMPD[0:1] ,VTK[0:1] ,RANDOM[0:1] ,TKST[0:7],FSW[0:1],TKRANDOM[0:7] 28Bit AMPLIFICATION FACTOR REGISTER:...

  • Page 72: Function Description

    8.3.1 Function Description SH79F1622 built-in Touch Key function module, which can connect at most 20 keys. When enable LED SHARE function, Touch Key function can connect at most 16 keys. COM1-COM7 is used as LED COM. It is need to notice that, if SHARE function is enable, LED scan function will enable after Touch Key function fininsh data storage.When scanning COM1-COM7 is...

  • Page 73: Euart

    This mode provides synchronous communication with external devices. In this mode serial data is transmitted and received on the RxD line. TxD is used to output the shift clock. The TxD clock is provided by the SH79F1622 whether the device is transmitting or receiving.
  • Page 74 SH79F1622 Any instruction that uses SBUF as a destination register (“write to SBUF” signal) will start the transmission. The next system clock tells the Tx control block to commence a transmission. The data shift occurs at the falling edge of the SHIFT CLOCK, and the contents of the transmit shift register is shifted one position to the right.
  • Page 75 SH79F1622 Transmission begins with a “write to SBUF” signal, and it actually commences at the next system clock following the next rollover in the divide-by-16 counter (divide baud-rate by 16), thus, the bit times are synchronized to the divide-by-16 counter, not to the “write to SUBF”...
  • Page 76 SH79F1622 Mode2: 9-Bit EUART, Fixed Baud Rate, Asynchronous Full-Duplex This mode provides the 11 bits full duplex asynchronous communication. The 11 bit consists of one start bit (logical 0), 8 data bits (LSB first), a programmable 9 data bit, and a stop bit (logical 1). Mode 2 supports multiprocessor communications and hardware address recognition (Refer to Multiprocessor Communication Section for details).
  • Page 77 SH79F1622 Reception is enabled only if REN is high. The serial port actually starts the receiving of serial data, with the detection of a falling edge on the RxD pin. For this purpose RxD is sampled at the rate of 16 times baud rate. When a falling edge is detected, the divide-by-16 counter is immediately reset.

  • Page 78: Baud Rate Generate

    SH79F1622 8.4.3 Baud Rate Generate The baud rate generator is an 15 bit up-counting timer. Overflow 15-bit timer To EUART Fsys From 7FFFH to 0000H SBRTEN=1 SBRTH[14:8],SBRTL7:0] Baudrate Generator for EUART Fsys SBRT = ， SBRToverfl owrate [SBRTH, SBRTL] −...

  • Page 79: Error Detection

    SH79F1622 Automatic (Hardware) Address Recognition In Mode2 & 3, setting the SM2 bit will configure EUART act as following: when a stop bit is received, EUART will generate an interrupt only if the 9 bit that goes into RB8 is logic 1 (address byte) and the received data byte matches the EUART slave address.

  • Page 80: Register

    SH79F1622 8.4.6 Register Table 8.19 Power Control Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PCON SMOD SSTAT Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Baud rate doubler SMOD 0: If set in Mode2, the baud-rate of EUART is system clock/64...
  • Page 81 SH79F1622 (continue) Bit Number Bit Mnemonic Description EUART Transmit Collision flag, when TXCOL bit is read, SSTAT bit must be set 1 TXCOL 0: No Transmit Collision, clear by software 1: Transmit Collision occurs, set by hardware EUART Receiver enable bit...
  • Page 82 SH79F1622 Table 8.23 EUART Baudrate generator Register 9CH-9DH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SBRTH (9CH) SBRTEN SBRT.14 SBRT.13 SBRT.12 SBRT.11 SBRT.10 SBRT.9 SBRT.8 SBRTL (9DH) SBRT.7 SBRT.6 SBRT.5 SBRT.4 SBRT.3 SBRT.2 SBRT.1 SBRT.0 Reset Value (POR/WDT/LVR/PIN) Bit Number...

  • Page 83: Twi

     Wake-up system when SH79F1622 is in IDLE Mode  Programable address TWI serial bus adopt two wires (SDA and SCL) to transmit messages between bus and device. SH79F1622 is totally in conformity with TWI bus standard, transmitting and processing bytes automatically, and tracking serial communication.
  • Page 84 Repeated START STOP When generating ACK signal, SH79F1622 will pull the SDA line low. During setting interrupt flag bit, SH79F1622 pull the SCL line low, releasing the SDA line. Clearing TWINT flag after interrupt process is finished, releasing the SCL line.

  • Page 85: Function Description

    SH79F1622 Data Arbitration A master may start a transfer only if the bus is free. Two or more devices may generate a START condition within the minimum hold time (t ), resulting in a defined START condition on the bus.
  • Page 86 (8 + 1 bit). When SH79F1622 is in slave transfer mode and the first byte of transferred message is low, the function can be used. STA and RSTA is not situable for this function. If SH79F1622 generates interrupt, TFREE bit in TWICON regiser will be set (if control bit EFREE bit has been set).

  • Page 87: Transmission Mode

    SH79F1622 8.5.4 Transmission Mode TWI is a byte-oriented and interrupt based communication bus. Interrupts will be generated by all bus events, like reception of a byte or transmission of a START condition. So the application software can do other oparations during a byte transfer. Note that TWI enable (ENTWI) bit in TWICON, all interrupts enable (EA) bit in IEN0 and ETWI bit will decide together whether generating an interrupt when TWINT bit is set.
  • Page 88 SH79F1622 Status Code for Master Transmitter Mode Application Software Response Status Status of TWI bus and Next Action Taken by Hardware Control Bit Operation To/From Code Hardware Interface TWIDAT STA STO TWINT A START Condition has Load SLA + W...
  • Page 89 Arbitration lost in slave address Ack or Nack Ack or Nack or data byte Other Master Other Master Continue Continue Arbitration lost and addressed as slave To Corresponding state in slave mode 68H/78H/B0H Other Device Actions SH79F1622 Actions...
  • Page 90 SH79F1622 Master Receiver Mode In the Master Receiver mode, a number of data bytes are received from a slave. In order to enter a Master mode, a STARTcondition must be transmitted, a following SLA + R address packet determines MR has entered.
  • Page 91 TWICON register and TWIADR register must be initialized: set ENTWI bit and AA bit in TWICON register, clearing STA, STO and TWINT; The high 7-bit in TWIADR register is used to prepare the corresponding address for SH79F1622. If GC is set, SH79F1622 will respond the general address (00H);...
  • Page 92 SH79F1622 Status Code for Slave Transmitter Mode Application Software Response Status Status of TWI bus and Next Action Taken by Hardware Control Bit Operation To/From Code Hardware Interface TWIDAT STA STO TWINT Transmit the last data byte and ACK will be...
  • Page 93 TWICON register and TWIADR register must be initialized: set ENTWI bit and STA bit in TWICON register, clearing STO and TWINT; The high 7-bit in TWIADR register is used to prepare the corresponding address for SH79F1622. If GC is set, SH79F1622 will respond the general address (00H);...
  • Page 94 SH79F1622 (continue) Arbitration lost in SLA + Receive data byte; Transmit NACK R/W as master; General No TWIDAT address has been action received; Receive data byte; Transmit ACK ACK has been received Previously addressed Receive data byte; Transmit NACK with own SLA address;...
  • Page 95 TWI bus signals. When a bus error occurs, TWINT will be set. To recover from a bus error, the STO flag must be set and TWINT must be cleared. This will cause SH79F1622 to enter the not addressed slave mode and to clear the STO flag. SDA and SCL lines will be released, and no STOP condition is transmitted.

  • Page 96: Register

    SH79F1622 8.5.5 Register Table 8.25 TWI Control Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TWICON TOUT ENTWI TWINT TFREE EFREE Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Bus line timeout flag 0: No timeout occurred TOUT 1: Set by hardware when TWI bus low level exceeds the timeout period (25ms).
  • Page 97 10: f /6/64 11: f /6/42 When SH79F1622 is in Master mode, the hold time of STA, STO and repeated STA is related to the transfer frequency which is selected by CR[1:0] Timeout Enable Bit ETOT 0: Disable Timeout detection 1: Enable Timeout detection Table 8.27 TWI Address Register...
  • Page 98 SH79F1622 Table 8.29 System Clock Control Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CLKCON 32k_SPDUP CLKS1 CLKS0 OSC2ON Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description 32.768kHz oscillator speed up mode control bit 0: 32.768kHz oscillator normal mode, cleared by software.

  • Page 99: Low Voltage Reset (Lvr)

    SH79F1622 8.6 Low Voltage Reset (LVR) 8.6.1 Features  Enabled by the code option and V is 4.1V or 2.8V  LVR de-bounce timer T is about 30-60µs  When the power supply voltage is lower than the set voltage V...

  • Page 100: Watchdog Timer (Wdt) And Reset State

    OVL Reset To enhance the anti-noise ability, SH79F1622 built in Program Counter (PC) over range detect circuit, if program counter value is larger than flash romsize, or detect operation code equal to A5H which is not exist in 8051 instruction set, a OVL reset will be generate to reset CPU, and set WDOF bit.

  • Page 101: Register

    SH79F1622 8.7.2 Register Table 8.30 Reset Control Register B1H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RSTSTAT WDOF PORF LVRF CLRF WDT.2 WDT.1 WDT.0 Reset Value (POR) Reset Value (WDT) Reset Value (LVR) Reset Value (PIN) Bit Number...

  • Page 102: Tone

    SH79F1622 8.8 Tone SH79F1622 has two 16-bit Tone generator, which can generate square ware with specific frequency. Table 8.31 Tone Generator Control Register (TGCR11, 12: 21, 22) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TGCR11 TG1.7 TG1.6 TG1.5 TG1.4 TG1.3...
  • Page 103 SH79F1622 Volume control register use 7-bit register control the output level of tone generator. TGxEN (X = 1, 2): Tone generator x enable. 0: Disable Tone generator x (default) 1: Enable Tone generator x Program Note: When Tone generator is operating, POWER-DOWN or IDEA instruction can’t be performed for avoiding electric leakage.
  • Page 104 SH79F1622 Music Table 1 Table 8.33 When OSC = 27MHz, music range reference table of Tone generator channel 1 TGCR Error TGCR Error Ideal Actual Ideal Actual Note Note Frequency (TGx.13 - TGx.0) Frequency Rate% Frequency (TGx.13 - TGx.0) Frequency Rate% 77.78...

  • Page 105: Power Management

    (2) Reset signal (logic low on the RESET pin, WDT RESET if enabled, LVR REST if enabled), this will restore the clock to the CPU, the SUSLO register and the IDL bit in PCON register will be cleared by hardware, finally the SH79F1622 will be reset.

  • Page 106: Register

    SH79F1622 8.9.4 Register Table 8.34 Power Control Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PCON SMOD SSTAT Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description SMOD Baud rate double bit SSTAT SCON[7:5] function selection bit GF[1:0] General purpose flags for software use...

  • Page 107: Warm-Up Timer

     Built-in oscillator warm-up counter to eliminate unstable state when oscillation startup SH79F1622 has a built-in power warm-up counter; it is designed to eliminate unstable state after power on or to do some internal initial operation such as read customer option etc.

  • Page 108: Code Option

    SH79F1622 8.11 Code Option OP_WDT: 0: Enable WDT (Default) 1: Disable WDT OP_WDTPD: 0: WDT can’t work in STOP MODE (Default) 1: WDT can work in STOP MODE OP_LVREN: 0: Disable LVR function (Default) 1: Enable LVR function OP_LVRLE: 0: 4.1V LVR level 1 (Default) 1: 2.8V LVR level 2...

  • Page 109: Instruction Set

    SH79F1622 9. Instruction Set ARITHMETIC OPERATIONS Opcode Description Code Byte Cycle ADD A, Rn Add register to accumulator 0x28-0x2F ADD A, direct Add direct byte to accumulator 0x25 ADD A, @Ri Add indirect RAM to accumulator 0x26-0x27 ADD A, #data...
  • Page 110 SH79F1622 LOGIC OPERATIONS Opcode Description Code Byte Cycle ANL A, Rn AND register to accumulator 0x58-0x5F ANL A, direct AND direct byte to accumulator 0x55 ANL A, @Ri AND indirect RAM to accumulator 0x56-0x57 ANL A, #data AND immediate data to accumulator...
  • Page 111 SH79F1622 DATA TRANSFERS Opcode Description Code Byte Cycle MOV A, Rn Move register to accumulator 0xE8-0xEF MOV A, direct Move direct byte to accumulator 0xE5 MOV A, @Ri Move indirect RAM to accumulator 0xE6-0xE7 MOV A, #data Move immediate data to accumulator...
  • Page 112 SH79F1622 PROGRAM BRANCHES Opcode Description Code Byte Cycle ACALL addr11 Absolute subroutine call 0x11-0xF1 LCALL addr16 Long subroutine call 0x12 Return from subroutine 0x22 RETI Return from interrupt 0x32 AJMP addr11 Absolute jump 0x01-0xE1 LJMP addr16 Long jump 0x02 SJMP rel...
  • Page 113 SH79F1622 BOOLEAN MANIPULATION Opcode Description Code Byte Cycle CLR C Clear carry flag 0xC3 CLR bit Clear direct bit 0xC2 SETB C Set carry flag 0xD3 SETB bit Set direct bit 0xD2 CPL C Complement carry flag 0xB3 CPL bit...

  • Page 114: Electrical Characteristics

    SH79F1622 10. Electrical Characteristics Absolute Maximum Ratings* *Comments DC Supply Voltage....-0.3V to +6.0V Stresses exceed those listed under “Absolute Maximum Ratings” may cause permanent damage to this device.
  • Page 115 SH79F1622 (continue) I/O Ports, I = 40mA, V = 5.0V (OP_SEG = 0) Output High Voltage1 - 3V P0.0-P0.7, P2.0-P2.7, output ability normal mode I/O Ports, I = 14mA, V = 5.0V (OP_SEG = 1) Output High Voltage2 - 3V P0.0-P0.7, P2.0-P2.7, output ability 1/3 normal mode...
  • Page 116 SH79F1622 Low Voltage Reset Electrical Characteristics (V = 2.7V - 5.5V, GND = 0V, T = +25°C, unless otherwise specified) Parameter Symbol Min. Typ. Max. Unit Condition LVR enabled LVR Voltage 1 LVR1 = 2.8V - 5.5V LVR enabled LVR Voltage 2 LVR2 = 2.0V - 5.5V...

  • Page 117: Application (Led Share Circuit, Only For Reference)

    SH79F1622 11. Application (LED SHARE circuit, only for reference) TK1：SEG0 LED01 TK2：SEG1 100u LED02 TK3：SEG2 LED03 TK4：SEG3 LED04 TK5：SEG4 LED05 TK6：SEG5 LED06 TK7：SEG6 LED07 TK8：SEG7 LED08 SH79F1622 TK9：SEG8 LED09 TK10：SEG9 LED10 TK11：SEG10 LED11 COM5 TK12：SEG11 LED12 COM4 TK13：SEG12 LED13 COM3 TK14：SEG13...

  • Page 118: Ordering Information

    SH79F1622 12. Ordering Information Part No. Package SH79F1622M/028MU SOP28 SH79F1622M/020MU SOP20 SH79F1622L/016LU SOP16...

  • Page 119: Package Information

    SH79F1622 13. Package Information SOP 16L (150mil) Outline Dimensions unit: inches/mm θ Detail F See Detail F Seating Plane Dimensions in inches Dimensions in mm Symbol 0.053 0.071 1.35 0.004 0.010 0.25 0.049 0.061 1.25 1.55 0.013 0.020 0.33 0.51 0.008...
  • Page 120 SH79F1622 SOP 20L Outline Dimensions unit: inches/mm θ Detail F See Detail F Seating Plane Dimensions in inches Dimensions in mm Symbol 0.093 0.104 2.35 2.65 0.004 0.012 0.10 0.30 0.083 0.098 2.10 2.50 0.013 0.020 0.33 0.51 0.008 0.013 0.20...
  • Page 121 SH79F1622 SOP28L Outline Dimensions unit: inches/mm Detail F See Detail F Seating Plane Dimensions in inches Dimensions in mm Symbol 0.085 0.104 2.15 2.65 0.004 0.012 0.10 0.30 0.081 0.098 2.05 2.50 0.013 0.02 0.33 0.51 0.008 0.014 0.20 0.36 0.697...

  • Page 122: Product Spec. Change Notice

    SH79F1622 14. Product SPEC. Change Notice Version Content Date Original Sep. 2015...

  • Page 123: Table Of Contents

    SH79F1622 Content FEATURES ..................................1 GENERAL DESCRIPTION .............................. 1 BLOCK DIAGRAM ................................2 PIN CONFIGURATION ..............................3 PIN DESCRIPTION ................................. 6 SFR MAPPING ................................7 NORMAL FUNCTION ..............................17 7.1 CPU ........................................17 7.1.1 CPU Core SFR .................................... 17 7.1.2 Enhanced CPU core SFRs ................................18 7.1.3 Register ......................................
  • Page 124 SH79F1622 8.4.3 Baud Rate Generate ..................................78 8.4.4 Multi-Processor Communication ..............................78 8.4.5 Error Detection .................................... 79 8.4.6 Register ......................................80 8.5 TWI ........................................83 8.5.1 Features ....................................... 83 8.5.2 Data Transformat ..................................83 8.5.3 Function Description ................................... 85 8.5.4 Transmission Mode ..................................87 8.5.5 Register ......................................

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