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Sino Wealth SH79F7416 Manual

Enhanced microcontroller with 4 channels uart and 3 channels pwm

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1. Features
8bits micro-controller with Pipe-line structured 8051
compatible instruction set
Flash ROM: 64K Bytes
RAM: internal 256 Bytes, external 4096 Bytes,LCD ram
40 Bytes
EEPROM-Like:bulid-in 4096 Bytes(code option)
Operation Voltage:
f
= 32.768kHz - 24MHz, V
OSC
Oscillator (code option)
- Crystal oscillator: 32.768kHz
- Crystal oscillator:2MHZ-16MHz
- Ceramic oscillator:2MHZ-16MHz
- Internal RC oscillator: 24MHz(±1%)/128K
61 CMOS bi-directional I/O pins
Built-in pull-up resistor for input pin
Three 16-bit timer/counters T3 ,T4,T5
8 large current driver I/O(code option optional enhanced
or standardized or weakened)
Four 16-bit PCA0, PCA1,PCA2 and PCA3 each contain
two comparison/capture units
3channels 12-bits PWM timer
Interrupt sources:
-Timer 3/4/5
-INT0/1/2
- INT3: 8 input
- INT4: 8 input
-,CRC,ADC, LPD,SCM
- SPI, TWI, CRC, EUART0/1/2/3
- PEM0/1/2, PCA0/1/2/3
SPI (Master/slave Mode)
TWI (Master/slave Mode)
2. General Description
The SH79F7416 is a high performance 8051 compatible micro-controller.The SH79F7416 can perform more fast
operation speed and higher calculation performance, if compare SH79F7416 with standard 8051 at same clock speed.
The SH79F7416 retains most features of the standard 8051. These features include internal 256 bytes RAM, INT0-INT4.
In addition,SH79F7416 provides external4096 bytes RAM.It also contains 64Kbytes Flash memory block for program storage.
The SH79F7416 not only include many standard communication modules, such as EUART/TWI/SPI and so on, but also
include LCD diver, ADC,PCA, PWM timer, ect.
In addition, the SH79F7416 also have CRC module, built in it.
Enhanced 8051 Microcontroller with 4 channels UART and 3 channels PWM
=2.0V -5.5V
DD
4 Enhanced UART (CMOS/TTL) (own baudrate
generator)
LCD driver
- 8 X 40dots (1/8 duty 1/4 bias)
- 6 X 40dots (1/6 duty 1/4 bias or 1/3 bias)
- 5 X 40dots (1/5 duty 1/3 bias)
- 4 X 40dots (1/4 duty 1/3 bias)
16 analog inputs 12-bit Analog Digital Converter
Internal Logic Configuration Module(LCM)
Low Power Detect (LPD) Module with 16 level
optional
Built-in CRC verification module, the verify size
can be selected
Support single line simulation and download
Built-in low voltage Reset (LVR) function (code
option)
- LVR voltage1: 4.1v
- LVR voltage2: 3.7v
- LVR voltage3: 2.8v
- LVR voltage3: 2.1v
CPU Machine period:
- 1 oscillator clock
Built-in Watch Dog Timer (WDT)
Built-in oscillator Warm-up timer
Support Low power operation modes:
- Idle Mode
- Power-Down Mode
Flash Type
Package:
- LQFP64 7*7
1
SH79F7416
V1.0

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Summary of Contents for Sino Wealth SH79F7416

  • Page 1 SH79F7416 with standard 8051 at same clock speed. The SH79F7416 retains most features of the standard 8051. These features include internal 256 bytes RAM, INT0-INT4. In addition,SH79F7416 provides external4096 bytes RAM.It also contains 64Kbytes Flash memory block for program storage.
  • Page 2 SH79F7416 3. Block Diagram Reset circuit Power Pipelined 8051 architecture Watch Dog 64K Bytes Flash ROM Port 7 Configuration I/Os P7.0 - P7.4 Internal 256 Bytes Port 6 External 4096Bytes Configuration I/Os (Exclude System P6.0 - P6.7 Register) Port 5 Configuration I/Os P5.0 - P5.7...
  • Page 3 SH79F7416 4. Pin Configration 4.1 LQFP64ackage 38 37 36 35 34 33 P7.4/INT32/SEG23/T3/P3CEX1AN1 XTAL2/AN5/INT42/P2.0 SEG7/P2.1 P7.3/INT33/SEG24/P3CEX0/AN0 SEG6/P2.2 SEG5/P2.3 SEG4/P2.4 P7.0/SEG27/P1CEX0/TDI SEG3/P2.5 P6.7/SEG28/ECI1/TCK SEG2/P2.6 P6.6/SEG29 SEG1/P2.7 P6.5/INT34/SEG30 SH79F7416 P6.4/INT35/SEG31 RESET P6.3/SEG32/T4 P6.2/INT47/SEG33 P3.0 P6.1/SEG34/ECI2 P3.1 P6.0/SEG35/P2CEX1/AN14 P3.2 P5.7/SEG36/P2CEX0/AN13 P5.6/INT36/SEG37/AN12 INT46/P3.3 AVREF/INT44/P3.4 P5.5/INT37/SEG38/AN11...
  • Page 4 SH79F7416 LCM (logical function configuration module) pin allocation table Function UART0 UART1 UART2 PWM0 PWM1 INT2 PCA0 RXD0 TXD0 RXD1 TXD1 RXD2 TXD2 PWM0 PWM1 INT2 P0CEX0 P0CEX1 ECI0 P0.0 P0.1 P0.2 P0.3  ● ● ● ● P0.4 ●...
  • Page 5 SH79F7416 (continue) Function UART0 UART1 UART2 PWM0 PWM1 INT2 PCA0 RXD0 TXD0 RXD1 TXD1 RXD2 TXD2 PWM0 PWM1 INT2 P0CEX0 P0CEX1 ECI0 ● P5.0 P5.1 P5.2 P5.3 P5.4 ● ● ● ● ● ● P5.5 ● ● ● ● ●...
  • Page 6 SH79F7416 引脚功能 Pin No. Default Type (LQFP64) AN6/INT40/P3.5 P3.5 AN7/P3.6 P3.6 AN8/P3.7 P3.7 AN9/INT45/P4.0 P4.0 COM8/P4.1 P4.1 COM7/P4.2 P4.2 COM6/P4.3 P4.3 COM5/P4.4 P4.4 COM4/P4.5 P4.5 COM3/P4.6 P4.6 COM2/P4.7 P4.7 COM1/P5.0 P5.0 VIN/AN10/INT40/P5.1 P5.1 SWE/INT1/P5.2 P5.2 TXD3/SEG40/P5.3 P5.3 RXD3/INT43/SEG39/P5.4 P5.4 AN11/SEG38/INT37/P5.5 P5.5...
  • Page 7 SH79F7416 续上表 Pin No. Default Type (LQFP64) AN3/SEG18/INT31/P0.4 P0.4 PWM2/SEG17/INT30/P0.5 P0.5 SEG16/P0.6 P0.6 SEG15/P0.7 P0.7 SEG14/P1.0 P1.0 SEG13/P1.1 P1.1 SEG12/P1.2 P1.2 SEG11/P1.3 P1.3 SEG10/P1.4 P1.4 SEG9/P1.5 P1.5 SEG8/P1.6 P1.6 P1.7 port or oscillator input pin (code option XTAL1/AN4/INT41/P1.7 control) P2.0 mouth or the oscillator output pin (code XTAL2/AN5/INT42/P2.0...
  • Page 8 SH79F7416 Pin Function and Pin Description 5.1 Pin Function Pin No. Type Description I/O PORT P0.0 - P0.7 8-bit bi-directional I/O port P1.0 - P1.7 8-bit bi-directional I/O port P2.0 - P2.7 8-bit bi-directional I/O port P3.0 - P3.7 8-bit bi-directional I/O port P4.0 - P4.7...
  • Page 9 SH79F7416 (continue) Interrupt & Reset & Clock & Power INT0 – INT2 External interrupt 0-2 input source INT30 – INT37 External interrupt 30-37 input source INT40 - INT47 External interrupt 40-47 input source The device will be reset by A low voltage on this pin longer than 10us, an internal resistor ————...
  • Page 10 SH79F7416 6. SFR Mapping The SFR of the SH79F7416 fall into the following categories: CPU Core Registers: ACC,B,PSW,SP,DPL,DPH Enhanced CPU Core Registers: AUXC,DPL1,DPH1,INSCON,XPAGE Power and Clock Control Registers: PCON,SUSLO Flash Registers: IB_OFFSET,IB_DATA,IB_CON1,IB_CON2,IB_CON3,IB_CON4,IB_CON5,FLASHCON Data Memory Register: XPAGE Hardware Watchdog Timer Registers:...
  • Page 11 SH79F7416 Table 6.1 C51 Core SFRs POR/WDT/LVR Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 symbol Address Name /PIN Reset Value Accumulator 00000000 ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 B Register 00000000 AUXC C Register 00000000 Program Status Word...
  • Page 12 SH79F7416 Table 6.3 Flash control SFRs POR/WDT/LVR Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 symbol Address Name /PIN Reset Value IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF Offset Register for Programming 00000000 Bank0 SET.7 SET.6 SET.5 SET.4 SET.3...
  • Page 13 SH79F7416 Table 6.6 Interrupt SFRs POR/WDT/LVR symbol Address Name /PIN Reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Value IEN0 Interrupt Enable Control 0 00000000 EADC EPCA1 EPCA0 Bank0 IEN1 Interrupt Enable Control 1 00000000 ESPI EPCA0 ETWI Bank0...
  • Page 14 SH79F7416 Table 6.7 TWI SFRs POR/WDT/LVR symbol Address Name /PIN Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TWICON TWI Control register 00000000 TOUT ENTWI TWINT TFREE EFREE Bank0 TWISTA TWII status register 11111000 TWISTA.7 TWISTA.6 TWISTA.5 TWISTA.4 TWISTA.3...
  • Page 15 SH79F7416 P2CR Port2 input/output direction control 00000000 P2CR.7 P2CR.6 P2CR.5 P2CR.4 P2CR.3 P2CR.2 P2CR.1 P2CR.0 Bank0 (continue) P2CR Port2 input/output direction control 00000000 P2CR.7 P2CR.6 P2CR.5 P2CR.4 P2CR.3 P2CR.2 P2CR.1 P2CR.0 Bank0 P3CR Port3 input/output direction control 00000000 P3CR.7 P3CR.6 P3CR.5...
  • Page 16 SH79F7416 Table 6.9 Timer SFRs POR/WDT/LVR Mnem Name /PIN Reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Value T3CON Timer/Counter3 Control 0-00-000 T3PS.1 T3PS.0 T3CLKS.1 T3CLKS.0 Bank1 Timer/Counter3 Low Byte 00000000 TL3.7 TL3.6 TL3.5 TL3.4 TL3.3 TL3.2 TL3.1 TL3.0...
  • Page 17 SH79F7416 P2CMD PCA2 Mode register 00---000 ECF2 P2SDEN P2CPS2 P2CPS1 P2CPS0 Bank2...
  • Page 18 SH79F7416 (continue) P3CMD PCA3 Mode register 00---000 ECF3 P3SDEN P3CPS2 P3CPS1 P3CPS0 Bank2 PCA0 Capture /Compare Module 0 P0CPM0 00000000 P0SMP0 P0SMN0 P0FSP0 P0FSN0 P0ECOM0 P0TCP0 P0MAT0 P0ECCF0 Bank2 register PCA0 Capture /Compare Module1 P0CPM1 00000000 P0SMP1 P0SMN1 P0FSP1 P0FSN1...
  • Page 19 SH79F7416 (continue) PCA0 capture/compare module 1 P0CPL1 00000000 P0CPL1.7 P0CPL1.6 P0CPL1.5 P0CPL1.4 P0CPL1.3 P0CPL1.2 P0CPL1.1 P0CPL1.0 Bank2 low byte PCA0 capture/compare module 1 P0CPH1 00000000 P0CPH1.7 P0CPH1.6 P0CPH1.5 P0CPH1.4 P0CPH1.3 P0CPH1.2 P0CPH1.1 P0CPH1.0 Bank2 high byte PCA1 capture/compare module 0...
  • Page 20 SH79F7416...
  • Page 21 SH79F7416 Table 6.11 EUART SFRs POR/WDT/LVR symbol Addres Name /PIN Reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Value PCON Power & serial Control 00--0000 SMOD SSTAT Bank0 SCON EUART0 serial control 00000000 SM0/FE SM1/RXOV SM2/TXCOL Bank0 SBUF EUART0 serial data buffer 00000000 SBUF.7...
  • Page 22 SH79F7416 SADEN2 EUART2 slave address mask 00000000 SADEN2.7 SADEN2.6 SADEN2.5 SADEN2.4 SADEN2.3 SADEN2.2 SADEN2.1 SADEN2.0 Bank1 SADDR2 EUART2 slave address 00000000 SADDR2.7 SADDR2.6 SADDR2.5 SADDR2.4 SADDR2.3 SADDR2.2 SADDR2.1 SADDR2.0 Bank1 SBRTH2 EUART2 baud rate generator high 00000000 SBRTEN2 SBRT2.14 SBRT2.13 SBRT2.12...
  • Page 23 SH79F7416 Table 6.13 ADC SFRs POR/WDT/LVR Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 symbol Address /PIN Reset Value —---—-----— ADCON1 ADC Control1 00000000 ADON ADCIF REFC XTRGEN GO/DONE Bank0 TRGEN TRGEN TRGEN ADCON2 ADC Control2 0000-000 GRP2 GRP1...
  • Page 24 SH79F7416 COMSEL COM mode select register 00000000 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 Bank0...
  • Page 25 SH79F7416 Table 6.16 PWM SFRs POR/WDT/LVR Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 symbol Address Name /PIN Reset PWM0CON PWM0 Control register 00000000 PWM0EN PWM0S PWM0CK2 PWM0CK1 PWM0CK0 PWM0IE PWM0IF PWM0SS Bank0 PWM1CON PWM1 Control register 00000000 PWM1EN PWM1S...
  • Page 26 SH79F7416 Table 6.16 CRC SFRs POR/WDT/LVR Name symbol Address /PIN Reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Value CRCCON CRC verify control 00--0000 CRC_GO CRCIF CRCADR3 CRCADR2 CRCADR1 CRCADR0 Bank0 CRCDL CRC verify result Low Byte 00000000 CRCD7...
  • Page 27 SH79F7416 Table 6.17 LCM SFRs POR/WDT/LVR symbol Address Name /PIN Reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Value UART0CR TXD0&RXD0 selection register -011-010 TX0CR2 TX0CR1 TX0CR0 RX0CR2 RX0CR1 RX0CR0 Bank1 UART1CR TXD1&RXD1 selection register -100-101 TX1CR2 TX1CR1 TX1CR0...
  • Page 28 SH79F7416 SFR Map Bank0 Non Bit addressable addressable SPSTA CRCDL CRCDH IB_OFFSET IB_DATA AUXC IB_CON1 IB_CON2 IB_CON3 IB_CON4 IB_CON5 XPAGE EXF2 P0PCR P1PCR P2PCR P3PCR P4PCR UTOS P0CR P1CR P2CR P3CR P4CR LCDSEG1 LCDSEG2 EXF1 PWM0CON PWM0PL PWM0PH PWM0DL PWM0DH...
  • Page 29 SH79F7416 Bank2 Non Bit addressable addressable AUXC P1CPL0 P1CPH0 P1CPL1 P1CPH1 XPAGE P2CPL0 P2CPH0 P2CPL1 P2CPH1 P3CPL0 P3CPH0 P3CPL1 P3CPH1 P2CF P0FORCE P2CPM0 P2CPM1 P3CPM0 P3CPM1 P3CF IPL0 IPL1 P1FORCE P2FORCE P3FORCE PCACON P1CPM0 IPH0 IPH1 P2TOPL P2TOPH IEN0 IEN1...
  • Page 30 SH79F7416 7. Normal Function 7.1 CPU 7.1.1 CPU core special function register Feature  CPU core registers: ACC, B, PSW, SP, DPL, DPH Accumulator Accumulator ACC is a commonly used special register. A is used as an mnemonic for the accumulator in the instruction system.
  • Page 31  Enhanced CPU core registers: AUXC, DPL1, DPH1, INSCON The SH79F7416 has modified 'MUL' and 'DIV' instructions. These instructions support 16 bits operand. A new register - the register is applied to hold the upper part of the operand/result. The AUXC register is used during 16 bits operand multiply and divide operations.
  • Page 32 256 bytes RAM; MOVX A, @DPTR or MOVX @DPTR, A also to access external 4136 bytes RAM. In SH79F7416 the user can also use XPAGE register to access external RAM only with MOVX A, @Ri or MOVX @Ri, A instructions.
  • Page 33 0000H Program Memory Block Information Block The SH79F7416 embeds 64K flash program memory for program code. The flash program memory provides electrical erasure and programming and supports In-Circuit Programming (ICP) mode and Self-Sector Programming (SSP) mode.Every sector is 512 bytes.
  • Page 34 SH79F7416 Code-protect control mode3:Customer password, write by customer, consists of 6 bytes. To enable the wanted protect mode, the user must use the Flash Programmer to set the corresponding protect bit. The user must use the following two ways to complete code protection control mode Settings: Flash programmer in ICP mode is set to corresponding protection bit to enter the protected mode.The SSP mode does not...
  • Page 35 SH79F7416 Write/Read (without security bit) (without security bit) EEPROM-like Write/Read 7.3.2 Flash Operation in ICP Mode Single Line Simulation model ICP mode is to program MCU through Flash programmer, which can be programmed after MCU is welded to the user board.
  • Page 36 The SH79F7416 builds in a complex control flow to prevent the code from carelessly modification.To enter the SSP mode, IB_CON2-5 must meet certain conditions. If the dedicated conditions are not met (IB_CON2-5), the SSP will be terminated.
  • Page 37 SH79F7416 Bit Number Bit Mnemonic Description IB_OFFSET[7:0] Low Address of Offset of the flash memory sector to be programmed Table 7.7 Data Register for Programming FCH,Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IB_DATA IB_DATA.7 IB_DATA.6 IB_DATA.5 IB_DATA.4 IB_DATA.3 IB_DATA.2 IB_DATA.1 IB_DATA.0...
  • Page 38 SH79F7416 IB_CON3[3:0] Must be 0AH else Flash Programming will terminate Table 7.11 SSP Flow Control Register3 F5H,Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IB_CON4 IB_CON4.3 IB_CON4.2 IB_CON4.1 IB_CON4.0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description IB_CON4[3:0] Must be 09H, else Flash Programming will terminate Table 7.12 SSP Flow Control Register4...
  • Page 39 SH79F7416 7.4.2 Flash Control Flow Set IB_OFFSET Set XPAGE Set IB_DATA Set IB_CON1 IB_CON2[3:0]≠5H Set IB_CON2[3:0]=5H IB_CON2≠5H IB_CON3≠AH IB_CON2≠5H Set IB_CON3=AH ELSE IB_CON3≠AH Set IB_CON4=9H IB_CON4≠9H Reset IB_CON1-5 Set IB_CON5=6H Sector Erase IB_CON1=E6H &IB_CON2[3:0]=5H &IB_CON3=AH &IB_CON4=9H &IB_CON5=6H IB_CON1=6EH &IB_CON2[3:0]=5H &IB_CON3=AH &IB_CON4=9H...
  • Page 40 SH79F7416 7.4.3 SSP Programming Note To successfully complete SSP programming, the user’s software must following the steps below: (1)For Code/DataProgramming 1. Disable interrupt; 2. Fill in the XPAGE, IB_OFFSET for the corresponding address; 3.Fill in IB_DATA if programming is wanted;...
  • Page 41 7.4.4 Readable identificantion Code Each chip of the SH79F7416 is factory-hardened with a 40-bit readable identification code. Its value is a random value of 0 - 0xffffffffff. It cannot be erased (stored in the address information memory area 0x127b - 127f) and can be read by program and program tool.
  • Page 42 (24MHz/128KHz), External Clock(128kHz~16MHz), which is selected by code option OP_OSC (Refer to code option section for details). SH79F7416 has2 Oscillator pins (XTAL1, XTAL2), which can generates one or two clock sources from three oscillator types. It is selected by code option OP_OSC (Refer to code option section for details). The oscillator generates the basic clock pulse that provides the system clock to supply CPU and on-chip peripherals.
  • Page 43 SH79F7416 7.5.4 Registers Table 7.14 System Clock Control Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 B2H,Bank0 32k_DR CLKCON 32k_SPDUP CLKS1 CLKS0 SCMIF HFON 32k_CAP Reset Value OP_32K OP_32K DRIVR (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description 32.768kHz oscillator speed up mode control bit 0: 32.768kHz oscillator normal mode, cleared by software.
  • Page 44 SH79F7416 Note: (1) If code option OP_OSC is 0011, 1010 OSCXCLK is internal 24MHzRC, if code option OP_OSC is 0110, OSCXCLK is oscillator from XTAL input. (2) HFON and FS is valid only when code option OP_OSC is 0011, 0110, 1010.
  • Page 45 SH79F7416 XTAL1 Crystal/Cer amic XTAL2 (5) OP_OSC = 1111: 128kHz~16MHz external clock input from XTAL1, XTAL2 shared with IO. External Clock XTAL1 XTAL2 Note: (1) The above capacitance value can be tested by the basic vibration and operation of the resonator, not the optimal value.
  • Page 46 SH79F7416 internal resonator drive circuit uses the industry-standard Pierce oscillator. It has the features of low power consumption, low cost, and good stability, so it is common in common applications. The equivalent circuit is shown 增益控制电路...
  • Page 47 Note:The resonator constants in the above table are based on the resonator model parameters referenced in the design of the SH79F7416 internal resonator drive circuit. In practical applications, this parameter can be used as a reference for selecting a resonator, and the resonator manufacturer is invited to evaluate the circuit design.
  • Page 48 7.6 System Clock Monitor (SCM) In order to enhance the reliability of the system, SH79F7416 contains a system clock monitoring (SCM) module. If the system clock fails (for example, external oscillator stops, etc.), the built-in SCM module will automatically switch OSCSCLK to the internal clock and the system clock monitor flag (SCMIF) will be set.
  • Page 49 PORT is used as input (x = 0-7, y = 0-7). For SH79F7416 , some I/O pins can share with alternative functions. There exists a priority rule in CPU toavoid these functions be conflict when all the functions are enabled. (Refer to Port Share Section for details).
  • Page 50 SH79F7416 Table 7.17 Port Pull up Resistor Control Register E9H - EDH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P0PCR (E9H, Bank0) P0PCR.7 P0PCR.6 P0PCR.5 P0PCR.4 P0PCR.3 P0PCR.2 P0PCR.1 P0PCR.0 P1PCR (EAH, Bank0) P1PCR.7 P1PCR.6 P1PCR.5 P1PCR.4 P1PCR.3 P1PCR.2 P1PCR.1...
  • Page 51 SH79F7416 Table 7.19 Port input mode select register(PIMS0) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 BAH,Bank1 PIMS0 P04S P05S P07S P10S P11S P12S P24S P25S Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description P0.4 input level logic control bit (not including port data register input) * 0: input high level threshold of 0.8vdd, input low level threshold of 0.2vdd (CMOS logic,...
  • Page 52 SH79F7416 Table 7.20 Port input mode select register(PIMS1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 BBH,Bank1 PIMS1 P26S P27S P41S P42S P43S P44S P45S P46S Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description P2.6 input level logic control bit (not including port data register input) * 0: input high level threshold of 0.8 V...
  • Page 53 SH79F7416 Table 7.21 Port input mode select register(PIMS2) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 BCH,Bank1 PIMS2 P55S P56S P57S P60S P61S P62S P67S P70S Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description P5.5input level logic control bit (not including port data register input) * 0: input high level threshold of 0.8 V...
  • Page 54 SH79F7416 Table 7.22 Port input mode select register(PIMS3) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 BDH,Bank1 PIMS3 P54S P53S Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description P5.4 input level logic control bit (not including port data register input) * 0: input high level threshold of 0.8 V...
  • Page 55 SH79F7416 7.7.3 Port Diagram SFEN PxPCRy Output Mode Input Mode 0 = ON (Pull-up) PxCRy 1 = OFF I/O Pad Write Data Data Bus Register Read Port Data Register Read Read Data Register/Pad Selection 0: From Pad 1: From data register...
  • Page 56 SH79F7416 ——— :SPI Master or Slave select (P0.2) - SS - SCK:SPI clock port (P0.3) - INT30-31:external interrupt(P0.4-P0.5) Table 7.23 PORT0 Share function Table Pin No. Priority Function Enable bit LQFP64 LQFP44 set SPEN bit in SPSTA register in slave mode...
  • Page 57 SH79F7416 P0.7 above condition is not met PORT1: - LCD Segment 8-14(P1.6-P1.0) - INT41:External Interrupt Input(P1.7) - AN4:ADC Input Channel(P1.7) - XTAL1:Resonator input(P1.7) Table 7.24 PORT1 Share function Table Pin No. Priority Function Enable bit LQFP64 LQFP44 set seg14-8 bit in SEG02...
  • Page 58 SH79F7416 PORT3: - AN6-AN8:ADC Input Channel(P3.5 - P3.7) - INT46:External Interrupt Input(P3.3) - INT40:External Interrupt Input(P3.0) - INT44:External Interrupt Input(P3.4) - AVREF:ADC external reference voltage input(P3.4) Table 7.26 PORT3 Share function Table Pin No. Priority Function Enable bit LQFP64 LQFP44 P3.0...
  • Page 59 SH79F7416 PORT5: - LCD Segment36-40(P5.7-P5.3) - AN10-AN13:ADC Input Channel(P5.1,P5.2,P5.5-P5.7) - VIN:LPD detection voltage input(P5.1) - P2CEX0:PCA2 Compare Capture Pin 0(P5.7) - INT43:External Interrupt Input(P5.4) - RXD3:EUART3 data input(P5.4) - TXD3:EUART3 data output(P5.3) - SWE:Single line simulation communication pin(P5.2) - INT0-INT1:External Interrupt Input(P5.0-P5.1)...
  • Page 60 SH79F7416 PORT6: - LCD Segment 28-35(P6.7-P6.0) - AN14:ADC Input Channel(P6.0) - P2CEX1:PCA2 Compare Capture Pin 1(P6.0) - ECI2:PCA2 clock input(P6.1) - T4:Timer 4 External Input(P6.3) - INT47:External Interrupt Input(P6.2) - INT34-35:External Interrupt Input(P6.4-P6.5) - T2EX:Timer2 external input(P6.6) - TCK:Debug interface for testing clock input(P6.7)...
  • Page 61 SH79F7416 PORT7: - LCD Segment 23-27(P7.4-P7.0) - AN0-AN1:ADC Input Channel(P7.3-P7.4) - T3:Timer 3 External Input(P7.4) - TDI:Debug interface for test data input(P7.0) - TMS:Debug interface for test mode selection(P7.1) - TDO:Debug interface for test data output(P7.2) - P1CEX0:PCA1 Compare Capture Pin 0(P7.0)...
  • Page 62 SH79F7416 7.8 Timer  The SH79F7416 has three timers (Timer 3, 4, 5)  Timer3 is a 16-bit auto-reload timer and can operate even in Power-Down mode  Timer4 is a 16-bit auto-reload timer  Timer5 is a 16-bit auto-reload timer 7.8.1 Timer3...
  • Page 63 SH79F7416 Note: (1) When T3 is selected as Timer3 clock source, read or write TH3 and TL3, must make sure TR3 = 0. When system clock is selected as Timer3 clock source, TH3 and TL3 can be read or written at anytime.
  • Page 64 SH79F7416 7.8.2 Timer4 Timer4 is a 16-bit auto-reload timer. It is accessed as two cascaded data registers: TH4 and TL4. It is controlled by the T4CON register. The Timer 4 interrupt can be enabled by setting ET4 bit in IEN1 register (Refer to interrupt Section for details).
  • Page 65 SH79F7416 Mode1: 16 bit Auto-Reload Timer with T4 Edge Trig Timer4 operates as 16-bit timer in Mode1. T4CLKS bit in T4CON.0 will be 0 always.Timer4 can select system clock as clock source. Other setting accords with mode 0. In Mode1, After Setting the TR4 bit (T4CON.1), Timer4 does not start counting but waits the trig signal (rising or falling edge controlled by T4M[1:0]) from T4.
  • Page 66 SH79F7416 7.8.2.2 Registers Table 7.33 Timer4 Control Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 D8H,Bank1 T4CON T4PS1 T4PS0 T4M1 T4M0 T4CLKS Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Timer4 overflow flag bit 0: No overflow (cleared by hardware)
  • Page 67 SH79F7416 7.8.3 Timer5 Timer5 is a 16-bit auto-reload timer. It is accessed as two cascaded data registers: TH5 and TL5. It is controlled by the T5CON register. The interrupt can be enabled by setting ET5 bit in IEN0 register (Refer to interrupt Section for details).
  • Page 68 SH79F7416 7.8.3.2 Registers Table 7.35 Timer5 Control Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 C0H,Bank1 T5CON T5PS1 T5PS0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Timer5 overflow flag bit 0: No overflow (cleared by hardware) 1: Overflow (Set by hardware)
  • Page 69 7.9 Programmable counter array(PCAx(x = 0、1、2、3)) 7.9.1 Feature  SH79F7416 has Four 16-bit timer PCA, PCA0 - 2 has two independent comparison capture module  Phase Correct PWMMode, Phase frequency Correct PWM Mode The Programmable Counter Array (PCAx) provides enhanced timer functionality while requiring less CPU intervention than the standard 8051 counter/timers.The PCAx consists of a dedicated 16-bit counter/timer and two 16-bit capture/compare...
  • Page 70 SH79F7416 Timer/Counter 16-bit Counter is also forced to clear '0'.When the timer from 0x0000 to PxTOP overflow (PxTOP to 0x0000 in the same system clock, the single slope model) or counter from PxTOP countdown to 0x0000 (PCAx Counter work in dual slope model), the overflow in the PxCF register of marks provided (CFx) is set to logic '1' and generate an interrupt request (PxCMD ECFx bit is set to logic '1' can be provided to allow CFx marks an interrupt request).
  • Page 71 SH79F7416 Mode2 frequency output(singleslope) 8 bit PWM(singleslope) 16 bit PWM(singleslope) Mode3 16bit phasecorrectionPWM (dual ramp) 16bit Phasefrequency correctionPWM (dual ramp) PCA0 Counter correctly, butthe compare/capturemodule Others does notwork. X: Don’t Care; When PCAx is set to one of two types of ramps, the other ramp mode of the comparison capture module is invalid even if it is configured.
  • Page 72 SH79F7416 PxCPS2 - 0 Sysclk PxTOPH PxTOPL Sysclk/4 Overflow Sysclk/12 Flag Sysclk/32 Overflow TIMER3 16Bit Compare ECIx Crystal/8 32.768k Clear Interrupt PxSMPn PxFSPn Request PxSMNn Capture PxECOMn PxCEXn PxFSNn PxCPHn PxCPLn PxCCFn PxTCPn Figure 7.9-4: PCAxCapture Mode Diagram Note:ThePxCEXn input signal must remain high or low for at least 4 system clock periods to be recognized by the hardware.
  • Page 73 SH79F7416 CFx SET 1, NEW TOP AND PxCPn RELOAD PxCCFn SET 1 PCAx PxCEXn Figure 7.9-6:softwaretimer modeprinciple diagram When PxFSPn: PxFSNn =1x, compare/capture module work in single trigger mode, by setting bit PxOSCn in PxFORCE register to generate single rising or falling edge.
  • Page 74 SH79F7416 7.9.5 Mode3:PWM mode Each PCAx module can be used independently to generate a pulse width modulated (PWM) output.Configuring PxSMPn:PxSMNn = 11 will enable compare/capture module n to operate in PWM mode. In this mode, configuring the PxFSPn and PxFSNn bits enables the compare/capture module n to operate in one of four PWM functions.
  • Page 75 SH79F7416 PxCPLn Reload Refresh PxCCFn set 1 Write Register: Write Register: Write Register: Write Register: Write Register: PxTOPL=FFH PxTOPL=FFH PxTOPL=FFH PxTOPL=FFH PxTOPL=FFH PxCPHn=00H PxCPHn=01H PxCPHn=80H PxCPHn=FEH PxCPHn=FF PxCPLn=00H PCAx Counter PxCEXn PxCEXn Period The small horizontal linerepresents PxCPLn value, the dot represents PxTOP value Figure 7.9-9:8 bit PWM waveform...
  • Page 76 SH79F7416 CFx set 1, PxTOP,PxCPn Refresh Write Register: Write Register: Write Register: Write Register: Write Register: Write Register: Write Register: Write Register: PxCCFn set 1 PxTOPH=FFH PxTOPH=FFH PxTOPH=02H PxTOPH=4FH PxTOPH=02H PxTOPH=FFH PxTOPH=FFH PxTOPH=FFH PxTOPL=FFH PxTOPL=FFH PxTOPL=FFH PxTOPL=FFH PxTOPL=FFH PxTOPL=71H PxTOPL=FFH...
  • Page 77 SH79F7416 PxTOP,PxCPn Refresh PxCCFn set 1 CFx set 1 PCAx Counter PxCEXn PxCEXn Period Figure7.9-1316 bit XPWMwaveform To change the PxTOP value while the PCAx is running, it is better to use the phase and frequency correction mode instead of the phase correction mode. If PxTOP remains unchanged, then there is virtually no difference between the two modes of operation.
  • Page 78 SH79F7416 PxTOP value), PxCPn dual buffering characteristics make it more suitable for this application. PxCCFn set 1 CFx set1, PxTOP,PxCPn Refresh PCAx Counter PxCEXn PxCEXn Period Frigue 7.9-1516 bit XPPWM waveform The PWM resolution for the phase correct PWM mode can be configured by PxTOP. The minimum resolution allowed is 2-bit(PxTOP set to 0x003), and the maximum resolution is 16-bit(PxTOP set to 0xff).
  • Page 79 SH79F7416 (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description PCA3 counter/timer run control 0: PCA3 counter/timerdisable 1: PCA3 counter/timerenable PCA2 counter/timer run control 0: PCA2 counter/timerdisable 1: PCA2 counter/timerenable PCA1 counter/timer run control 0: PCA1 counter/timerdisable 1: PCA1 counter/timerenable PCA0 counter/timer run control...
  • Page 80 SH79F7416 P2CPM1 (CAH) P2SMP1 P2SMN1 P2FSP1 P2FSN1 P2ECOM1 P2TCP1 P2MAT1 P2ECCF1 P3CPM0 (CBH) P3SMP0 P3SMN0 P3FSP0 P3FSN0 P3ECOM0 P3TCP0 P3MAT0 P3ECCF0 P3CPM1 (CCH) P3SMP1 P3SMN1 P3FSP1 P3FSN1 P3ECOM1 P3TCP1 P3MAT1 P3ECCF1 RESET value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description PCAx mode select...
  • Page 81 SH79F7416 Table 7.41 PxFORCE forced output control register Bank2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P0FORCE (DCH) P0OSC1 P0OSC0 P0FCO1 P0FCO0 P1FORCE (BDH) P1OSC1 P1OSC0 P1FCO1 P1FCO0 P2FORCE (BEH) P2OSC1 P2OSC0 P2FCO1 P2FCO0 P3FORCE (BFH) P3OSC1 P3OSC0 P3FCO1...
  • Page 82 SH79F7416 Table 7.43 PCAxcount maximum high byte Bank2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P0TOPH (9FH) P0TOPH.7 P0TOPH.6 P0TOPH.5 P0TOPH.4 P0TOPH.3 P0TOPH.2 P0TOPH.1 P0TOPH.0 P1TOPH (AFH) P1TOPH.7 P1TOPH.6 P1TOPH.5 P1TOPH.4 P1TOPH.3 P1TOPH.2 P1TOPH.1 P1TOPH.0 P2TOPH (B7H) P2TOPH.7 P2TOPH.6 P2TOPH.5...
  • Page 83 SH79F7416 Table 7.45 PCAxcapture/compare module high byte Bank2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P0CPH0 (9DH) P0CPH0.7 P0CPH0.6 P0CPH0.5 P0CPH0.4 P0CPH0.3 P0CPH0.2 P0CPH0.1 P0CPH0.0 P0CPH1 (ADH) P0CPH1.7 P0CPH1.6 P0CPH1.5 P0CPH1.4 P0CPH1.3 P0CPH1.2 P0CPH1.1 P0CPH1.0 P1CPH0 (F3H) P1CPH0.7 P1CPH0.6 P1CPH0.5...
  • Page 84 SCM interrupt,1 SPI interrupt,1 ADC interrupt ,3 PWM interrupts, 1 LED interrupt, 1 TWI interrupt, 1 CRC interrupt, 1 LPD interrupt. The SH79F7416 have 4 interrupt priority levels, which make operating 27 interrupt sources becoming flexible. Otherwise,the SH79F7416 also provide 4 ttigger modes for INT4, which can be selected through register.
  • Page 85 SH79F7416 Table 7.47 Interrupt Enable Register 1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IEN1 ESPI EPCA0 ELED ETWI Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description External interrupt3 enable bit 0: Disable INT3 interrupt 1: EnableINT3 interrupt SPI interrupt enable bit...
  • Page 86 SH79F7416 Table 7.48 Interrupt Enable Register2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IEN2 EPWM1 EPCA1 EPWM0 ECRC Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description PWM1 interrupt enable bit EPWM1 0: Disable PWM1 interrupt 1: Enable PWM1 interrupt...
  • Page 87 SH79F7416 Table 7.50 Interrupt channel Enable Register 1 BAH,Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IENC EXS47 EXS46 EXS45 EXS44 EXS43 EXS42 EXS41 EXS40 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description External interrupt4 channel select bit (x = 0-7)
  • Page 88 SH79F7416 7.10.3 Interrupt Flag Each Interrupt source has its own interrupt flag, when interrupt occurs, corresponding flag will be set by hardware, the interrupt flag bits are listed in Table bellow. For external Interrupt INT0/1, When External Interrupt INTx (x = 0, 1) is generated, if the interrupt is edge triggered, the CPU clears the flag IEx (x = 0, 1) if the interrupt is acknowledged by the CPU;...
  • Page 89 SH79F7416 Table 7.53 External interrupt flag register 88H,Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TCON Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description External interrupt x request flag 3,1 0: No interrupt pending (x = 0,1) 1: Interrupt is pending External interrupt x trigger mode 2,0...
  • Page 90 SH79F7416 Table 7.55 External Interrupt 4 Flag Register D8H,Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EXF1 IF47 IF46 IF45 IF44 IF43 IF42 IF41 IF40 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description External interrupt4 request flag bit IF4x...
  • Page 91 SH79F7416 7.10.4 Interrupt Vector When an interrupt occurs, the program counter is pushed onto the stack and the corresponding interrupt vector address is loaded into the program counter. The interrupt vector addresses are listed in Interrupt Summary table. 7.10.5 Interrupt Priority Each interrupt source can be individually programmed to one of four priority levels by setting or clearing corresponding bits in the interrupt priority control registers IPL0, IPH0, IPL1, and IPH1.
  • Page 92 SH79F7416 7.10.6 Interrupt Handling The interrupt flags are sampled and polled at the fetch period of each machine period. All interrupts are sampled at the rising edge of the clock. If one of the flags was set, the CPU will find it and the interrupt system will generate a LCALL to the appropriate service routine, provided this hardware-generated LCALL is not blocked by any of the following conditions: An interrupt of equal or higher priority is already in progress.
  • Page 93 External interrupt 3/4 is similar to the external interrupt 0,1 except that it has more interrupt trigger modes. When SH79F7416 is in IDLE mode or Power-Down mode, interrupt will cause the processor to wake up and resume operation, refer to “Power Management” chapter for details.
  • Page 94 SH79F7416 Table 7.58 External interrupt sample times control registrer 8BH,Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EXCON I1PS1 I1PS0 I1SN1 I1SN0 I0PS1 I0PS0 I0SN1 I0SN0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description INT4 sample clock Prescaler Select bits 00:1/1...
  • Page 95 SH79F7416 7.10.9 Interrupt Summary Vector Polling Interrupt Source Enable bits Flag bits Address Priority No. (C51) Reset 0000H (highest) INT0 0003H PCA3 000BH ECF3 INT1 0013H EUART1 001BH RI1+TI1 EUART0 0023H RI+TI EUART2 002BH RI2+TI2 0033H EADC ADCIF 003BH ETWI...
  • Page 96 Therefore, SH79F7416 provides both the low power consumption and display effect of the display mode: fast charge mode. Set MOD[1:0] = 10 to select this mode. When refresh the display data 20k bias resistors are selected to provide larger current.
  • Page 97 SH79F7416 one frame COM4 COM1 COM3 COM2 COM2 COM1 COM3 COM4 SEGn+1 SEGn SEGn SEGn+1 COM4 - SEGn -Vcc LCD Waveform (1/4duty, 1/3bias)
  • Page 98 SH79F7416 COM8 COM1 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM2 COM3 COM4 SEGn SEGn COM1- SEGn - V1 - V2 - V3 LCD Waveform (1/8 duty, 1/4 bias)
  • Page 99 1101:VLCD = 0.938VDD 1110:VLCD = 0.969VDD 1111:VLCD = 1.000VDD Note : SH79F7416 has LCD and LED driver,but can not work in the same time , When enabled LED and LCD function at disabled, the same time, LCD will be LED will be enabled...
  • Page 100 SH79F7416 Table 8.2 LCD Control Register1 AEH (Bank0) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DISPCON1 DUTY2 DUTY1 DUTY0 RLCD FCCTL1 FCCTL2 MOD1 MOD0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description LCD duty selected bits (control with DUTY0) 000:1/4 Duty,1/3 Bias(4 COM X 40 SEG)...
  • Page 101 SH79F7416 Table 8.3 LCD Clock Control Register ADH (Bank0) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DISPCLK0 DCK1 DCK0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description LCD clock frequency division selectiom bits 00: divided by 4 01: divided by 3...
  • Page 102 SH79F7416 续上表 SEG2 port mode selection bit P1S1 0:P2.6 is I/O 1:P2.6 is SEG2 SEG1 port mode selection bit P1S0 0:P2.7 is I/O 1:P2.7 is SEG1 Table 8.5 LCD Port mode selection register 2 E7H,Bank0 Bit7 Bit6 Bit5 Bit4 Bit3...
  • Page 103 SH79F7416 Table 8.6 LCD Port mode selection register3 E7H,Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LCDSEG3 P3S7 P3S6 P3S5 P3S4 P3S3 P3S2 P3S1 P3S0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description SEG24 port mode selection bit P3S7 0:P7.3 is I/O...
  • Page 104 SH79F7416 Table 8.7 LCD Port mode selection register4 CFH,Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LCDSEG4 P4S7 P4S6 P4S5 P4S4 P4S3 P4S2 P4S1 P4S0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description SEG32 port mode selection bit P4S7 0:P6.3 is I/O...
  • Page 105 SH79F7416 Table 8.8 LCD Port mode selection register5 C6H,Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LCDSEG5 P5S7 P5S6 P5S5 P5S4 P5S3 P5S2 P5S1 P5S0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description SEG40 port mode selection bit P5S7 0:P5.3 is I/O...
  • Page 106 SH79F7416 8.1.2 LCD RAM configuration LCD 1/4 duty, 1/3 bias (COM1 - 4, SEG1 - 40) Address COM4 COM3 COM2 COM1 1000H SEG1 SEG1 SEG1 SEG1 1001H SEG2 SEG2 SEG2 SEG2 1002H SEG3 SEG3 SEG3 SEG3 1003H SEG4 SEG4 SEG4...
  • Page 107 SH79F7416 LCD 1/8 duty,1/4 bias(COM1 - 8,SEG1 - 40) Address COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 1000H SEG1 SEG1 SEG1 SEG1 SEG1 SEG1 SEG1 SEG1 1001H SEG2 SEG2 SEG2 SEG2 SEG2 SEG2 SEG2 SEG2 1002H SEG3 SEG3 SEG3...
  • Page 108 SH79F7416 LCD 1/5 duty, 1/3 bias (COM1 - 5, SEG1 - 40) Address COM5 COM4 COM3 COM2 COM1 1000H SEG1 SEG1 SEG1 SEG1 SEG1 1001H SEG2 SEG2 SEG2 SEG2 SEG2 1002H SEG3 SEG3 SEG3 SEG3 SEG3 1003H SEG4 SEG4 SEG4...
  • Page 109 SH79F7416 LCD 1/6 duty, 1/3 or 1/4 bias (COM1 - 6, SEG1 - 40) Address COM6 COM5 COM4 COM3 COM2 COM1 1000H SEG1 SEG1 SEG1 SEG1 SEG1 SEG1 1001H SEG2 SEG2 SEG2 SEG2 SEG2 SEG2 1002H SEG3 SEG3 SEG3 SEG3...
  • Page 110  Provided interrupt function on period overflow  Selectable output polarity The SH79F7416 has three 12-bit PWM module. Which can provide three channel pulse width modulation waveform with the period and the duty being controlled individually by corresponding register. PWMxEN(x = 0-2) used to enable PWM modules.
  • Page 111 SH79F7416 PWMx pin output control bit 0: PWMxoutput disable, PWMx as I/O , Note: if this bit is 0 but PWMxEN = 1 the PWM timer can work normally, only PWMxSS can not output waveform, the PWMx still can be used as a timer.
  • Page 112 SH79F7416 Table 8.17 PWMx Duty Control Register PWMxDH/L(x = 0-2) Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWM0DH (DDH) PWM0D.11 PWM0D.10 PWM0D.9 PWM0D.8 PWM0DL (DCH) PWM0D.7 PWM0D.6 PWM0D.5 PWM0D.4 PWM0D.3 PWM0D.2 PWM0D.1 PWM0D.0 PWM1DH (C5H) PWM1D.11 PWM1D.10 PWM1D.9 PWM1D.8 PWM1DL (C4H) PWM1D.7...
  • Page 113 SH79F7416 PWM clock t PWM output (PWMS=0) PWM output (PWMS=1) PWMP = F0H PWM output duty cycle = 7FH x t PWMD = 7FH PWM output period cycle = F0H x t PWM Output Example 08 09 0A 0B 0C 0D 01 02...
  • Page 114 (SCONx.5). When this bit is set to 0, the serial port runs at 1/12 of the system clock. When set to 1, the serial port runs at 1/4 of the system clock. The only difference from the standard 8051 is that the SH79F7416 has 2 baud rates available in Mode 0.
  • Page 115 SH79F7416 Any instruction that uses SBUFxas a destination register (“write to SBUFx” signal) will start the transmission. The next system clock tells the Tx control block to commence a transmission. The data shift occurs at the falling edge of the SHIFT CLOCK, and the contents of the transmit shift register is shifted one position to the right.
  • Page 116 SH79F7416 Transmission begins with a “write to SBUFx” signal, and it actually commences at the next system clock following the next rollover in the divide-by-16 counter (divide baud-rate by 16), thus, the bit times are synchronized to the divide-by-16 counter, not to the “write to SBUFx”...
  • Page 117 SH79F7416 Mode2: 9-Bit EUARTx, Fixed Baud Rate, Asynchronous Full-Duplex This mode provides the 11 bits full duplex asynchronous communication. The 11 bits consists of one start bit (logical 0), 8 data bits (LSB first), a programmable 9 data bit, and a stop bit (logical 1). Mode 2 supports multiprocessor communications and hardware address recognition (Refer to Multiprocessor Communication Section for details).
  • Page 118 SH79F7416 Reception is enabled only if RXDxis high. The serial port actually starts the receiving of serial data, with the detection of a falling edge on the RXDxpin. For this purpose RXDxis sampled at the rate of 16 times baud rate. When a falling edge is detected, the divide-by-16 counter is immediately reset.
  • Page 119 SH79F7416 8.3.3 Baud Rate Generate EUARTx with own baud rate generator, the baud rate generator is an 15-bit up-counting timer. Overflow 15-bit timer To EUART Fsys From 7FFFH to 0000H SBRTEN=1 SBRTH[14:8],SBRTL7:0] Baudrate Generator for EUART The overflow rate of baud rate generator can be calculated as follow:...
  • Page 120 SH79F7416 8.3.4 Multi-Processor Communication Software Address Recognition Modes 2 and 3 of the EUARTx have a special provision for multi-processor communication. In these modes, 9 data bits are received. The 9th bit goes into RB8. Then a stop bit follows. The EUARTxcan be programmed such that when the stop bit is received, the EUARTxinterrupt will be activated (i.e.
  • Page 121 SH79F7416 8.3.5 Error Detection Error detection is available when the SSTAT bit in register PCON is set to logic 1. All the 3 bits should be cleared by software after they are set, even when the following frames received without any error will not be cleared automatically.
  • Page 122 SH79F7416 Table 8.23 EUART0 Control and Status Register 98H,Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCON /RXOV /TXCOL Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description EUART0 Serial mode control bits, when SSTAT = 0 00: mode 0, Synchronous Mode, fixed baud rate...
  • Page 123 SH79F7416 Table 8.24 EUART0 Data Buffer Register 99H,Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SBUF SBUF.7 SBUF.6 SBUF.5 SBUF.4 SBUF.3 SBUF.2 SBUF.1 SBUF.0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description This SFR accesses two registers; a transmit shift register and a receive latch...
  • Page 124 SH79F7416 Table 8.28 EUART1 Control & Status Register B0H,Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SM10/FE1 SM11/RXOV1 SM12/TXCOL1 REN1 TB81 RB81 SCON1 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description EUART1 Serial mode control bits, when SSTAT1 = 0...
  • Page 125 SH79F7416 Table 8.29 EUART1 Data Buffer Register A7H,Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PCON1 SMOD1 SSTAT1 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description EUART1 Baud rate doubler SMOD1 0: in Mode2, the baud-rate of EUART is 1/64 of the system clock...
  • Page 126 SH79F7416 Table 8.32 EUART1 Baudrate generator register A5H-A4H,Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SBRTEN1 SBRT1.14 SBRT1.13 SBRT1.12 SBRT1.11 SBRT1.10 SBRT1.9 SBRT1.8 SBRTH1 (A5H) SBRT1.7 SBRT1.6 SBRT1.5 SBRT1.4 SBRT1.3 SBRT1.2 SBRT1.1 SBRT1.0 SBRTL1 (A4H) Reset Value (POR/WDT/LVR/PIN) Bit Number...
  • Page 127 SH79F7416 EUART2 Transmit Collision flag, when TXCOL2 bit is read, SSTAT2 bit must be set 1 TXCOL2 0: No Transmit Collision, clear by software 1: Transmit Collision occurs, set by hardware EUART2 Receiver enable bit REN2 0: Receive Disable 1: Receive Enable The 9th bit to be transmitted in Mode2 &...
  • Page 128 SH79F7416 Table 8.37 EUART2 Slave Address & Address Mask Register 92H-93H,Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SADDR2 (92H) SADDR2.7 SADDR2.6 SADDR2.5 SADDR2.4 SADDR2.3 SADDR2.2 SADDR2.1 SADDR2.0 SADEN2 (93H) SADEN2.7 SADEN2.6 SADEN2.5 SADEN2.4 SADEN2.3 SADEN2.2 SADEN2.1 SADEN2.0 Reset Value...
  • Page 129 SH79F7416 Table 8.40 EUART3 Baudrate generator fine-tune register F8H,Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SM30 SM31 SM32 SCON3 REN3 TB83 RB83 /FE3 /RXOV3 /TXCOL3 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description EUART3 Serial mode control bits, when SSTAT3 = 0...
  • Page 130 SH79F7416 Table 8.41 EUART3 serial control register FFH,Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PCON3 SMOD3 SSTAT3 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description UART3 baud rate multiplier SMOD3 0: in mode 2, the baud rate is 1/64 of the system clock...
  • Page 131 SH79F7416 Table 8.44 EUART3 Baudrate generator register FDH-FCH,Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SBRTH3 (FDH) SBRTEN3 SBRT3.14 SBRT3.13 SBRT3.12 SBRT3.11 SBRT3.10 SBRT3.9 SBRT3.8 SBRTL3 (FCH) SBRT3.7 SBRT3.6 SBRT3.5 SBRT3.4 SBRT3.3 SBRT3.2 SBRT3.1 SBRT3.0 Reset Value (POR/WDT/LVR/PIN) Bit Number...
  • Page 132  Programmable Slave Address The TWI Interface complete the transition with SDA and SCL, between Master and Slaver.SH79F7416 has the ability to process and transmit byte, and track the serial transaction automaticly ,which conforms to TWI protocol. TWIclock is system clock.
  • Page 133 STOP SH79F7416 generates an ACK by pulling the SDA line low. After the interrupt flag be set, SH79F7416 pulls the SCL line low,and releases SDA line.When the interrupt process has completed, SCL line should be released and TWINT flag should be cleared.
  • Page 134 SH79F7416 Data Arbitration A master may start a transfer only if the bus is free. Two or more masters may generate a START condition within the )of the START condition which results in a defined START condition to the bus.
  • Page 135 FREE> Bus. The function is only used in the transmission process of one packet (8 + 1 bit). When SH79F7416 is in slave transfer mode and the first byte of transferred message is low, the function can be used. STA and RSTA is not situable for this function. If SH79F7416 generates interrupt, TFREE bit in TWICON regiser will be set (if control bit EFREE bit has been set).
  • Page 136 SH79F7416 8.4.4 Transmission Modes TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like reception of a byte or transmission of a START condition. Because the TWI is interrupt-based, the application software is free to carry on other operations during a TWI byte transfer.
  • Page 137 SH79F7416 Status codes for master transmitter mode Application software response R/W data Control bit operation TWI bus and serial Status register Next Action Taken by TWI Hardware interface hardware status TWIDAT STA STO operation A START condition has been Load...
  • Page 138 SH79F7416 Master Transmitter Successfull transmission to a slave SLA+W DATA receiver Next transfer started with a repeated start SLA+W condition SLA+R Not acknowledge received Master Nack after the slave address Receiver Not acknowledge received Nack after a data byte Arbitration lost in slave...
  • Page 139 SH79F7416 Master Receiver Mode In the Master Receiver mode, a number of data bytes are received from a Slave Transmitter. In order to enter a Master mode,aSTART condition mustbe transmitted. The format of the following address packet determines whether MasterTransmitter or Master Receiver mode is to be entered. If SLA+W is transmitted, MTmode is entered, if SLA+R is transmitted, MR mode is entered.
  • Page 140 SH79F7416 Master Receiver Successfull reception SLA+R DATA DATA Nack from a slave transmitter Next transfer started with a repeated start SLA+R condition SLA+W Not acknowledge received Master Nack after a data byte Transmitter Arbitration lost in slave Ack or address or not acknowledged...
  • Page 141 TWICON register and TWIADR register must be initialized: set ENTWI bit and AA bit in TWICON register, clearing STA, STO and TWINT; The high 7-bit in TWIADR register is used to prepare the corresponding address for SH79F7416. If GC is set, SH79F7416 will respond the general address (00H); Otherwise, will not respond the address.
  • Page 142 Arbitration lost as master and addressed as slave transmitter Last data byte transmitted, Switched to not addressed All '1' P or S slave (AA = 0) Other Device Actions SH79F7416 Actions...
  • Page 143 If the AA bit is cleared during a transfer, TWI will receive the last byte and respond NACK. Responding NACK indicates the current slaver can’t receive more bytes. When AA = 0, SH79F7416 can’t respond the visit to its own address. However, SH79F7416 still monitors the bus status, and address recognition may resume at any time by setting AA.
  • Page 144 SH79F7416 Status codes for slave Receiver mode Application software response TWI bus and serial interface R/W data register Control bit operation Next Action Taken by TWI Status hardware status TWIDAT operation Hardware STA STO data byte will be transmitted and NOT ACK shouldbe Own SLA+W has been received;...
  • Page 145 SH79F7416 Previously addressed with data byte will be transmitted and NOT ACK shouldbe received general call; data has been Load data byte received; data byte will be transmitted and ACK has been returned ACK shouldbe received Switched to the not addressed Slave mode;...
  • Page 146 SH79F7416 Reception of the own SLA+W DATA DATA P or S slave address and one or more data bytes, All are acknowledged Arbitration lost as master and addressed as slave receiver Last data byte received is Nack P or S...
  • Page 147 SH79F7416 8.4.5 Register Table 8.46TWI control register C8H,Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TWICON TOUT ENTWI TWINT TFREE EFREE Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Bus Timeout Flag 0: No Timeout TOUT 1: Timeout happened when the periods of bus low level is more than N*Tsys.Then the bit will be set.
  • Page 148 SH79F7416 Table 8.47 Timeout For Bus Low level Count Register C9H,Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CNT1 CNT0 TWITOUT TWIPCR Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Bus Timeout Count 00:N=25000 01:N=50000 CNT[1:0] 10:N=100000 11:N=200000 N used in timeout for bus...
  • Page 149 SH79F7416 Table 8.50TWI Bit Rate Register 8AH,Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TWIBR TWIBR.7 TWIBR.6 TWIBR.5 TWIBR.4 TWIBR.3 TWIBR.2 TWIBR.1 TWIBR.0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description selects the division factor for the bit rate generator TWIBR [7:0] Table 8.51 TWI (Slave) Address Register...
  • Page 150 SH79F7416 8.5 Serial External Device Interface (SPI) 8.5.1 Features ■ Full-duplex, three-wire synchronous transmission ■ Master slave operation ■ 8 programmable master clock frequencies ■ Polar phase programmable serial clock ■ Main mode failure error flag with MCU interrupt ■ Write conflict flag protection ■...
  • Page 151 SH79F7416 ——— The SS pin can be used as a normal port or other function in the following cases: (1) The device acts as the master device and the SSDIS bit in the SPICON control register, SPCON register, is set.
  • Page 152 SH79F7416 8.5.5 Working Mode The SPI can be configured as one of master mode or slave mode. The configuration and initialization of the SPI module is done by setting the SPCON register (serial peripheral control register) and SPSTA (serial peripheral status register). After the configuration is completed, data transmission is completed by setting SPCON, SPSTA, and SPDAT (Serial Peripheral Device Data Registers).
  • Page 153 SH79F7416 To prevent overruns, the SPI slave must also clear the SPIF flag before software shifts data into the receive shift register. Otherwise, the RXOV bit is set to indicate a data overrun. At this point the receive shift register retains the old data and the SPIF bit is set so that the SPI slave device will not receive any data until SPIF is cleared.
  • Page 154 SH79F7416 8.5.7 Error Detection The flag in the SPSTA register indicates an error condition in SPI communication: (1) Mode Failure (MODF) A mode fault error in SPI master mode indicates that the level state on the SS pin is inconsistent with the actual device mode.
  • Page 155 SH79F7416 8.5.9 Registers Table 8.54 SPI Control Registers A2H,Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SPCON MSTR CPHA CPOL SSDIS SPR2 SPR1 SPR0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Direction of transmission selection 0: MSBfirstsent 1: LSB first send...
  • Page 156 SH79F7416 Table 8.55 SPI Status Registers F8H,Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SPSTA SPEN SPIF MODF WCOL RXOV Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description SPI control bits SPEN 0: Close SPI 1: Open SPI interface...
  • Page 157 SH79F7416 8.6 Logic Configurable Module(LCM) 8.6.1 Features  Though the Logic Configurable Module 14 kinds of Logic function port can be remap to I/O, and each function can choose one of the eight IO to map. The Logic Configurable Module( LCM) used to realize the remap of some logic function port, and keep the one-to-one match between logic and hardware.
  • Page 158 SH79F7416 Functio UART0 UART1 UART2 PWM0 PWM1 INT2 PCA0 RXD0 TXD0 RXD1 TXD1 RXD2 TXD2 SDA PWM0 PWM1 INT2 P0CEX0 P0CEX1 ECI0 P0.0 P0.1 P0.2 P0.3 ● ●  ● ● P0.4  ● ● ● P0.5 ● P0.6 ●...
  • Page 159 SH79F7416 (continue) Functio UART0 UART1 UART2 PWM0 PWM1 INT2 PCA0 RXD0 TXD0 RXD1 TXD1 RXD2 TXD2 SDA PWM0 PWM1 INT2 P0CEX0 P0CEX1 ECI0 ● P5.0 P5.1 P5.2 P5.3 P5.4 ● ● ● ● ● ● P5.5 ● ● ● ●...
  • Page 160 SH79F7416 8.6.2 Register Table 8.57 TXD0 and RXD0 selection register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DAH,Bank0 UART0CR TX0CR2 TX0CR1 TX0CR0 RX0CR2 RX0CR1 RX0CR0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description TXD0 Selection Bits 000:TXD0 map to P1.1 001:TXD0 map to P1.2...
  • Page 161 SH79F7416 Table 8.59 TXD2 and RXD2 selection register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 D9H,Bank1 UART2CR TX2CR2 TX2CR1 TX2CR0 RX2CR2 RX2CR1 RX2CR0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description TXD2 Selection Bits 000:TXD2 map to P0.4 001:TXD2 map to P0.5 010:TXD2 map to P4.5...
  • Page 162 SH79F7416 Table 8.61 PWM1 and PWM0 selection register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 E6H,Bank1 PWMCR PW1CR2 PW1CR1 PW1CR0 PW0CR2 PW0CR1 PW0CR0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description PWM1 Selection Bits map to (Default) 000:PWM1 P4.1 map to 001:PWM1...
  • Page 163 SH79F7416...
  • Page 164 SH79F7416 Table 8.63 ECI0 and INT2 selection register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 D1H,Bank0 ECICR INT2CR2 INT2CR1 INT2CR0 ECICR2 ECICR1 ECICR0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description INT2 Selection Bit map to 000:INT2 P1.5 map to 001:INT2...
  • Page 165  INT2(rising-edge, falling-edge, double-edge), the overflow of PCA0, PWM1 or Timer3 can trigger an ADC conversion.  Up to 1MSPS The SH79F7416 includes a single ended, 12-bit SAR Analog to Digital Converter (ADC Analog-to-Digit Converter). Moduleas shown in figure8.8-1. After reset, the default reference voltage of ADC is VDD.Users can select external input voltage V reference voltage.
  • Page 166 SH79F7416 8.8.2 ADC Diagram Software Trigger Event Trigger sequence mode SEQCH0 State pointer GRP[2:0] SEQCHn SEQCH7 Mode Arbiter ADD0L/H CH13 12-Bits ADDnL/H ADD7L/H (1.20V) CH8/VREF ADC_Clk Time Gap Refc Logic Pre-Counter for ADC clock,4-bit ADCON1[REFC] SOC Stands for Start of Convertion...
  • Page 167 SH79F7416 8.8.3 ADC Register The registers of ADC moldule are as follows: Function Name Register description ADC Clock Register Configuration of ADC clock, sample time Enable of ADC module, start a conversion, reference voltage selection, ADCON1 trigger mode and sources, interrupt flag...
  • Page 168 SH79F7416 ≥ 4. Configurate the register TADC to make sure ADC clock period t 40ns For Example: System Clock TADC[2:0] TS[3:0] Sample time Conversion time SYSCLK 0000 0.083*1=0.083us 0000 2*0.083=0.166us 14*0.083+0.166=1.328us 0000 0.083*1=0.083us 0111 8*0.083=0.664us 14*0.083+0.664=1.826us 0000 0.083*1=0.083us 1111 15*0.083=1.245us 14*0.083+1.245=2.407us...
  • Page 169 SH79F7416 Note;Once selected external VREF port as reference voltage(REFC = 1), P1.6 used as V input pin rather than AN8 input port.
  • Page 170 SH79F7416 Table 8.66 ADC Control Register2 92H,Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADCON2 GRP2 GRP1 GRP0 TGAP2 TGAP1 TGAP0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Reference source switch bit 0: Disable 1.20V Reference 1: Enable 1.20V Reference...
  • Page 171 SH79F7416 Table 8.67 Map control register 91H,Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SEQCON REG2 REG1 REG0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description ADC result left & right aligned selection bit 0: The 12-bits result stored in result register ADDxL/H(x = 0 - 7) are stored in left aligned.
  • Page 172 SH79F7416 Table 8.69 ADC Channel Configure Register 2 A6H,Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADCH2 CH14 CH13 CH12 CH11 CH10 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Channel Configuration bit 1: P3.7,P4.0,P5.1,P5.5 - P6.0 is ADC input port CH[13:8] 0: P3.7,P4.0,P5.1,P5.5 - P6.0 is I/O port...
  • Page 173 SH79F7416 Table 8.71 ADC Result Rgister x(x = 0 - 7) Left alignment mode: 96H,Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADDxL Reset Value (POR/WDT/LVR/PIN) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 97H,Bank0 ADDxH Reset Value (POR/WDT/LVR/PIN) Right alignment mode: 96H,Bank0...
  • Page 174 SH79F7416 The Approach for AD Conversion by software: Select referent voltage Set sequence, including the number of channels and analog input channel Enable ADC module ———— Set GO/DONE to1,start ADC conversion ———— Wait until GO/DONE = 0 or ADCIF = 1, if the ADC interrupt is enabled, the ADC interrupt will occur, user need clear ADCIF by software.
  • Page 175 SH79F7416 8.7.4 Sequence conversion mode The ADC sequence consist of one or more channels, the conversion of sequence is to convert the channels in the sequence one by one. It makes multiple signals to convert at the same time become possible in hardware. (the minmum...
  • Page 176 SH79F7416 ADDxH(97H) ADDxL(96H) ALR=0 ADDxH(97H) ADDxL(96H) ALR=1 Figure8.7-3Diagram of ADC conversion result storage mode...
  • Page 177 SH79F7416 GRP[2:0]=2 Result SEQCH0 =5 ADD0L/H SEQCH1= 2 ADD1L/H SEQCH2 = 8 ADD2L/H SEQCH3 = x ADD3L/H sequencer SEQCH6 = x ADD6L/H SEQCH7 = x ADD7L/H Figure8.8-4 The configuration of gap time between adjacent channel during sequence conversion During sequence conversion, the time between last channel finished conversion and next channel start sampling can be set by TGAP bit in ADCON2 register.
  • Page 178 SH79F7416 8.7.5 The configuration of ADC conversion time The ADC clock and sampling time can be set through ADT register. By setting the TADC[3:0] bits in the ADT can set the ADC clock. The TS[3:0] bits in the register ADT can be used to set the sampling time( t...
  • Page 179 SH79F7416 8.8 Low Power Detect (LPD) 8.8.1 Feature  Lowvoltage detection and interrupt generation  LPD detect voltage is selectable  LPD debounce time TLPD is 30-60µs Low Power Detect( LPD) function is used to monitor the supply voltage and generate an internal flag if the voltage decreasebelow the specified value.It is used to inform CPU whether the power is shut off or the battery is used out, so the...
  • Page 180 SH79F7416 Table 8.73 LPD Voltage Selection Register BBH,Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LPDSEL LPDS3 LPDS2 LPDS1 LPDS0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description LPD Voltage Select Bit 0000:2.4V 0001:2.55V 0010:2.7V 0011:2.85V 0100:3.00V 0101:3.15V 0110:3.30V 0111:3.45V...
  • Page 181 SH79F7416 8.9 Low Voltage Reset (LVR) 8.9.1 Features  Enabled by the code option and V is2.1V、2.8V、3.7V or 4.1V  LVR de-bounce timer T is about 30-60µs  When the supply voltage is lower than the set voltage V , an internal reset will be generated...
  • Page 182 OVL Reset To enhance the anti-noise ability, SH79F7416 built in Program Counter (PC) over range detect circuit, if program counter value is larger than flash romsize, or detect operation code equal to A5H which is not exist in 8051 instruction set, a OVL reset will be generate to reset CPU, and set WDOF bit.
  • Page 183  CRC generator polynomial adopt the CRC-CCITT Standard: X +1, high bit first. To improve the system reliability, the SH79F7416 has one CRC verification module built-in, CRC check code can be used to generate real-time code, using the generation polynomial: X +1, which adopt the CRC-CCITT Standard.Users can...
  • Page 184 SH79F7416 By setting the CRC_FAC bit, the CRC check area can be selected as the Main Block or EEPROM-like area. The related registers are described as follows: Table 8.77Flash Access Control Register A7H,Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1...
  • Page 185 (2) Reset signal (logic low on the RESET pin, WDT RESET if enabled, LVR REST if enabled), this will restore the clock to the CPU, the SUSLO register and the IDL bit in PCON register will be cleared by hardware, finally the SH79F7416 will be reset.
  • Page 186 SH79F7416 8.12.4 Register Table 8.80 Power Control Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PCON SMOD SSTAT Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description SMOD EUART Baud rate doubler SSTAT SCON[7:5] function select bit GF[1:0] General purpose flags for software use...
  • Page 187  Built-in oscillator warm-up counter to eliminate unstable state when oscillation startup SH79F7416 has a built-in power warm-up counter; it is designed to eliminate unstable state after power on or to do some internal initial operation such as read customer option etc.
  • Page 188 SH79F7416 8.14 Code Option OP_WDT: 0101: Disable WDT function other: Enable WDT function(default) OP_WDTPD: 0: Disable WDT function in Power-Down mode (default) 1: Enable WDT function in Power-Down mode OP_WMT: (unavailable for 32kHz crystal and Internal RC) 00: longest warm up time (default)
  • Page 189 SH79F7416 OP_EEPROMSIZE: 0000: 8 x 512Bytes(default) 0001: 7 x 512Bytes 0010: 6 x 512Bytes 0011: 5 x 512Bytes 0100: 4 x 512Bytes 0101: 3 x 512Bytes 0110: 2 x 512Bytes 0111: 1 x 512Bytes 1000: 0 bytes Other: 0 bytes OP_MODSW:...
  • Page 190 SH79F7416 9. Instruction Set ARITHMETIC OPERATIONS Opcode Description Code Byte Period ADD A,Rn Add register to accumulator 0x28-0x2F ADD A,direct Add direct byte to accumulator 0x25 ADD A,@Ri Add indirect RAM to accumulator 0x26-0x27 ADD A,#data Add immediate data to accumulator...
  • Page 191 SH79F7416 ORL direct,#data OR immediate data to direct byte 0x43 XRL A,Rn Exclusive OR register to accumulator 0x68-0x6F XRL A,direct Exclusive OR direct byte to accumulator 0x65 XRL A,@Ri Exclusive OR indirect RAM to accumulator 0x66-0x67 XRL A,#data Exclusive OR immediate data to accumulator...
  • Page 192 SH79F7416 XCHD A,@Ri Exchange low-order nibble indirect RAM with A 0xD6-0xD7 PROGRAM BRANCHES Opcode Description Code Byte Period ACALL addr11 Absolute subroutine call 0x11-0xF1 LCALL addr16 Long subroutine call 0x12 Return from subroutine 0x22 RETI Return from interrupt 0x32 AJMP addr11...
  • Page 193 SH79F7416 BOOLEAN MANIPULATION Opcode Description Code Byte Period CLR C Clear carry flag 0xC3 CLR bit Clear direct bit 0xC2 SETB C Set carry flag 0xD3 SETB bit Set direct bit 0xD2 CPL C Complement carry flag 0xB3 CPL bit...
  • Page 194 SH79F7416 10. Electrical Characteristics Absolute Maximum Ratings* *Comments DC Supply Voltage....-0.3V to +6.0V Stresses exceed those listed under “Absolute Maximum Input/Output Voltage... GND-0.3V to V +0.3V...
  • Page 195 SH79F7416 DC Electrical Characteristics (V = 2.0V - 5.5V, GND = 0V, T = +25°C, unless otherwise specified) Parameter Symbol Min. Max. Unit Condition Typ.∗ 32.768kHz or 2MHz ≤ f ≤24MHz Operating Voltage = 24MHz,V = 5.0V All output pins unload (including all digital input...
  • Page 196 SH79F7416 Select TTL input for 26 I/O ports (Note 4) (input high/low voltage window 0.4v) VDD = 4.5-5.5v Input low Voltage3 Select TTL input for 26 I/O ports (Note 4) (input 0.15 X high/low voltage window 0.4v) VDD = 2.0-5.5v Select TTL input for 26 I/O ports (Note 4) (input high/low voltage window 0.4v)
  • Page 197 SH79F7416 Build time of ADC internal VDD=2.7V~5.5V,T =25°C,VBGVoltage is set up µs reference source (0.1%) internal reference VDD=2.7V ~5.5V,T =25°C,VBGVoltage is set up µs channel switching stability (0.1%) time The external analog reference voltage VDD = 4.2V - 5.5V, switching channel sampling...
  • Page 198 SH79F7416 LVR enable LVR voltage1 LVR1 = 2.0V - 5.5V LVR enable LVR voltage2 LVR2 = 2.0V - 5.5V LVR enable LVR voltage3 LVR3 = 2.0V - 5.5V LVR enable LVR voltage4 LVR3 = 2.0V - 5.5V LVRVoltage detection hysteresis...
  • Page 199 SH79F7416 11. Ordering Information Part No. Package SH79F7416S/064SR LQFP64 7*7...
  • Page 200 SH79F7416 12. Package Information LQFP64 Outline Dimensions (BODY SIZE: 7 X 7) unit: inches/mm θ2 See Detail F DETAIL F Dimensions in inches Dimensions in mm Symbol 0.063 1.600 0.002 0.006 0.050 0.150 0.053 0.057 1.350 1.450 0.272 0.280 6.900 7.100...
  • Page 201 SH79F7416 13. Specification Change Record Record Version Data Original 2018-05-01...
  • Page 202 SH79F7416 Directory 1. FEATURES ..................................1 2. GENERAL DESCRIPTION ..............................1 3. BLOCK DIAGRAM ................................2 4. PIN CONFIGRATION ................................3 4.1 LQFP64 ....................................3 ACKAGE 5. PIN FUNCTION AND PIN DESCRIPTION ........................... 8 5.1 P ......................................8 UNCTION ............................错误!未定义书签。...
  • Page 203 SH79F7416 7.10.4 Interrupt Vector ..................................91 7.10.5 Interrupt Priority ..................................91 7.10.6 Interrupt Handling ..................................92 7.10.7 Interrupt Response Timing ................................. 92 7.10.8 External Interrupt Input ................................93 7.10.9 Interrupt Summary ..................................95 8. ENHANCED FEATURES ..............................96 8.1 LCD ......................................
  • Page 204 SH79F7416 8.12.3 Power-Down Mode ................................. 185 8.12.4 Register ....................................186 8.13 W ..................................... 187 IMER 8.13.1 Featueres ....................................187 8.14 C ....................................188 PTION 9. INSTRUCTION SET ................................. 190 10. ELECTRICAL CHARACTERISTICS..........................194 11. ORDERING INFORMATION ............................199 12. PRODUCT NAMING RULES ......................... 错误!未定义书签。...

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