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Sino Wealth SH69P55A Manual

Otp/mask 8k 4-bit micro-controller with lcd driver & 10-bit sar adc

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Features
SH6610D-Based Single-Chip 4-bit Micro-Controller With
LCD Driver & 10-bit SAR ADC
OTP ROM: 8K X 16 bits (SH69P55A)
MASK ROM: 8K X 16 bits (SH69K55A)
RAM: 515X 4 bits
- 99 System Control Register
- 376 Data Memory
- 40 LCD RAM
Operation Voltage: 2.4V - 5.5V
- f
= 30k- 4MHz, V
OSC
- f
= 30k - 8MHz, V
OSC
42 CMOS Bi-directional I/O Pins (Including one
open-drain output PortC.3)
Built-in Pull-high Resistor For PORTA - PORTK
8-Level Stack (Including Interrupts)
Two 8-bit and One 16-bit Auto Re-loaded Timer/Counter
LCD Driver:
- 16 SEG X 8 COM (1/8 Duty, 1/4 Bias)
- 18 SEG X 6 COM (1/6 Duty, 1/3 Bias)
- 20 SEG X 4 COM (1/4 Duty, 1/3 Bias)
LED Driver:
- 8 SEG X 6 COM (1/6 Duty)
- 8 SEG X 5 COM (1/5 Duty)
- 8 SEG X 4 COM (1/4 Duty)
Powerful Interrupt Sources:
- Timer0 Interrupt
- Timer1 Interrupt
- Timer2 Interrupt
- External Interrupts (PORTB & PORTC Falling Edge
Interrupts, A/D Interrupt, Key Scan Interrupt)
General Description
SH69P55A/69K55A is a single-chip 4-bit micro-controller. This device integrates a SH6610D CPU core, RAM, ROM, timer,
LCD/LED driver, I/O ports, watchdog timer, 10 channels 10-bit resolution ADC, low voltage reset, automatic key scan, PLL
and Zero Cross Detect function. The SH69P55A/69K55A is suitable for washing machine and micro-wave oven etc.
application.
= 2.4V - 5.5V
DD
= 4.5V - 5.5V
DD
OTP/MASK 8K 4-Bit Micro-controller
With LCD Driver & 10-bit SAR ADC
Oscillator (Code Option)
- Crystal Oscillator: 32.768kHz, 400kHz - 8MHz
- Ceramic Resonator: 400kHz - 8MHz
- External RC Oscillator: 400kHz - 8MHz
- Internal RC Oscillator: 4MHz ±5%
One Built-in PLL Oscillator (1, 2, 4, 8MHz)
Instruction Cycle Time (4/f
10 Channels 10-Bit Resolution Analog/Digital Converter
(ADC)
2 Channel Tone Generators
Built-in Automatic Key Scanner
Zero Cross Detect Function for AC Power Line
Read ROM Data Table Function (RDT)
One Channel 8+2Bit PWM Output
Reset
- Built-in Watchdog Timer (WDT) [(Code Option)]
- Built-in Power-on Reset (POR)
- Built-in Low Voltage Reset (LVR) [(Code Option)]
Two-Level Low Voltage Reset (LVR) (Code Option)
Two Low Power Operation Modes: HALT and STOP
OTP Type/Code Protection (SH69P55A)
MASK Type (SH69K55A)
28-pin SOP package; 44-pin QFP package; 32-pin DIP
package
1
SH69P55A/K55A
)
OSC
V2.2

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Summary of Contents for Sino Wealth SH69P55A

  • Page 1 Interrupts, A/D Interrupt, Key Scan Interrupt) General Description SH69P55A/69K55A is a single-chip 4-bit micro-controller. This device integrates a SH6610D CPU core, RAM, ROM, timer, LCD/LED driver, I/O ports, watchdog timer, 10 channels 10-bit resolution ADC, low voltage reset, automatic key scan, PLL and Zero Cross Detect function.
  • Page 2 SH69P55A/K55A Pin Configuration (44 Pin) 32 31 27 26 25 24 PORTI.0/SEG9 PORTD.0/COM4/LED_C4/KEY_04 PORTF.3/SEG8/LED_S8 PORTD.1/COM3/LED_C3/KEY_03 PORTF.2/SEG7/LED_S7 PORTD.2/COM2/LED_C2/KEY_02 PORTF.1/SEG6/LED_S6 PORTD.3/COM1/LED_C1/KEY_01 SH69P55A/69K55A PORTF.0/SEG5/LED_S5/KEY_I5 PORTB.0/AN0 /44 Pin PORTA.3/SEG4/LED_S4/KEY_I4 PORTB.1/AN1 PORTA.2/SEG3/LED_S3/KEY_I3 PORTB.2/AN2 PORTB.3/AN3 PORTA.1/SEG2/LED_S2/KEY_I2 PORTG.0/PWM PORTA.0/SEG1/LED_S1/KEY_I1 PORTG.1/TONE/AN9 PORTG.2/V...
  • Page 3 SH69P55A/K55A Pin Configuration (32 Pin & 28 Pin) PORTB.0/AN0 PORTD.3/COM1/LED_C1/KEY_O1 PORTD.2/COM2/LED_C2/KEY_O2 PORTB.1/AN1 PORTD.1/COM3/LED_C3/KEY_O3 PORTB.2/AN2 PORTD.0/COM4/LED_C4/KEY_O4 PORTB.3/AN3 PORTE.3/COM5/SEG20/LED_C5 PORTG.0/PWM PORTG.1/TONE/AN9 PORTE.2/COM6/SEG19/LED_C6 PORTG.2/VREF/T0 PORTE.1/COM7/SEG18 PORTE.0/COM8/SEG17 PORTG.3/T2/AN8 PORTC.0/PLL_C PORTH.3/SEG16 PORTH.2/SEG15 OSCO/PORTC.1 PORTF.3/SEG8/LED_S8 OSCI/PORTC.2 PORTF.2/SEG7/LED_S7 RESET/PORTC.3 PORTF.1/SEG6/LED_S6 PORTF.0/SEG5/KEY_I5/LED_S5 PORTA.3/SEG4/KEY_I4/LED_S4 PORTA.0/SEG1/LED_S1/KEY_I1 PORTA.2/SEG3/KEY_I3/LED_S3 PORTA.1/SEG2/LED_S2/KEY_I2 PORTB.3/AN3 PORTB.2/AN2 PO RTG .0/PW M...
  • Page 4: Block Diagram

    SH69P55A/K55A Block Diagram OSCI/PORTC.2 WDT RC OSCO/PORTC.1 Reset Circuit Oscillator RESET/PORTC.3 PORTC.0/PLL_C PORTC.2 - 0 Watch Dog Timer PORTC.3 PORTA.3 - 0/SEG4 - SEG1/ PORTA (4-bit) LED_S4 - LED_S1/ 99 X 4 Bits KEY_I4 - KEY_I1 System Register 10ch X 10bits...
  • Page 5 SH69P55A/K55A Pin Descriptions Pin No. Pad No. Pin Name Description 44 pin 28 pin 32 pin PORTG.2 Bit programmable I/O Timer0 Clock/Counter input pin. (Schmitt trigger input) External ADC V input PORTG.3 Bit programmable I/O Timer2 Clock/Counter input pin. (Schmitt trigger input)
  • Page 6 32 pin 14, 15 Programming Power supply (+5.5V) Programming high voltage Power supply (+11V) RESET Ground OSCI Programming Clock input pin PORTA.0 Programming Data pin *: Only SH69P55A has the OTP Program Mode, SH69K55A has not the OTP Program Mode.
  • Page 7: Functional Descriptions

    SH69P55A/K55A Functional Descriptions 1. CPU The CPU contains the following functional blocks: Program 1.4. Table Branch Register (TBR) Counter (PC), Arithmetic Logic Unit (ALU), Carry Flag (CY), Table Data can be stored in program memory and can be Accumulator, Table Branch Register, Data Pointer (INX, referenced by using Table Branch (TJMP) and Return DPH, DPM, and DPL) and Stacks.
  • Page 8 SH69P55A/K55A 2.2. Configuration of System Register: Address Bit 3 Bit 2 Bit 1 Bit 0 Remarks IET0 IET1 IET2 IEEX R/W Interrupt enable flags register IRQT0 IRQT1 IRQT2 IRQEX R/W Interrupt request flags register Bit2-0: Timer0 Mode register T0M.2 T0M.1 T0M.0...
  • Page 9 SH69P55A/K55A Configuration of System Register (continued1): Address Bit 3 Bit 2 Bit 1 Bit 0 Remarks Bit0: PWM output enable control register PWMS TCK1 TCK0 PWM_EN R/W Bit2-1: PWM clock control register Bit3: PWM output mode of duty cycle control register PP.3...
  • Page 10 SH69P55A/K55A Configuration of System Register (continued2): Address Bit 3 Bit 2 Bit 1 Bit 0 Remarks $390 PI.3 PI.2 PI.1 PI.0 R/W PORTI data register $391 PJ.3 PJ.2 PJ.1 PJ.0 R/W PORTJ data register $392 PK.1 PK.0 R/W PORTK data register $393 PGCR.3...
  • Page 11 SH69P55A/K55A 3. ROM The ROM can address 8192 X 16 bits of program area from $000 to $1FFF. 3.1. Vector Address Area ($000 to $004) The program is sequentially executed. There is an area address $000 through $004 that is reserved for a special interrupt service routine such as starting vector address.
  • Page 12 SH69P55A/K55A 4. Initial State 4.1. System Register State: Power On Reset WDT Reset Address Bit 3 Bit 2 Bit 1 Bit 0 /Pin Reset /Low Voltage Reset IET0 IET1 IET2 IEEX 0000 0000 IRQT0 IRQT1 IRQT2 IRQEX 0000 0000 T0M.2 T0M.1...
  • Page 13 SH69P55A/K55A System Register State (Continued1): Power On Reset WDT Reset Address Bit 3 Bit 2 Bit 1 Bit 0 /Pin Reset /Low Voltage Reset PDF.1 PDF.0 --xx --uu PD.3 PD.2 PD.1 PD.0 xxxx uuuu PD.7 PD.6 PD.5 PD.4 xxxx uuuu...
  • Page 14 SH69P55A/K55A System Register State (Continued2): Power On Reset WDT Reset Address Bit 3 Bit 2 Bit 1 Bit 0 /Pin Reset /Low Voltage Reset $399 PPBCR.3 PPBCR.2 PPBCR.1 PPBCR.0 0000 0000 $39A PPCCR.2 PPCCR.1 PPCCR.0 -000 -000 $39B PPDCR.3 PPDCR.2 PPDCR.1 PPDCR.0...
  • Page 15 SH69P55A/K55A 5. System Clock and Oscillator SH69P55A/69K55A has one clock source, which is determined in Code options. The oscillator generates the basic clock pulses that provide the system clock to supply CPU and on-chip peripherals. System clock f 5.1. Instruction Cycle Time: (1) 4/32.768kHz ( ≈...
  • Page 16 5.3. Control of Phase Locked Loop Clock Source (PLL) A phase locked loop (PLL) is built in SH69P55A/69K55A, which can provide up to 8MHz clock source when the 32.768kHz oscillator is selected. PLL control register can decide whether PLL enable or disable. When PLL is enabled, PORTC.0 is shared as PLL capacitor connecting port, which is connected with a RC network.
  • Page 17 SH69P55A/K55A 5.4. Capacitor Selection for Oscillator Ceramic Resonators Recommend Type Manufacturer Frequency ZTB 455KHz Vectron International 455kHz 47 - 100pF 47 - 100pF ZT 455E Shenzhen DGJB Electronic Co.,Ltd. ZTT 3.580M Vectron International 3.58MHz ZT 3.58M* Shenzhen DGJB Electronic Co.,Ltd.
  • Page 18 6. I/O Port The SH69P55A/69K55A provides 42 bi-directional I/O ports including one open-drain output. The PORT data is put in register $08 - $0D and $38E - $392. The PORT control register ($18 - $1D and $393 - $397) controls the PORT as input or output.
  • Page 19 SH69P55A/K55A System Register $398 - $3A2: Port Pull-high Control Register (PPCR) Address Bit3 Bit2 Bit1 Bit0 Remarks $398 PPACR.3 PPACR.2 PPACR.1 PPACR.0 PORTA pull high control register $399 PPBCR.3 PPBCR.2 PPBCR.1 PPBCR.0 PORTB pull high control register $39A PPCCR.2 PPCCR.1 PPCCR.0...
  • Page 20 PORTC.0 can be shared with PLL_C (code option), if PLL is enabled, a RC network must be connected with this port. The OSCO pin can be shared with PORTC.1 if the SH69P55A/69K55A uses the external clock or the RC oscillator as the system oscillation.
  • Page 21 SH69P55A/K55A Port Interrupt The PORTB and PORTC are used as port interrupt sources. Since PORTB and PORTC are bit programmable I/Os, only when the PORTB and PORTC are selected as normal I/O input, the voltage transition from V to GND applying to the digital input port can generate a port interrupt.
  • Page 22 SH69P55A/K55A 7. Timer SH69P55A/69K55A has three timers: two 8-bit timers The low-order digit should be written first, and then the (Timer0, Timer1) and one 16-bit timer (Timer2). high-order digit. The timer/counter is automatically loaded with the contents of the load register when the high order digit is The 8-bit timer/counter has the following features: written or the counter counts overflow from $FF to $00.
  • Page 23 SH69P55A/K55A System SYNC clock 8-BIT Prescaler 32.768 kHz COUNTER 2.048 kHz TM.2 TM.1 TM.0 Also the clock source of Timer0 and Timer1 is set in timer control registers, as shown blow: Systems Register: Address Bit 3 Bit 2 Bit 1...
  • Page 24 SH69P55A/K55A 7.4. Timer2 Timer2 is a 16-bit timer and it has the following features: The low-order digit should be written first, and then the high-order digit. The timer counter is automatically loaded with - 16-bit up-counting timer/counter. the contents of the load register when the high order digit is - Automatic re-load counter.
  • Page 25 SH69P55A/K55A (1) Timer Mode In this mode, Timer2 is performed using the internal system clock. The contents of the Timer2 load register ($384 - $387) are loaded into the up-counter while the highest nibble ($387) has been written. The up-counter will start counting if the Timer2 control register ($27) T2GO (bit3) is set to 1.
  • Page 26 SH69P55A/K55A (3) External Trigger Timer Mode In this mode, the counting is triggered by an external signal via T2 pin (shared with PORTG3). Either the rising or falling edge can be selected by setting the Timer2 pre-scaler register ($15) T2E (bit3). But the clock source of the up-counter is the internal system clock.
  • Page 27 SH69P55A/K55A Count start Count start Internal clock Up-counter FF9C FF9D FF9E FFFF FF9C FF9D FF9E FF9F T2GO Timer2 INT Trigger Start (DEC = 0) Count relooad Count start Count start Internal clock Up-counter F060 F060 F061 F062 M - 1...
  • Page 28 SH69P55A/K55A Where M (pre-scaler value for Timer2 internal clock) = 2 or 2 But, in order to correctly get the pulse measurement value in programming, a sufficient wait period must be needed for the relevant Timer2 interrupt subroutine program. So, if the Timer2 control register ($27) DEC (bit2) is 0, the Timer2 is in the one-edge capture mode. The limitation is applied...
  • Page 29 SH69P55A/K55A 8. LCD Driver The LCD driver contains a controller, a voltage generator, 4-8 common driver pins/pads and 16-20 segment driver pins/pads. There are three different driving programmable modes: 1/4 duty & 1/3 bias, 1/6 duty & 1/3 bias and 1/8 duty & 1/4 bias. The driving mode is controlled by the system register $29.
  • Page 30 SH69P55A/K55A COM1 COM1 FRAME LCD Output Frame The following table is the recommended setting. 8COM 6COM 4COM OPTION (Hz) (Hz) (Hz) 4.0001M 2.0001M 1.0001M 500k 32.768k 2. If the $3C1 = 0000B. The LCD clock is divided from OSC, so LCD frame frequency will change in proportion to the variation of OSC frequency in spite of OSC type and the FOSC Code Option (See Page 56 for detail).
  • Page 31 SH69P55A/K55A 3. SH69P55A/69K55A both has LCD driver and LED driver, and only one is valid at one time. If LEDEN = 1, the LCD driver is disabled; if LEDEN = 0, the LED driver is disabled. SEG Configuration Register: $2E...
  • Page 32 SH69P55A/K55A Configuration of LCD RAM Area: (LCD 1/6 duty, 1/3 bias, COM uses COM1 - 6, SEG uses SEG1 - 18) Bit3 Bit2 Bit1 Bit0 Bit3 Bit2 Bit1 Bit0 Address Address COM4 COM3 COM2 COM1 COM6 COM5 $300 SEG1 SEG1...
  • Page 33 SH69P55A/K55A LCD Power LCD ON com1 common driver & Power scan Supply input com8 Control Circuit seg1 segment driver & scan output seg20 SEG Configuration Register: $2E Address Bit 3 Bit 2 Bit 1 Bit 0 Remarks RLCD Bit3: Set LCD bias resistor register...
  • Page 34 SH69P55A/K55A LCD Waveform 1/4 duty, 1/3 bias LCD Waveform COM1 COM2 COM3 COM4...
  • Page 35 SH69P55A/K55A 1/6 duty, 1/3 bias LCD Waveform COM1 COM2 COM3 COM4...
  • Page 36 SH69P55A/K55A 1/8 duty, 1/4 bias LCD Waveform COM1 COM2 COM3...
  • Page 37 COM1 - 6 for LED display Note: SH69P55A/69K55A both has LCD driver and LED driver, and just only one is valid at one time. If LEDEN = 1, the LCD driver is disabled; if LEDEN = 0, the LED driver is disabled.
  • Page 38 SH69P55A/K55A Configuration of LED RAM Configuration of LCD RAM Area: (LED 1/4 duty, COM1 - 4, SEG1 - 8) Bit3 Bit2 Bit1 Bit0 Bit3 Bit2 Bit1 Bit0 Address Address COM4 COM3 COM2 COM1 COM4 COM3 COM2 COM1 $300 SEG1 SEG1...
  • Page 39 10. Key Scan There is a key scanner built in the SH69P55A/69K55A, which can automatic detect the key-press. It includes four outputs (KEY_O1 - 4, shared with COM1 - COM4), five inputs (KEY_I5 - 1, shared with SEG1 - SEG5), and it can detect 20 individual keys.
  • Page 40 SH69P55A/K55A Note: 1. If key scan function is shared with LCD function, the LCD function must be selected as 4com, 6com or 8com. It is important that if the LCD function is selected as 4com, PORTD must be selected as COM port (the LCD control register $29 bit2 - 0 can be selected as ‘100’, ‘110’...
  • Page 41 SH69P55A/K55A An Example of the program flow of customer applications Start KEYIF=1? Clear KEYIF KEYNUM0=1? Key pressed KEYNUM1=1? Single key pressed Store KEYC and KEYL Identify the pressed key Other Routines...
  • Page 42 SH69P55A/K55A 11. Analog/Digital Converter (ADC) The 10 channels and 10-bit resolution A/D converter are implemented in this micro-controller. The ADC control registers can be used to define the A/D channel number, select analog channel, reference voltage and conversion clock, start A/D conversion, and set the end of A/D conversion flag. The A/D conversion result register byte is read-only.
  • Page 43 SH69P55A/K55A ADC Channels Control Remarks ADC Channel AN0 ADC Channel AN1 ADC Channel AN2 ADC Channel AN3 ADC Channel AN4 ADC Channel AN5 ADC Channel AN6 ADC Channel AN7 ADC Channel AN8 ADC Channel AN9...
  • Page 44 SH69P55A/K55A Systems Register for ADC Data: Address Bit 3 Bit 2 Bit 1 Bit 0 Remarks $3AD ADC data low nibble register $3AE ADC data middle nibble register $3AF ADC data high nibble register Systems Register: Address Bit 3 Bit 2...
  • Page 45 SH69P55A/K55A Application Notes: When the External reference voltage is selected, the SH69P55A/69K55A ADC needs a little current, which is input into SH69P55A/69K55A from the V pin to maintain the A/D normal running. The methods that show in figure 1 and figure 2 to set up the External reference voltage are recommended.
  • Page 46 12. Pulse Width Modulation (PWM) The SH69P55A/69K55A consists of one 8+2 bit PWM module. The PWM module can provide the pulse width modulation waveform with the period and the duty being controlled, individually. The PWMC is used to control the PWM module operation with proper clocks.
  • Page 47 SH69P55A/K55A System Register $24: PWM Duty Fine Control Register (PWMDF) Address Bit 3 Bit 2 Bit 1 Bit 0 Remarks PDF.1 PDF.0 R/W Bit1-0: PWM duty f fine-tune bits register R/W Duty cycle = [PD.7, PD0] in Period cycle0, 1, 2, 3 Duty cycle = [PD.7, PD0]+1 in Period cycle0...
  • Page 48 SH69P55A/K55A Note: - If the I/O port (PORTG.0) is selected as the PWM output, the I/O functions and pull-high resistor are disabled. - The PWM could keep on working in the HALT mode, and would stop automatic when the “STOP” instruction is executed.
  • Page 49 SH69P55A/K55A 13. Low Voltage Reset (LVR) The LVR function is to monitor the supply voltage and generate an internal reset in the device. It is typically used in AC line applications or large battery where heavy loads may be switched in and cause the device voltage to temporarily fall below the specified operating minimum.
  • Page 50 SH69P55A/K55A 15. Dual Tone SH69P55A/69K55A has two 12-bit tone generators. The tone generators generate the specific frequency of tone with square wave. Tone Generator Control Register: Address Bit 3 Bit 2 Bit 1 Bit 0 Remarks $3A3 TG1.3 TG1.2 TG1.1 TG1.0...
  • Page 51 SH69P55A/K55A Music Table 1 Following is the music scale reference table for the Tone Generator channel 1 (or channel 2) under OSX = 4MHz. TGCR TGCR Ideal Real Ideal Real Note (TGx.11 - TGx.0) Error% Note (TGx.11 - TGx.0) Error% freq.
  • Page 52 SH69P55A/K55A Music Table 2 Following is the music scale reference table for the Tone Generator channel 1(or channel 2) under OSX = 2MHz. TGCR TGCR Ideal Real Ideal Real Note (TGx.11 - TGx.0) Error% Note (TGx.11 - TGx.0) Error% freq.
  • Page 53 SH69P55A/K55A 16. Watch Dog Timer (WDT) Watch dog timer is a down-count counter, and its clock source is an independent built-in RC oscillator, so that the WDT will always run even in the STOP mode. The watchdog timer automatically generates a device reset when it overflows. It can be enabled or disabled permanently by using the code option.
  • Page 54 SH69P55A/K55A 17. Interrupt Four interrupt sources are available on SH69P55A/69K55A: - Timer0 interrupt - Timer1 interrupt - Timer2 interrupt - External interrupts (include PORTB, PORTC interrupts (Falling edge), AD interrupt, Key scan interrupt) Interrupt Control Bits and Interrupt Service The interrupt control flags are mapped on $00 and $01 of the system register. They can be accessed by the program. Those flags are cleared to “0”...
  • Page 55 SH69P55A/K55A PORTB, PORTC falling Edge Interrupt The PORTB and PORTC are used as external port interrupt sources. Since PORTB and PORTC are bit programmable I/Os, only when the PORTB and PORTC are selected as normal I/O input, the voltage transition from VDD to GND applying to the digital input port can generate a port interrupt.
  • Page 56 SH69P55A/K55A PB.3 - 0 Falling Edge Request Flag Detector (PBIF.3 - 0) PBIEN.3 - 0 PBCR.3 - 0 Falling Edge PC.3 - 0 Request Flag Detector (PCIF.3 - 0) PCIEN.3 - 0 PCCR.3 - 0 IRQEX Interrupt CPU ADC Completion...
  • Page 57 (Timer0, Timer1, Timer2, ADC, PWM and watchdog timer) will keep status. After the execution of STOP instruction, SH69P55A/69K55A will enter the STOP mode. The whole chip (If the OSC is not 32.768kHz, the oscillator will stop in STOP mode. If the OSC is 32.768kHz, the oscillator ON/OFF in STOP mode will be controlled by the register $23) will stop operating without watchdog timer if it is enabled.
  • Page 58 SH69P55A/K55A 20. Code Option (a) Oscillator Type: OSC[2:0]: 000 = Internal RC Oscillator (Select OSCO pin as PORTC1 and OSCI pin as PORTC2 for normal I/O ports.) (default) 001 = External RC Oscillator (400kHz - 8MHz) (Select OSCO pin as PORTC1 for a normal I/O port.)
  • Page 59: Instruction Set

    SH69P55A/K55A Instruction Set All instructions are one cycle and one-word instructions. The characteristic is memory-oriented operation. 1. Arithmetic and Logical Instruction 1.1. Accumulator Type Mnemonic Instruction Code Function Flag Change ← Mx + AC + CY X (, B) 00000 0bbb xxx xxxx AC, Mx ←...
  • Page 60 SH69P55A/K55A 2. Transfer Instruction Mnemonic Instruction Code Function Flag Change ← Mx X (, B) 00111 0bbb xxx xxxx ← AC X (, B) 00111 1bbb xxx xxxx AC, Mx ← I X, I 01111 iiii xxx xxxx 3. Control Instruction...
  • Page 61 SH69P55A/K55A In System Programming Note for OTP The In System Programming technology is valid for OTP chip (SH69P55A). The Programming Interface of the OTP chip must be set on the user’s application PCB, and users can assemble all components including the OTP chip in the application PCB before programming the OTP chip. Of course, it’s accessible bonding OTP chip only first, and then programming code and finally assembling other components.
  • Page 62: Electrical Characteristics

    SH69P55A/K55A Electrical Characteristics Absolute Maximum Ratings* *Comments DC Supply Voltage ....-0.3V to +7.0V Stresses above those listed under " Absolute Maximum Ratings "...
  • Page 63 SH69P55A/K55A DC Electrical Characteristics (Continued) = 2.4 - 5.5V GND = 0V, T = -40°C to +85°C, unless otherwise specified.) Parameter Symbol Min. Typ. Max. Unit Condition Output High Voltage - 0.7 V I/O ports, I = -10mA (V = 5.0V) - GND + 0.6 V I/O ports, I...
  • Page 64 SH69P55A/K55A Timing Waveform (a) System Clock Timing Waveform System Clock (b) T0/T2 Input Waveform IPW(L) IPW(H) T0/T2 input signal...
  • Page 65 SH69P55A/K55A RC Oscillator Characteristics Graphs (for reference only) (a) External RC Oscillator Resistor vs. Frequency: Typical RC Oscillator Resistor vs. Frequency (V = 5V) Typical RC Oscillator Resistance: Rosc (kΩ) (b) External RC Oscillator Operation Voltage vs. Frequency: External RC Oscillator Operation Voltage vs. Frequency (Rosc = 7.5kΩ)
  • Page 66 SH69P55A/K55A Application Circuit (for reference only) AP1: (1) Operating voltage: 5.0V (2) Oscillator: Crystal 8MHz (3) PORTA, PORTF: LED SEG1-8. PORTD, PORTE.3, PORTE.2: LEDCOM1-6. PORTA, PORTD are shared as keyscan ports. PORTG.1 is used as tone output. PORTI.0 is used as Zero Cross Detect function for AC Power line.
  • Page 67 SH69P55A/K55A AP2: (1) Operating voltage: 5.0V (2) Oscillator: Crystal 8MHz (3) PORTA, PORTF: LCD SEG1-8. PORTD: LCD COM1-4. PORTA, PORTD are shared as keyscan ports. PORTG.1 is used as tone output. PORTK.0 is used as Zero Cross Detect function for AC Power line.
  • Page 68 SH69P55A/K55A Ordering Information Part No. Package SH69P55AF/SH69K55AF 44 QFP SH69P55AM/SH69K55AM 28 SOP SH69P55A/SH69K55A 32 DIP...
  • Page 69: Package Information

    SH69P55A/K55A Package Information unit: inch/mm QFP 44 Outline Dimensions θ See Detail F DETAIL F Seating Plane Symbol Dimensions in inches Dimensions in mm 0.106 Max. 2.70 Max. 0.01 Min.0.02Max. 0.25 Min.0.50Max. 0.079+0.008 2.00+0.2 -0.004 -0.1 0.012 Typ. 0.30 Typ.
  • Page 70 SH69P55A/K55A unit: inches/mm SOP (W.B.) 28L Outline Dimensions Detail F See Detail F Seating Plane Symbol Dimensions in inches Dimensions in mm 0.110 Max. 2.79 Max. 0.004 Min. 0.10 Min. 0.093 ± 0.005 2.36 ± 0.13 0.016 +0.004 0.41 +0.10 -0.002...
  • Page 71 SH69P55A/K55A unit: inches/mm P-DIP 32L Outline Dimensions Base Plane Seating Plane α Symbol Dimensions in inches Dimensions in mm 0.210 Max. 5.33 Max. 0.010 Min. 0.25 Min. 0.155 ± 0.010 3.94 ± 0.25 0.018+0.004 0.46+0.10 -0.002 -0.05 0.050+0.004 1.27+0.10 -0.002 -0.05...
  • Page 72: Data Sheet Revision History

    SH69P55A/K55A Data Sheet Revision History Version Content Date Add keyscan description Jan. 2011 Ordering information updated Dec. 2008 Ordering information updated Mar. 2008 Original Jan. 2008...

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Sh69k55a