Sino Wealth SH79F3283 Manual

Enhanced 8051 microcontroller with 12bit adc
Table of Contents

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1. Features

8bits micro-controller with Pipe-line structured 8051
compatible instruction set
Flash ROM: 32K Bytes
RAM: internal 256 Bytes, external 1280 Bytes, LCD
RAM: 28 Bytes
EEPROM-like: 1024 Bytes
Operation Voltage:
f
= 32.768kHz - 16MHz, V
OSC
Oscillator (code option)
- Crystal oscillator: 32.768kHz
- Crystal oscillator: 2MHz - 16MHz
- Ceramic oscillator: 2MHz - 16MHz
- Internal RC: 12MHz (±2%)/128K
46/42/30 CMOS bi-directional I/O pins
Built-in pull-up resistor for input pin
Four 16-bit timer/counters: T2, T3, T4 and T5
One 12-bit PWM
One 8-bit PWM
Powerful interrupt sources:
- Timer2, 3, 4, 5
- INT0, 1, 2, 3
- INT40 - INT47
- ADC, EUART, SCM, LPD
- PWM, SPI
EUART0, EUART1 (No EUART1 in 32 PIN package)
SPI Interface (Master/Slave Mode)

2. General Description

The SH79F3283 is a high performance 8051 compatible micro-controller, regard to its build-in Pipe-line instruction fetch
structure, that helps the SH79F3283 can perform more fast operation speed and higher calculation performance, if compare
SH79F3283 with standard 8051 at same clock speed.
The SH79F3283 retains most features of the standard 8051. These features include internal 256 bytes RAM, UART and INT0,
INT1, INT2 and INT3. In addition, the SH79F3283 provides external 1280 bytes RAM, Four 16-bit timer/counters T2-T5. It also
contains 32K bytes Flash memory block both for program and data.
Also the ADC, EUART, SPI, LCD Driver, PWM timer and CRC module functions are incorporated in SH79F3283.
For high reliability and low power consumption, the SH79F3283 builds in Watchdog Timer, Low Voltage Reset function and
SCM function. And SH79F3283 also supports two power saving modes to reduce power consumption.
Enhanced 8051 Microcontroller with 12bit ADC
= 2.0V - 5.5V
DD
Buzzer
9 channels 12-bits Analog Digital Converter
(ADC), with comparator function built-in
LED driver:
- 3-8 X 8 dots (1/3 - 1/8 duty)
LCD driver:
- 8 X 24 dots (1/8 duty, 1/4 bias)
- 6 X 26 dots (1/6 duty, 1/4 or 1/3 bias)
- 5 X 27 dots (1/5 duty, 1/3 bias)
- 4 X 28 dots (1/4 duty, 1/3 bias)
Low Voltage Reset (LVR) function (enabled by
code option)
- LVR voltage level 1: 4.1V
- LVR voltage level 2: 3.7V
- LVR voltage level 3: 2.8V
- LVR voltage level 4: 2.1V
CRC verify module built-in, check size is optional
Support SWE simulation, write and read
CPU Machine cycle: 1 oscillator clock
Watch Dog Timer (WDT)
Warm-up Timer
Support Low power operation modes:
- Idle Mode
- Power-Down Mode
Flash Type
Package: TQFP48/LQFP44/LQFP32
1
SH79F3283
V2.0

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Summary of Contents for Sino Wealth SH79F3283

  • Page 1: Features

    SH79F3283 with standard 8051 at same clock speed. The SH79F3283 retains most features of the standard 8051. These features include internal 256 bytes RAM, UART and INT0, INT1, INT2 and INT3. In addition, the SH79F3283 provides external 1280 bytes RAM, Four 16-bit timer/counters T2-T5. It also contains 32K bytes Flash memory block both for program and data.
  • Page 2: Block Diagram

    SH79F3283 3. Block Diagram Reset circuit Power Pipelined 8051 architecture Watch Dog 32K Bytes Flash ROM Port 5 Configuration I/Os P5.0~P5.5 Internal 256 Bytes External 1280Bytes (Exclude System Port 4 Register) Configuration I/Os P4.0~ P4.7 Port 3 Timer2 (16bit) Configuration I/Os Timer3 (16bit) P3.0~ P3.7...
  • Page 3: Pin Configuration

    SH79F3283 4. Pin Configuration 4.1 TQFP48 30 29 27 26 LED_S7/SEG7/P1.6 P3.6/COM7/LED_C7/SGE26/AN6 P3.7/COM8/LED_C8/SGE25/AN7 LED_S8/SEG8/P1.7 RXD0/SEG9/P2.0 P4.0/INT40/AN0 TXD0/SEG10/P2.1 P4.1/INT41/AN1 MOSI/RXD1/SEG11/P2.2 P4.2/INT42/AN2 MISO/TXD1/SEG12/P2.3 P4.3/INT43/AN3 SH79F3283U SCK/SEG13/P2.4 P4.4/AN8/AVREF FLT/SS/SEG14/P2.5 P4.5/SEG24/PWM1 PWM01C/SEG15/P2.6 P4.6/SEG23 PWM0C/SEG16/P2.7 P4.7/SEG22 PWM01B/SEG17/P0.0 P5.5/SEG21 PWM0B/SEG18/P0.1 P5.4/SEG20 Pin Configuration Diagram TQFP48 Note: The out most pin function has the highest priority, and the inner most pin function has the lowest priority (Refer to Pin Configuration Diagram.
  • Page 4: Lqfp44

    SH79F3283 4.2 LQFP44 32 31 27 26 LED_S8/SEG8/P1.7 P3.4/COM5/LED_C5/SEG28/AN4 P3.5/COM6/LED_C6/SGE27/AN5 RXD0/SEG9/P2.0 P3.6/COM7/LED_C7/SGE26/AN6 TXD0/SEG10/P2.1 P3.7/COM8/LED_C8/SGE25/AN7 MOSI/RXD1/SEG11/P2.2 P4.0/INT40/AN0 MISO/TXD1/SEG12/P2.3 SH79F3283P SCK/SEG13/P2.4 P4.1/INT41/AN1 FLT/SS/SEG14/P2.5 P4.2/INT42/AN2 PWM01C/SEG15/P2.6 P4.3/INT43/AN3 PWM0C/SEG16/P2.7 P4.4/AN8/AVREF PWM01B/SEG17/P0.0 P4.5/SEG24/PWM1 PWM0B/SEG18/P0.1 Pin Configuration Diagram LQFP44 Note: The out most pin function has the highest priority, and the inner most pin function has the lowest priority (Refer to Pin Configuration Diagram.
  • Page 5: Lqfp32

    SH79F3283 4.3 LQFP32 TCK/INT47/LED_S4/SEG4/P1.3 P3.5/COM6/LED_C6/SGE27/AN5 LED_S5/SEG5/P1.4 P3.6/COM7/LED_C7/SGE26/AN6 RXD0/SEG9/P2.0 P3.7/COM8/LED_C8/SGE25/AN7 TXD0/SEG10/P2.1 SH79F3283P P4.0/INT40/AN0 FLT/SEG14/P2.5 P4.1/INT41/AN1 PWM01C/SEG15/P2.6 P4.2/INT42/AN2 PWM01A/SEG19/P0.2 P4.3/INT43/AN3 PWM0A/T4/P0.3 P4.4/AN8/AVREF Pin Configuration Diagram LQFP32 Note: The out most pin function has the highest priority, and the inner most pin function has the lowest priority (Refer to Pin Configuration Diagram.
  • Page 6 SH79F3283 Table 4.1 Pin Function Pin No. Pin No. Pin No. Pin Name Default Function (TQFP48) (LQFP44) (LQFP32) PWM01A/SEG19/P0.2 P0.2 PWM0A/T4/P0.3 P0.3 T2EX/INT0/P0.4 P0.4 T2/INT1/P0.5 P0.5 XTALX2/INT2/P0.6 P0.6 XTALX1/INT3/P0.7 P0.7 ---- XTAL1/P5.0 ---- XTAL2/P5.1 ---- ———— ———— /P5.2 BUZ/T3/P5.3 P5.3 ---- SEG20/P5.4...
  • Page 7 SH79F3283 (continue) Pin No. Pin No. Pin No. Pin Name Default Function (TQFP48) (LQFP44) (LQFP32) LED_S7/SEG7/P1.6 P1.6 LED_S8/SEG8/P1.7 P1.7 RXD0/SEG9/P2.0 P2.0 TXD0/SEG10/P2.1 P2.1 MOSI/RXD1/SEG11/P2.2 P2.2 MISO/TXD1/SEG12/P2.3 P2.3 SCK/SEG13/P2.4 P2.4 FLT/SS/SEG14/P2.5 P2.5 PWM01C/SEG15/P2.6 P2.6 PWM0C/SEG16/ P2.7 P2.7 PWM01B/SEG17/P0.0 P0.0 PWM0B/SEG18/P0.1 P0.1...
  • Page 8: Pin Description

    SH79F3283 5. Pin Description Pin No. Type Description I/O PORT P0.0 - P0.7 8 bit General purpose CMOS I/O P1.0 - P1.7 8 bit General purpose CMOS I/O P2.0 - P2.7 8 bit General purpose CMOS I/O P3.0 - P3.7 8 bit General purpose CMOS I/O P4.0 - P4.7...
  • Page 9 SH79F3283 (continue) Interrupt & Reset & Clock & Power INT0 - INT3 External interrupt 0-3 input source INT40 - INT47 External interrupt 40-47 input source The device will be reset by a low voltage on this pin longer than 10us, an internal ————...
  • Page 10: Sfr Mapping

    SH79F3283 6. SFR Mapping The SH79F3283 provides 256 bytes of internal RAM to contain general-purpose data memory and Special Function Register (SFR). The SFR of the SH79F3283 fall into the following categories: CPU Core Registers: ACC, B, PSW, SP, DPL, DPH...
  • Page 11 SH79F3283 Table 6.1 CPU Core SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 /PIN Reset Value Accumulator 00000000 ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 B Register 00000000 AUXC C Register 00000000 Program Status Word...
  • Page 12 SH79F3283 Table 6.3 Flash control SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 /PIN Reset Value IB_OFF Low byte offset of flash memory IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF 00000000 Bank0 for programming SET.7 SET.6...
  • Page 13 SH79F3283 Table 6.6 Interrupt SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 /PIN Reset Value IEN0 Interrupt Enable Control 0 00000000 EADC ECMP Bank0 ESCM_LPD IEN1 Interrupt Enable Control 1 00000000 EPWM ET3_ES1 ESPI Bank0 _CRC...
  • Page 14 SH79F3283 Table 6.7 Port SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 /PIN Reset Value 8-bit Port 0 00000000 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 Bank0 8-bit Port 1 00000000 P1.7 P1.6 P1.5 P1.4 P1.3...
  • Page 15 SH79F3283 Table 6.8 Timer SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 /PIN Reset Value TCON Timer/Counter Control ----0000 Bank0 ---- ---- ---- ---- ---- T2CON Timer/Counter 2 Control 00000000 EXF2 RCLK TCLK EXEN2 CP/R Bank0...
  • Page 16 SH79F3283 Table 6.9 EUART SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 /PIN Reset Value SCON EUART0 Serial Control 00000000 SM0/FE SM1/RXOV SM2/TXCOL Bank0 SBUF EUART0 Serial Data Buffer 00000000 SBUF.7 SBUF.6 SBUF.5 SBUF.4 SBUF.3 SBUF.2 SBUF.1...
  • Page 17 SH79F3283 Table 6.11 ADC SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 /PIN Reset Value ---- ---- ---- ---- ADCON ADC Control 00000000 ADON ADCIF REFC SCH2 SCH1 SCH0 GO/D Bank0 ADC Time Configuration 00000000 TADC2...
  • Page 18 SH79F3283 Table 6.14 LED SFRs POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 /PIN Reset Value DISPCON LED Control 00-0---- DISPSEL LEDON DUTY0 Bank0 DISPCON1 LED Control 1 000----- MODSW DUTY2 DUTY1 Bank0 DISPCLK0 LED clock 0...
  • Page 19 SH79F3283 Table 6.16 LPD SFR POR/WDT/LVR Mnem Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 /PIN Reset Value LPDCON LPD Control 00000000 LPDEN LPDF LPDMD LPDIF LPDS3 LPDS2 LPDS1 LPDS0 Bank0 Table 6.17 CRC SFRs POR/WDT/LVR Mnem Name Bit7...
  • Page 20 SH79F3283 SFR Map Bank0 Non Bit addressable addressable SPSTA CRCDL CRCDH IB_OFFSET IB_DATA CRCCON AUXC IB_CON1 IB_CON2 IB_CON3 IB_CON4 IB_CON5 XPAGE EXF0 P0PCR P1PCR P2PCR P3PCR P4PCR P0OS P0CR P1CR P2CR P3CR P4CR PWMLO EXF1 PWM1C PWM1P PWM1D PWM0DT PWM0C...
  • Page 21: Normal Function

    SH79F3283 7. Normal Function 7.1 CPU 7.1.1 CPU Core SFR Feature  CPU core registers: ACC, B, PSW, SP, DPL, DPH Accumulator ACC is the Accumulator register. Instruction system adopts A as mnemonic symbol of accumulator. B Register The B register is used during multiply and divide operations. For other instructions it can be treated as another scratch pad register.
  • Page 22: Enhanced Cpu Core Sfrs

     Enhanced CPU core registers: AUXC, DPL1, DPH1, INSCON The SH79F3283 has modified 'MUL' and 'DIV' instructions. These instructions support 16 bit operand. A new register - the register AUXC is applied to hold the upper part of the operand/result.
  • Page 23: Ram

    256 bytes RAM; MOVX A, @DPTR or MOVX @DPTR, A also to access external 1308 bytes RAM. In SH79F3283 the user can also use XPAGE register to access external RAM only with MOVX A, @Ri or MOVX @Ri, A instructions.
  • Page 24: Flash Program Memory

    In-Circuit Programming (ICP) mode and Self-Sector Programming (SSP) mode. Every sector is 1024 bytes. The SH79F3283 also embeds 1024 bytes EEPROM-like memory block for storing user data. Every sector is 256 bytes. It has 4 sectors.
  • Page 25 SH79F3283 (2) Mass Erase Regardless of the state of the code protection control mode, the overall erasure operation will erase all programs, code options, the code protection bit, but they will not erase EEPROM-like memory block. The user must use the following way to complete the overall erasure: The Flash programmer in ICP mode sends overall erasure instruction to run overall erasure.
  • Page 26: Flash Operation In Icp Mode

    , GND, TCK, TDI, TMS, TDO/SWE). SH79F3283 provides two types JTAG pins, the four JTAG pins (TDO, TDI, TCK, TMS) and the single SWE pin (SWE) are used to enter the programming mode. Only after the four pins are inputted the specified waveform, the CPU will enter the programming mode.
  • Page 27: Ssp Function

    But once sector has been programmed, it cannot be reprogrammed before sector erase. The SH79F3283 builds in a complex control flow to prevent the code from carelessly modification. If the dedicated conditions are not met (IB_CON2-5), the SSP will be terminated.
  • Page 28 SH79F3283 Table 7.8 SSP Type select Register F2H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IB_CON1 IB_CON1.7 IB_CON1.6 IB_CON1.5 IB_CON1.4 IB_CON1.3 IB_CON1.2 IB_CON1.1 IB_CON1.0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description SSP Type select IB_CON1[7:0] 0xE6: Sector Erase 0x6E: Sector Programming Table 7.9 SSP Flow Control Register1...
  • Page 29: Flash Control Flow

    SH79F3283 7.4.2 Flash Control Flow Set IB_OFFSET Set XPAGE Set IB_DATA Set IB_CON1 IB_CON2[3:0]≠5H Set IB_CON2[3:0]=5H IB_CON2≠5H IB_CON3≠AH IB_CON2≠5H Set IB_CON3=AH ELSE IB_CON3≠AH Set IB_CON4=9H IB_CON4≠9H Reset IB_CON1-5 Set IB_CON5=6H Sector Erase IB_CON1=E6H &IB_CON2[3:0]=5H &IB_CON3=AH &IB_CON4=9H &IB_CON5=6H IB_CON1=6EH &IB_CON2[3:0]=5H &IB_CON3=AH &IB_CON4=9H...
  • Page 30: Ssp Programming Notice

    SH79F3283 7.4.3 SSP Programming Notice To successfully complete SSP programming, the user’s software must be set as the following the steps: (1) For Code/Data Programming: 1. Disable interrupt; 2. Fill in the XPAGE, IB_OFFSET for the corresponding address; 3. Fill in IB_DATA if programming is wanted;...
  • Page 31: System Clock And Oscillator

    RC (16MHz, 12MHz, 8MHz, 128KHz), which is selected by code option OP_OSC (Refer to code option section for details). SH79F3283 has 4 oscillator pins (XTAL1, XTAL2, XTALX1, XTALX2), which can generate 1 or 2 clocks from 3 oscillator types. They also are selected by code option OP_OSC (Refer to code option section for details). The oscillator generates the basic clock pulse that provides the system clock to supply CPU and on-chip peripherals.
  • Page 32 SH79F3283 (continue) SYSCLK Prescaler Register 00: f OSCS 01: f OSCS CLKS [1: 0] 10: f OSCS 11: f OSCS If 32.768kHz oscillator is selected as OSCSCLK, these control bits is invalid. OSCXCLK On-Off control Register 0: turn off OSCXCLK...
  • Page 33: Oscillator Type

    SH79F3283 7.5.5 Oscillator Type (1) OP_OSC = 0000, 0001, 0011, 0100: internal RC 16M/12M/8M/128K, XTAL, XTALX shared with IO. XTALX1 XTALX2 XTAL1 XTAL2 (2) OP_OSC = 1010, 1011: 32.768kHz Crystal Oscillator at XTAL, Internal RC can be enabled, XTALX shared with IO.
  • Page 34: Capacitor Selection For Oscillator

    SH79F3283 7.5.6 Capacitor Selection for Oscillator Ceramic Oscillator Frequency 3.58MHz 4MHz Crystal Oscillator Frequency 32.768kHz 10 - 12pF 10 - 12pF 4MHz 8 - 22pF 8 - 22pF 12MHz 8 - 22pF 8 - 22pF Note: (1) Capacitor values are used for design guidance only! (2) These capacitors were tested with the crystals listed above for basic start-up and operation.
  • Page 35: System Clock Monitor (Scm)

    7.6 System Clock Monitor (SCM) In order to enhance the system reliability, SH79F3283 contains a system clock monitor (SCM) module. If the system clock breaks down (for example the external oscillator stops oscillating), the built-in SCM will switch the OSCCLK to the internal RC clock, and set system clock monitor bit (SCMIF) to 1.
  • Page 36: I/O Port

     Share with alternative functions The SH79F3283 has 46 bi-directional I/O ports. The PORT data is put in Px register. The PORT control register (PxCRy) controls the PORT as input or output. Each I/O port has an internal pull-high resistor, which is controlled by PxPCRy when the PORT is used as input (x = 0-5, y = 0-7).
  • Page 37 SH79F3283 Table 7.19 Port Data Register 80H - C0H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P0 (80H, Bank0) P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 P1 (90H, Bank0) P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 P2 (A0H, Bank0) P2.7...
  • Page 38: Port Diagram

    SH79F3283 7.7.3 Port Diagram SFEN PxPCRy Output Mode Input Mode 0 = ON (Pull-up) PxCRy 1 = OFF I/O Pad Write Data Data Bus Register Read Port Data Register Read Read Data Register/Pad Selection 0: From Pad 1: From data register...
  • Page 39 SH79F3283 Table 7.21 PORT0 Share Table Pin No. Priority Function Enable bit TQFP48 LQFP44 LQFP32 PWM01B Set EPWM1 bit and PWM01BOE bit in PWMEN Register Clear DISPSEL bit in DISPCON Register and set P0S0 in P0SS SEG17 Register P0.0 Above condition is not met...
  • Page 40 SH79F3283 PORT1: - LED Segment 1-8 (P1.0-P1.7) - LCD Segment 1-8 (P1.0-P1.7) - INT44-INT47 (P1.0-P1.3): External interrupt input Table 7.22 PORT1 Share Table Pin No. Priority Function Enable bit TQFP48 LQFP44 LQFP32 Set EX4 bit in IEN1 register and EXS44-47 bit in IENC register, INT44-47 P1.0-P1.3 in input mode...
  • Page 41 SH79F3283 (continued) Set SPEN bit in SPSTAT register MISO (when SPEN bit in SPSTAT register in Master mode, Auto Pull up) TXD1 Do write operation to SBUF1 register Clear DISPSEL bit in DISPCON Register and set P2S3 in P2SS Register SEG12 P2.3...
  • Page 42 SH79F3283 PORT4: - INT40-INT43 (P4.0-P4.3): External interrupt input - AN0-AN3, AN8 (P4.0-P4.4): ADC input channel - LCD SEGMENT22-24 (P4.5-P4.7) - AVREF (P4.4): AD reference voltage - PWM1: PWM1 output (P4.5) Table 7.25 PORT4 Share Table Pin No. Priority Function Enable bit...
  • Page 43 SH79F3283 PORT5: - XTAL1 (P5.0): oscillator input - XTAL2 (P5.1): oscillator output ——— - RST (P5.2): system reset pin - PWM1 (P5.3): PWM1 output - BUZ (P5.3): Buzzer output - T3 (P5.3): Timer3 external input - LCD SEGMENT20-21 (P5.4-P5.5) Table 7.26 PORT5 Share Table Pin No.
  • Page 44: Timer

    7.8 Timer 7.8.1 Features  The SH79F3283 has four timers (Timer2, 3, 4, 5)  Timer2 is compatible with the standard 8052 and has up or down counting and programmable clock output function  Timer3 is a 16-bit auto-reload timer and can operate even in Power-Down mode ...
  • Page 45 SH79F3283 Mode1: 16 bit auto-reload Timer Timer2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit in T2MOD. After reset, the DCEN bit is set to 0 so that Timer2 will default to count up. When DCEN is set, Timer2 can count up or down, depending on the value of the T2EX pin.
  • Page 46 SH79F3283 Mode2: Baud-Rate Generator Timer2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON. The baud rates for transmit and receive can be different if Timer2 is used for the receiver or transmitter and Timer4 is used for the other.
  • Page 47 SH79F3283 Mode3: Programmable Clock Output ——— A 50% duty cycle clock can be programmed to come out on P0.5. To configure the Timer2 as a clock generator, bit C/ T2 must be cleared and bit T2OE must be set. Bit TR2 starts and stops the timer.
  • Page 48 SH79F3283 Registers Table 7.28 Timer2 Control Register C8H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ——— ———— T2CON EXF2 RCLK TCLK EXEN2 C/T2 CP/RL2 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Timer2 overflow flag bit 0: No overflow(must be cleared by software) 1: Overflow (Set by hardware if RCLK = 0 &...
  • Page 49 SH79F3283 Table 7.29 Timer2 Mode Control Register C9H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 T2MOD TCLKP2 T2OE DCEN Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Prescaler control bit TCLKP2 0: Timer2 source is system clock 1:Timer2 source is 1/12 prescaler of system clock...
  • Page 50: Timer3

    SH79F3283 7.8.3 Timer3 Timer3 is a 16-bit auto-reload timer. It is accessed as two cascaded data registers: TH3 and TL3. It is controlled by the T3CON register. The Timer3 interrupt can be enabled by setting ET3 bit in IEN1 register (Refer to Interrupt Section for details).
  • Page 51 SH79F3283 Registers Table 7.31 Timer3 Control Register 88H, Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 T3CON T3PS.1 T3PS.0 T3CLKS.1 T3CLKS.0 Reset Value (POR/WDT/LVR/PIN Bit Number Bit Mnemonic Description Timer3 overflow flag bit 0: No overflow (cleared by hardware)
  • Page 52: Timer4

    SH79F3283 7.8.4 Timer4 Timer4 is a 16-bit auto-reload timer. It is accessed as two cascaded data registers: TH4 and TL4. It is controlled by the T4CON register. The Timer 4 interrupt can be enabled by setting ET4 bit in IEN1 register (Refer to interrupt Section for details).
  • Page 53 SH79F3283 Mode2: Mode2: 16 bit Auto-Reload Timer with T4 Edge Trig Timer4 operates as 16-bit timer in Mode 2. T4CLKS bit in T4CON.0 will be always 0. Timer4 can select system clock as clock source. Other settings accord with mode 0.
  • Page 54 SH79F3283 Registers Table 7.34 Timer4 Control Register C8H, Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 T4CON T4PS1 T4PS0 T4M1 T4M0 T4CLKS Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Timer4 overflow flag bit 0: No overflow (cleared by hardware)
  • Page 55: Timer5

    SH79F3283 7.8.5 Timer5 Timer5 is a 16-bit auto-reload timer. It is accessed as two cascaded data registers: TH5 and TL5. It is controlled by the T5CON register. The interrupt can be enabled by setting ET5 bit in IEN0 register (Refer to interrupt Section for details).
  • Page 56 SH79F3283 Registers Table 7.36 Timer5 Control Register C0H, Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 T5CON T5PS1 T5PS0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Timer5 overflow flag bit 0: No overflow (cleared by hardware) 1: Overflow (Set by hardware)
  • Page 57: Interrupt

     4 interrupt priority levels The SH79F3283 provides total 15 interrupt sources: 5 external interrupts (INT0, INT1, INT2, INT3, INT4), INT4 has 8 interrupt sources (INT40-47, which share the same vector address), 4 timer interrupts (Timer2, 3, 4, 5), two EUART interrupt, SPI interrupt, ADC Interrupt, PWM interrupts, SCM interrupt and LPD interrupt.
  • Page 58 SH79F3283 Table 7.40 Secondary Interrupt Enable Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ESCM_LPD IEN1 EPWM ET3_ES1 ESPI _CRC Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description SCM/LPD/CRC interrupt enable bit ESCM_LPD_CRC 0: Disable SCM/LPD/CRC interrupt 1: Enable SCM/LPD/CRC interrupt...
  • Page 59 SH79F3283 Table 7.41 Interrupt channel Enable Register BAH, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IENC EXS47 EXS46 EXS45 EXS44 EXS43 EXS42 EXS41 EXS40 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description External interrupt4 channel select bit (x = 7-0)
  • Page 60: Interrupt Flag

    SH79F3283 7.9.4 Interrupt Flag Each Interrupt source has its own interrupt flag, when interrupt occurs, corresponding flag will be set by hardware, the interrupt flag bits are listed in interrupt abstract table. When an external interrupt INT0/1/2/3 is generated, if the interrupt was edge trigged, the flag IEx (x = 0-3) that generated this interrupt is cleared by hardware when the service routine is vectored.
  • Page 61 SH79F3283 Table 7.44 External Interrupt Flag Register E8H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EXF0 IT4.1 IT4.0 IT3.1 IT3.0 IT2.1 IT2.0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description External interrupt4 trigger mode selection bit 00: Low Level trigger...
  • Page 62: Interrupt Vector

    SH79F3283 7.9.5 Interrupt Vector When an interrupt occurs, the program counter is pushed onto the stack and the corresponding interrupt vector address is loaded into the program counter. The interrupt vector addresses are listed in Interrupt Summary table. 7.9.6 Interrupt Priority Each interrupt source can be individually programmed to one of four priority levels by setting or clearing corresponding bits in the interrupt priority control registers IPL0, IPH0, IPL1, and IPH1.
  • Page 63: Interrupt Handling

    SH79F3283 7.9.7 Interrupt Handling The interrupt flags are sampled and captured at each machine cycle. All interrupts are sampled at the rising edge of the clock. If one of the flags was set, the CPU will find it and the interrupt system will generate a LCALL to the appropriate service routine, LCALL generated by hardware is not blocked by any of the following conditions: An interrupt of equal or higher priority is already in progress.
  • Page 64: External Interrupt Inputs

    Sample clock Prescaler Select bits and sample times Select bits in EXCON register are invalid in the IDLE and Power-Down mode. If an external interrupt is enabled when the SH79F3283 is put into Power down or Idle mode, the interrupt occurrence will cause the processor to wake up and resume operation.
  • Page 65 SH79F3283 Table7.47 External interrupt sample times control register 8BH, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EXCON I1PS1 I1PS0 I1SN1 I1SN0 I0PS1 I0PS0 I0SN1 I0SN0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description INT4 sample clock Prescaler Select bits...
  • Page 66: Interrupt Summary

    SH79F3283 7.9.10 Interrupt Summary Vector Interrupt number Source Enable bits Flag bits Polling Priority Address (C51) Reset 0000H 0 (highest) INT0 0003H Timer5 000BH INT1 0013H EUART0 0023H RI+TI Timer2 002BH TF2+EXF2 0033H EADC ADCIF 003BH ESPI SPIF INT2 0043H...
  • Page 67: Enhanced Function

    LCD display effect will down. Therefore SH79F3283 provides both the low power consumption and display effect of the display mode. Set MOD[1:0] = 10 to select this mode. When refresh the display data 20k bias resistors are selected to provide larger current. When keep the display data 75K/300k bias resistors are selected to save drive current.
  • Page 68 SH79F3283 one frame COM4 COM1 COM3 COM2 COM2 COM1 COM3 COM4 SEGn+1 SEGn SEGn SEGn+1 COM4 - SEGn LCD Waveform (1/4duty, 1/3bias)
  • Page 69 SH79F3283 COM8 COM1 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM2 COM3 COM4 SEGn SEGn COM1- SEGn - V1 - V2 - V3 LCD Waveform (1/8duty, 1/4bias)
  • Page 70: Register

    1101: V = 0.938V 1110: V = 0.969V 1111: V = 1.000V Note: SH79F3283 has LCD and LED driver, but cannot work at the same time. When DISPSEL = 1, LCD is disabled, when DISPSEL = 0, LED is disable.
  • Page 71 SH79F3283 Table 8.2 LCD Control Register 1 ADH, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DISPCON1 MODSW DUTY2 DUTY1 RLCD FCCTL1 FCCTL2 MOD1 MOD0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description LCD/LED shared control bit MODSW 0: P0SS is valid...
  • Page 72 SH79F3283 Table 8.3 LCD Clock Control Register ACH, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DISPCLK0 DCK1 DCK0 Reset Value (POR/WDT/LVR/PIN Bit Number Bit Mnemonic Description LCD clock prescaler select bit 00: 1/4 prescaler 01: 1/3 prescaler DCK[1:0]...
  • Page 73 SH79F3283 Table 8.5 P1 mode select register 9CH, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P1SS P1S7 P1S6 P1S5 P1S4 P1S3 P1S2 P1S1 P1S0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description P1 mode select bit P1S[7:0] 0: P1.0-P1.7 is I/O 1: P1.0-P1.7 shared as Segment (SEG1 - SEG8)
  • Page 74: Configuration Of Lcd Ram

    SH79F3283 8.1.2 Configuration of LCD RAM LCD 1/4 duty, 1/3 bias (COM1 - 4, SEG1 - 28) Address COM4 COM3 COM2 COM1 500H SEG1 SEG1 SEG1 SEG1 501H SEG2 SEG2 SEG2 SEG2 502H SEG3 SEG3 SEG3 SEG3 503H SEG4 SEG4...
  • Page 75 SH79F3283 LCD 1/8 duty, 1/4 bias (COM1 - 8, SEG1 - 24) Address COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 500H SEG1 SEG1 SEG1 SEG1 SEG1 SEG1 SEG1 SEG1 501H SEG2 SEG2 SEG2 SEG2 SEG2 SEG2 SEG2 SEG2 502H...
  • Page 76 SH79F3283 LCD 1/5 duty, 1/3 bias (COM1 - 5, SEG1 - 27) Address COM5 COM4 COM3 COM2 COM1 500H SEG1 SEG1 SEG1 SEG1 SEG1 501H SEG2 SEG2 SEG2 SEG2 SEG2 502H SEG3 SEG3 SEG3 SEG3 SEG3 503H SEG4 SEG4 SEG4...
  • Page 77 SH79F3283 LCD 1/6 duty, 1/3 or 1/4 bias (COM1 - 6, SEG1 - 26) Address COM6 COM5 COM4 COM3 COM2 COM1 500H SEG1 SEG1 SEG1 SEG1 SEG1 SEG1 501H SEG2 SEG2 SEG2 SEG2 SEG2 SEG2 502H SEG3 SEG3 SEG3 SEG3...
  • Page 78: Led Driver

    LED duty selection bit (Combination control with DUTY[2:1]) DUTY[2:1] Refer to DUTY[2:1] Note: SH79F3283 has LCD and LED driver, but cannot work at the same time. When DISPSEL = 1, LCD is disabled, when DISPSEL = 0, LED is disable.
  • Page 79 SH79F3283 Table 8.9 LED Control Register 1 ADH, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DISPCON1 MODSW DUTY2 DUTY1 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description LED duty selection bit (Combination control with DUTY0) 000: 1/4 duty...
  • Page 80: Configuration Of Led Ram

    SH79F3283 Table 8.11 P1 mode select register 9CH, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P1SS P1S7 P1S6 P1S5 P1S4 P1S3 P1S2 P1S1 P1S0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description P1 mode select bit P1S[7:0] 0: P1.0-P1.7 is I/O 1: P1.0-P1.7 shared as Segment (LED_S1 - LED_S8)
  • Page 81 SH79F3283 LED 1/6 duty (LED_C1 - 6, LED_S1 - 8) Address 500H COM1 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 501H COM2 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 502H COM3 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2...
  • Page 82: 12-Bit Pwm0 (Pulse Width Modulation)

     Lock register provided to avoid PWM control register to be unexpected change The SH79F3283 has one 12-bit PWM module, which can provide the pulse width modulation waveform with the period and the duty being controlled individually by corresponding register.
  • Page 83: 12-Bit Pwm Timer

    8.3.4 12-bit PWM Timer The SH79F3283 has one 12-bit PWM module. The PWM module can provide the pulse width modulation waveform with the period and the duty being controlled, individually. The PWMC is used to control the PWM module operation with proper clocks.
  • Page 84 SH79F3283 Table 8.16 PWM Period Control Register (PWM0PL) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWM0PL PP0.7 PP0.6 PP0.5 PP0.4 PP0.3 PP0.2 PP0.1 PP0.0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description PP0[7:0] 12-bit PWM period low 8 bits registers Table 8.17 PWM Period Control Register (PWM0PH)
  • Page 85: Pwm01X (X = A, B, C)

    SH79F3283 Programming Note: (1) Set PWMLO register to 55H and select the PWM module system clock. (2) Set the PWM period/duty cycle by writing proper value to the PWM period control register (PWMP) or PWM duty control register (PWMD). First set the low Byte, then the high Byte. Note that even if the high constant value keeps unchanged, it also needs to rewrite once, otherwise, the low modify is invalid.
  • Page 86: Dead Time

    SH79F3283 8.3.6 Dead time SH79F3283 provides dead time function on-chip. When PWM0S = 0, the dead time is generated as below. PWM int PWM int period PWM0S=0 duty cycle PWM0x x=A,B,C PWM01x x=A,B,C dead time dead time dead time Reload...
  • Page 87: 12-Bit Pwm1 (Pulse Width Modulation)

     Selectable output polarity, can be use as normal timer when the enable bit is set to 0 The SH79F3283 has one 8-bit PWM module, which can provide the pulse width modulation waveform with the period and the duty being controlled individually by corresponding register. The PWM module clock source or pin output selection is controlled by PWM1C register.
  • Page 88 SH79F3283 Table 8.22 PWM1 Period Control Register (PWM1PL) DAH, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWM1P PWM1P.7 PWM1P.6 PWM1P.5 PWM1P.4 PWM1P.3 PWM1P.2 PWM1P.1 PWM1P.0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description PWM1output Period = PWM1P * PWM clock...
  • Page 89 SH79F3283 7D 7E PWM1 clock t PWM1 output (PWM1S=0) PWM1 output (PWM1S=1) PWM1P = F0H PWM1 output duty cycle = 7FH x t PWM1D = 7FH PWM1 output period cycle = F0H x t PWM1 Output Example 01 02 03 04 05 06 07 08 09 0A 0B0C0D 0E 0F 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 01 02 03 04 05 06 07 08...
  • Page 90: Euart

    (SCON.5). When this bit is set to 0, the serial port runs at 1/12 of the system clock. When set to 1, the serial port runs at 1/4 of the system clock. The only difference from standard 8051 is that SH79F3283 in the mode 0 has variable baud rate.
  • Page 91 SH79F3283 Any instruction that uses SBUF as a destination register (“write to SBUF” signal) will start the transmission. The next system clock tells the Tx control block to commence a transmission. The data shift occurs at the falling edge of the SHIFT CLOCK, and the contents of the transmit shift register is shifted one position from left to the right.
  • Page 92 SH79F3283 Transmission begins with a “write to SBUF” signal, and it actually commences at the next system clock following the next rollover in the divide-by-16 counter (divide baud-rate by 16), thus, the bit times are synchronized to the divide-by-16 counter, not to the “write to SUBF”...
  • Page 93 SH79F3283 Mode2: 9-Bit EUART, Fixed Baud Rate, Asynchronous Full-Duplex This mode provides the 11 bits full duplex asynchronous communication. The 11 bit consists of one start bit (logical 0), 8 data bits (LSB first), a programmable 9 data bit, and a stop bit (logical 1). Mode 2 supports multiprocessor communications and hardware address recognition (Refer to Multiprocessor Communication Section for details).
  • Page 94 SH79F3283 Reception is enabled only if REN is high. The serial port actually starts the receiving of serial data, with the detection of a falling edge on the RXD pin. For this purpose RXD is sampled at the rate of 16 times baud rate. When a falling edge is detected, the divide-by-16 counter is immediately reset.
  • Page 95 SH79F3283 Baud Rate Generate In Mode0, the baud rate is programmable to either 1/12 or 1/4 of the system clock. This baud rate is determined by SM2 bit. When set to 0, the serial port runs at 1/12 of the system clock. When set to 1, the serial port runs at 1/4 of the system clock.
  • Page 96 SH79F3283 Slave 1 Slave 2 SADDR 10100100 10100111 SADEN (bit = 0 will be ignored) 11111010 11111001 Given Address 10100x0x 10100xx1 Broadcast Address (SADDR or SADEN) 1111111x 11111111 The given address for slave 1 and 2 differs in the LSB. For slave 1, it is ignore LSB, while for slave 2 LSB is 1. Thus to communicate only with slave 1, the master must send an address with LSB = 0 (10100000).
  • Page 97: Euart1

    SH79F3283 8.5.3 EUART1 The control and operate mode of EUART1 is similar to EUART0, the different is EUART1 has a baud rate generator is an 15-bit up-counting timer. Otherwise, the baud rate generator of EURART1 has baud rate fine adjustment function by set BFINE register.
  • Page 98: Register

    SH79F3283 8.5.4 Register Table 8.24 EUART0 Control & Status Register 98H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCON /RXOV /TXCOL Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description EUART0 Serial mode control bit, when SSTAT = 0...
  • Page 99 SH79F3283 Table 8.25 EUART0 Data Buffer Register 99H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SBUF SBUF.7 SBUF.6 SBUF.5 SBUF.4 SBUF.3 SBUF.2 SBUF.1 SBUF.0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description This SFR accesses two registers; a transmit shift register and a receive latch register...
  • Page 100 SH79F3283 Table 8.28 EUART1 Control & Status Register 98H, Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SM10 SM11 SM12 SCON1 REN1 TB18 RB18 /FE1 /RXOV1 /TXCOL1 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description EUART1 Serial mode control bit, when SSTAT1 = 0...
  • Page 101 SH79F3283 Table 8.29 EUART1 Data Buffer Register 99H, Bank1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SBUF1 SBUF1.7 SBUF1.6 SBUF1.5 SBUF1.4 SBUF1.3 SBUF1.2 SBUF1.1 SBUF1.0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description This SFR accesses two registers; a transmit shift register and a receive latch register...
  • Page 102: Serial Peripheral Interface (Spi)

    SH79F3283 8.6 Serial Peripheral Interface (SPI) 8.6.1 Features  Full-duplex, three-wire synchronous transfers  Master or slave operation  Six programmable master clock rates  Serial clock with programmable polarity and phase  Master mode fault error flag with MCU interrupt capability ...
  • Page 103: Baud Rate

    SH79F3283 8.6.3 Baud Rate In master mode, the baud rate is chosen from one of the six clock rates by the division of the internal clock by 4, 8, 16, 32, 64 or 128 set by the three bits SPR[2:0] in the SPCON register.
  • Page 104: Operating Modes

    SH79F3283 8.6.5 Operating Modes The Serial Peripheral Interface can be configured as one of the two modes, master mode or slave mode. The configuration and initialization of the SPI module is made through SPCON (the serial peripheral control register) and SPSTA (the serial peripheral status register).
  • Page 105 SH79F3283 Slave Mode (1) Enable The SPI operates in slave mode when the MSTR is cleared in the SPCON register. Before a data transmission occurs, the ——— ——— slave select (SS ) pin of the Slave device must be set to ’0’. The SS pin must remain low until the 1-byte transmission is complete.
  • Page 106: Transmission Formats

    SH79F3283 8.6.6 Transmission Formats Software can select any of four combinations of serial clock (SCK) phase and polarity using two bits in the SPCON, the clock polarity CPOL and the clock phase CPHA. CPOL defines the default SCK line level in idle state. It has no significant effect on the transmission format.
  • Page 107: Error Conditions

    SH79F3283 8.6.7 Error Conditions The following flags in the SPSTA signal SPI error conditions: (1) Mode Fault (MODF) ——— Mode fault error in master mode SPI indicates that the level on the SS pin is inconsistent with the actual mode of the device.
  • Page 108: Registers

    SH79F3283 8.6.9 Registers Table 8.33 Serial Peripheral Control Register A2H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SPCON MSTR CPHA CPOL SSDIS SPR2 SPR1 SPR0 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description Transfer Direction Selection 0: MSB first...
  • Page 109 SH79F3283 Table 8.34 Serial Peripheral Status Register F8H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SPSTA SPEN SPIF MODF WCOL RXOV Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description SPI Enable SPEN 0: Disable the SPI interface 1: Enable the SPI interface...
  • Page 110: Analog Digital Converter (Adc)

     Selectable external or built-in V  9 analog Channels input The SH79F3283 includes a single ended, 12-bit SAR Analog to Digital Converter (ADC) with build in reference voltage connected to the V , users also can select the AVREF port input reference voltage. The 10 ADC channels are shared with 1 ADC module;...
  • Page 111: Register

    SH79F3283 8.7.3 Register Table 8.36 ADC Control Register 93H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 —---—-----— ADCON ADON ADCIF REFC SCH2 SCH1 SCH0 GO/DONE Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description ADC Enable bit ADON 0: Disable the ADC module...
  • Page 112 SH79F3283 Table 8.37 ADC Control Register 1 92H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADCON1 RESO SCH3 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description ADC Resolution select bit RESO 0: Resolution is 12bit, ADDH is the high byte, ADDL[3:0] is the low 4 bit...
  • Page 113 SH79F3283 For Example System Clock TADC[2:0] TS[3:0] Sample Time Conversion Time (SYSCLK) 0000 30.5 *2=61µs 2*61=122µs 12*61+122=854µs 0111 30.5 *2=61µs 8*61=488µs 12*61+488=1220µs 30.5 *2=61µs 1111 15*61=915µs 12*61+915=1647µs 32.768kHz 30.5 *32=976µs 0000 2*976=1952µs 12*976+1952=13664µs 30.5 *32=976µs 0111 8*976=7808µs 12*976+7808=19520µs 1111 30.5 *32=976µs 15*976=14640µs...
  • Page 114 SH79F3283 Table 8.40 AD Converter Data Register (Compare Value Register) 96H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADDL Reset Value (POR/WDT/LVR/PIN) 97H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADDH Reset Value (POR/WDT/LVR/PIN) Bit Number...
  • Page 115: Buzzer

    SH79F3283 8.8 Buzzer 8.8.1 Feature  Output a signal (square wave) used for tones such as confirmation tone  Selectable whether to output one of 8 output frequencies or to disable the output 8.8.2 Register Table 8.41 Buzzer Output Control Register...
  • Page 116: Low Power Detect (Lpd)

    SH79F3283 8.9 Low Power Detect (LPD) 8.9.1 Feature  Low power detect and generate interrupt  LPD detect voltage is selectable  LPD de-bounce timer T is about 30-60µs The low power detect (LPD) is used to monitor the supply voltage and generate an internal flag if the voltage decrease below the specified value.
  • Page 117: Low Voltage Reset (Lvr)

    SH79F3283 8.10 Low Voltage Reset (LVR) 8.10.1 Feature  Enabled by the code option and V is 4.1V, 3.7V, 2.8V or 2.1V  LVR de-bounce timer T is 30-60µs  When the power supply voltage is lower than the set voltage V...
  • Page 118: Watchdog Timer (Wdt) And Reset State

    OVL Reset To enhance the anti-noise ability, SH79F3283 built in Program Counter (PC) over range detect circuit, if program counter value is larger than flash Rom size, or detect operation code equal to A5H which is not exist in 8051 instruction set, a OVL reset will be generate to reset CPU, and set WDOF bit.
  • Page 119: Crc Verification Module

     Two mode: High speed CRC mode and Normal CRC speed mode To improve the system reliability, the SH79F3283 has one CRC verification module built-in, CRC check code can be used to generate real-time code, using the generation polynomial: X +1, which adopt the CRC-CCITT Standard.
  • Page 120 SH79F3283 Table 8.45 CRC Check Data Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CRCDL (F9H, Bank0) CRCD7 CRCD6 CRCD5 CRCD4 CRCD3 CRCD2 CRCD1 CRCD0 CRCDH (FAH, Bank0) CRCD15 CRCD14 CRCD13 CRCD12 CRCD11 CRCD10 CRCD9 CRCD8 Reset Value (POR/WDT/LVR/PIN)
  • Page 121: Power Management

    The setting of PD bit will be the last instruction that CPU executed. Note: If IDL bit and PD bit are set simultaneously, the SH79F3283 enters Power-Down mode. The CPU will not go in Idle mode when exiting from Power-Down mode, and the hardware will clear both IDL & PD bit after exit form Power-Down mode.
  • Page 122: Register

    SH79F3283 8.13.4 Register Table 8.46 Power Control Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PCON SMOD SSTAT SSTAT1 Reset Value (POR/WDT/LVR/PIN) Bit Number Bit Mnemonic Description SMOD Baud rate double bit SSTAT SCON[7:5] function selection bit SSTAT1 SCON1[7:5] function selection bit...
  • Page 123: Warm-Up Timer

     Built-in oscillator warm-up counter to eliminate unstable state when oscillation start up SH79F3283 has a built-in power warm-up counter; it is designed to eliminate unstable state after power on or to do some internal initial operation such as read internal customer code option etc.
  • Page 124: Code Option

    SH79F3283 8.15 Code Option OP_WDT: 0: Enable WDT function (default) 1: Disable WDT function OP_WDTPD: 0: Disable WDT function in Power-Down mode (default) 1: Enable WDT function in Power-Down mode OP_RST: 0: P5.2 used as RST pin (default) 1: P5.2 used as I/O pin...
  • Page 125 SH79F3283 OP_P1DRIVE: 0: Port1 drive ability normal mode (default) 1: Port1 drive ability large mode OP_PORTDRIVE: (Except Port3) 0: Port drive ability normal mode (default) 1: Port drive ability large mode OP_P33-P30: 0: port3 [3:0] sink ability normal mode 1: port3 [3:0] sink ability large mode (default)
  • Page 126: Instruction Set

    SH79F3283 9. Instruction Set ARITHMETIC OPERATIONS Opcode Description Code Byte Cycle ADD A, Rn Add register to accumulator 0x28-0x2F ADD A, direct Add direct byte to accumulator 0x25 ADD A, @Ri Add indirect RAM to accumulator 0x26-0x27 ADD A, #data...
  • Page 127 SH79F3283 LOGIC OPERATIONS Opcode Description Code Byte Cycle ANL A, Rn AND register to accumulator 0x58-0x5F ANL A, direct AND direct byte to accumulator 0x55 ANL A, @Ri AND indirect RAM to accumulator 0x56-0x57 ANL A, #data AND immediate data to accumulator...
  • Page 128 SH79F3283 LOGIC OPERATIONS Opcode Description Code Byte Cycle ANL A, Rn AND register to accumulator 0x58-0x5F ANL A, direct AND direct byte to accumulator 0x55 ANL A, @Ri AND indirect RAM to accumulator 0x56-0x57 ANL A, #data AND immediate data to accumulator...
  • Page 129 SH79F3283 DATA TRANSFERS Opcode Description Code Byte Cycle MOV A, Rn Move register to accumulator 0xE8-0xEF MOV A, direct Move direct byte to accumulator 0xE5 MOV A, @Ri Move indirect RAM to accumulator 0xE6-0xE7 MOV A, #data Move immediate data to accumulator...
  • Page 130 SH79F3283 PROGRAM BRANCHES Instructions Description Code Byte Cycle ACALL addr11 Absolute subroutine call 0x11-0xF1 LCALL addr16 Long subroutine call 0x12 Return from subroutine 0x22 RETI Return from interrupt 0x32 AJMP addr11 Absolute jump 0x01-0xE1 LJMP addr16 Long jump 0x02 SJMP rel...
  • Page 131 SH79F3283 BOOLEAN MANIPULATION Opcode Description Code Byte Cycle CLR C Clear carry flag 0xC3 CLR bit Clear direct bit 0xC2 SETB C Set carry flag 0xD3 SETB bit Set direct bit 0xD2 CPL C Complement carry flag 0xB3 CPL bit...
  • Page 132: Electrical Characteristics

    SH79F3283 10. Electrical Characteristics Absolute Maximum Ratings* *Comments DC Supply Voltage....-0.3V to +6.0V Stresses exceed those listed under “Absolute Maximum Ratings” may cause permanent damage to this device.
  • Page 133 SH79F3283 (continue) Input Low Voltage 1 0.3 X V I/O Ports Input High Voltage 1 0.7 X V I/O Ports ——-------—— , T2, T3, T4, INT0/1/2/3/4, T2EX, RXD0, Input Low Voltage 2 0.2 X V RXD1, FLT, V = 2.4 - 5.5V ——-------——...
  • Page 134 SH79F3283 A/D Converter Electrical Characteristics (V = 5V, GND = 0V, T = 25°C, unless otherwise specified) Parameter Symbol Min. Typ. Max. Unit Condition Supply Voltage GND ≤ V ≤ V Resolution A/D Input Voltage A/D Input Resistor* MΩ V = 5.0V...
  • Page 135 SH79F3283 Low Voltage Reset Electrical Characteristics (V = 2.0V - 5.5V, GND = 0V, T = +25°C, unless otherwise specified) Parameter Symbol Min. Typ. Max. Unit Condition LVR Voltage1 LVR Enable, V = 2.0V - 5.5V LVR1 LVR Voltage2 LVR Enable, V = 2.0V - 5.5V...
  • Page 136: Ordering Information

    SH79F3283 11 Ordering Information Part No. Package SH79F3283P/032PR LQFP32 SH79F3283P/044PR LQFP44 SH79F3283U/048UR TQFP48...
  • Page 137: Product Naming Rules

    SH79F3283 12 Product Naming Rules SH 79 F 32 83 P / 032 P R R: Tray P: LQFP package U: TQFP package 032: pin 32 044: pin 44 048: pin 48 /: Dividing line P: LQFP package U: TQFP package...
  • Page 138: Package Information

    SH79F3283 13 Package Information TQFP48 Outline Dimensions unit: inch/mm θ2 See Detail F DETAIL F Dimensions in inches Dimensions in mm Symbol 0.047 0.002 0.006 0.05 0.15 0.035 0.041 1.05 0.270 0.281 6.85 7.15 0.270 0.281 6.85 7.15 0.346 0.362 0.346...
  • Page 139 SH79F3283 LQFP 44 Outline Dimensions (BODY SIZE: 10*10) unit: inch/mm θ2 See Detail F DETAIL F Seating Plane Dimensions in inches Dimensions in mm Symbol 0.057 0.065 1.45 1.65 0.000 0.001 0.01 0.21 0.051 0.059 0.388 0.400 9.85 10.15 0.388 0.400...
  • Page 140 SH79F3283 LQFP32 Outline Dimensions unit: inch/mm θ2 See Detail F DETAIL F Dimensions in inches Dimensions in mm Symbol 0.057 0.065 1.45 1.65 0.000 0.008 0.01 0.21 0.051 0.059 1.30 1.50 0.268 0.281 6.80 7.15 0.268 0.281 6.80 7.15 0.346 0.362...
  • Page 141: Product Spec. Change Notice

    SH79F3283 14 Product SPEC. Change Notice Version Content Date Original Jun. 2021...
  • Page 142 SH79F3283 IMPORTANT NOTICE This manual is the property of Sino Wealth Electronic Ltd. and its affiliates ("Company"). This manual, including all of the Company's products ("Products") described herein, is owned by the Company according to relevant laws or treaties. The Company reserves all rights under such laws and treaties, and does not grant you any license to use its patents, copyrights, trademarks and other intellectual property rights.
  • Page 143: Table Of Contents

    SH79F3283 Content FEATURES ............................... 1 GENERAL DESCRIPTION ..........................1 BLOCK DIAGRAM ............................2 PIN CONFIGURATION ............................. 3 4.1 TQFP48 ........................................ 3 4.2 LQFP44 ........................................ 4 4.3 LQFP32 ........................................ 5 PIN DESCRIPTION ............................8 SFR MAPPING ............................... 10 NORMAL FUNCTION ............................. 21 7.1 CPU ........................................
  • Page 144 SH79F3283 8.3 12- PWM0 (P ) ............................82 ULSE IDTH ODULATION 8.3.1 Feature ......................................82 8.3.2 PWM Module Enable ................................... 82 8.3.3 PWM Timer Lock Register ................................82 8.3.4 12-bit PWM Timer ..................................83 8.3.5 PWM01x (x = A, B, C) ................................. 85 8.3.6 Dead time .....................................

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