Avalue Technology EMX-RPLP User Manual page 60

13th gen intel core soc & celeron processor mini itx motherboard
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EMX-RPLP User's Manual
3.6.3.2.1.3
PCI Express Root Port 8(LAN2-I225/I226)
Item
PCI Express Root Port 8
(LAN2-I225/I226)
ASPM
L1 Substates
L1 Low
PTM
PCIe Speed
60 EMX-RPLP User's Manual
Option
Disabled
Enabled[Default],
Disabled[Default]
L1
Auto
Disabled[Default],
L1.1
L1.1 & L1.2
Disabled[Default]
Enabled
Disabled[Default]
Enabled
Auto[Default]
Gen1
Gen2
Gen3
Description
Control the PCI Express Root Port.
Set the ASPM Level: Force L0s – Force all
links to L0s State AUTO – BIOS auto
configure DISABLE – Disables ASPM.
PCI Express L1 Substates settings.
PCI Express L1 Low Substate
Enable/Disable.
Enable/Disable Precision Time
Measurement
Configure PCIe speed.

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