Dma Controller; Dma Controller Clock Cycle; Controller Channels - HP Vectra Reference Manual

Direct Memory Access (DMA)
Controller
DMA control is provided by two Intel 8237A chips that provide
timing, control functions, and most of the address generation,
and a 74LS612 page register Ie that generates the most
significant memory address bits. Each 8237A chip supports four
channels, with DMA controller 2 cascaded to DMA controller 1 for
seven DMA channels. The DMA controller regulates transfers from
I/O to memory or from memory to I/O. Buffering the system
address bus and the system backplane bus signals with three-state
gates permits DMA operations to take over the bus.
DMA
Controller Clock Cycle
The DMA controller operates at 4MHz, which results in a clock
cycle time of 250ns. The DMA clock is derived by dividing the
backplane clock by two. All DMA data transfers use five DMA
clock cycles with a sum of 1.25us. Not included in this time are
the cycles spent in transfer of bus control to the DMA controller.
Controller Channels
DMA allows an I/O device to gain direct access to the system bus
via the backplane channel connectors. The DMA controller allows
prioritized bus access for individual devices.
DMA controller 1 contains channels 0 through 3. It supports 8-bit
data transfers between 8-bit I/O devices and 8-bit or 16-bit
memory. During 8-bit to 16-bit transfers the backplane state
machine provides the required multiplexing. Each channel can
transfer data throughout the 16 Mbyte system address space in
64 Kbyte blocks.
Processor Board 23