HP Vectra Reference Manual page 148

Line Status Register (XFDH)
This register provides information on the data transfer. Bits
1
through 4 are error conditions that generate a receiver line status
interrupt. This register is not to be written to.
Bit Data Definition
0
1
Set when a complete incoming character has been
received and transferred into the receiver buffer
register.
0 Reset by reading the data in the receiver buffer
register or writing 0 in it.
Indicates that data in the receive buffer register was
not read by the processor before the next character
was transferred into the register, thereby erasing the
previous character.
0 Reset when the 80286 reads the Line Status Register.
2
1 Detection of a parity error.
~
0 Reset when the 80286 reads the Line Status Register.
3 Framing error has occured, character does not have a
valid stop bit.
0 Reset when the 80286 reads the Line Status Register.
4
The received data line was at a space state (0) for
longer than a transmission time of a complete data
character. (Including start, data, parity, and stop bits.)
0 Reset when the 80286 reads the Line Status Register.
S
Set when a character is transferred from the transmit
buffer register to the transmit shift register indicating
the card is available to transmit another character.
0
Reset when the next character is written into the
transmit buffer register.
6 Transmit buffer register and transmit shift register are
empty.
0
Reset when either register contains a character.
7 0 Always.
Serial/Parallel Card 131