Hard Disc Controller Subsystem; Hardware Interface - HP Vectra Reference Manual

Hard Disc Subsystem
The HP45816A and HP45817A hard disc subsystem cards insert
into slot seven of the backplane I/O slots. The disc controller is an
intelligent subsystem using the 6809 processor to offload disc
operations from the system processor. Its implementation uses the
backplane I/O signals defined in Section 2 of this manual.
Hardware Interface
Interface to the system is through two registers: the control/status
register, and the data register. Each port is connected to the 8-bit
interface data bus. Each port is selected by a decoded address
defined by the system.
The hard disc subsystem card occupies two address locations in
the system I/O memory space. The selected lines for these
registers are generated by the system address and lOR or lOW
lines. One location addresses the write-only control register and
the read-only status register, and the other location addresses the
bidirectional FIFO data register.
The controller-to-system hardware interface is performed by
programmable I/O. It interfaces with the system at software
interrupt 13 BIOS level. Refer to the
HP Vectra Technical Reference
Manual Volume 2: System BIOS
for detailed BIOS listings. The
interface does not bottleneck the data transfer rate. The rate is
determined by the speed of the system and the data rate of the
disc drive.
Disc Drives 109