Supermicro X13DGU User Manual page 113

Chipset Configuration

Warning: Setting the wrong values in the following features may cause the system to malfunc-
tion.
North Bridge
This feature allows you to configure the following North Bridge settings.
Uncore Configuration

The following information is displayed.
•
Number of CPU
•
Current UPI Link Speed
•
Current UPI Link Frequency
•
Global MMIO Low Base / Limit
•
Global MMIO High Base / Limit
•
PCIe Configuration Base / Size
Degrade Precedence
Use this feature to select the degrading precedence option for Ultra Path Interconnect
(UPI) connections. Select Topology Precedent to degrade UPI features if system options
are in conflict. Select Feature Precedent to degrade UPI topology if system options are
in conflict. The options are Topology Precedence and Feature Precedence.
Link L0p Enable
Select Enable for the system BIOS to enable Link L0p support which will allow the CPU
to reduce the UPI links from full width to half width in the event when the CPU's workload
is low in an attempt to save power. This feature is available for the system that uses
Intel processors with UPI technology support. The options are Disable, Enable, Auto,
and Full L0p Enable.
Note 1: You can change the performance settings for non-standard applications by
using this parameter. It is recommended that the default settings be used for standard
applications.
Note 2: The option of Full L0p Enable is available when the 5th Gen. Intel Xeon Scal-
able Series processor is used.
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Chapter 4: UEFI BIOS