D Data Flow At The Time Of Data Register Write - Mitsubishi Electric Melsec-k Instruction Manual

I
4. PROGRAMMING
~ ~
~-
4.5.4
D
data flow at the time of data register write
Master channel (K3NCPUP2)
K3NCPU Optical data link card
1 #
I
I
7
Data register communication
I
D qata
OUT
FlOO
O I
O I
OUT
1
FlOO
OUT
1
FlOO
OUT
1
F I O O
X / Y data communication
I
X 1024/Y 1024=5ms
c--=-=3
Y32+D24=1 m$
X32=0.2ms
*
X/Y data communication
4
X/Y data com mu ni cati on
4
I
MA 1 8=0F F
X/Y data communication
FFFF
Local channel
KJ71P3
1
1
E N D 1
e ; m m u n i ea ti
0;
[ - k
024=1 lms
X /Y data com m u n i ea
t
i o n
I
I
T
-
-i
Compleiion.
t
signal
Fig.
4.9
D Data Flow a t the Time of Data Register Write
D data flows as shown by the thick line in Fig. 4.9.
L
1
Process time is longer by approximately 1 ms in the master channel when the data registers are the
maximum simultaneous 24 points (DA22
=
24). In the local channel, the process time i s longer by
approximately 1 1 ms. The transmission delay time in response to the write request from the master
channel to the local channel is (1 cycle of K3NCPUP2
+
2 cycles of K2CPU-S3). The MA18 "on"
time during sending i s (2 cycles of K3NCPUP2
+
2 cycles of K2CPU-S3).