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1
D
P1
1
3
5
7
9
11 12
13 14
15 16
17 18
19 20
Analog Input
C
J5
+VA
-VA
TP1
1
2
+5VA
3
4
TP2
DGND
AGND
5
6
7
8
+3.3VD
+5VD
9
10
B
A
1
2
3
J1
2
4
J2
6
8
10
TP3
TP4
TP5
TP6
W1
+BVDD
J6
2
4
6
8
10
12
11
ADC Control
P3
2
4
6
8
10
12
14
16
18
20
Parallel Control
2
3
4
Analog-to-Digital Converter
+IN
-IN
EXT_REF
Power & Digital Buffer
+AVCC
+VA
B_DB[17...0]
-VA
+BVDD
CS
1
RD
3
CONVST
5
BYTE
7
BUS18/16
9
B_BUSY
DC_CS
1
3
5
A0
7
A1
9
A2
11
13
15
DC_CONVST
17
INTC
19
4
5
REV
B_DB[17...0]
P2
B_DB0
1
2
1
2
B_DB1
3
4
3
4
B_DB2
5
6
5
6
B_DB3
7
8
7
8
B_DB4
9
10
9
10
B_DB5
11
12
11
12
B_DB6
13
14
13
14
B_DB7
15
16
15
16
B_DB8
17
18
17
18
B_DB9
19
20
19
20
21
22
B_DB10
21
22
B_DB11
23
24
23
24
B_DB12
25
26
25
26
B_DB13
27
28
27
28
B_DB14
29
30
29
30
B_DB15
31
32
31
32
B_DB16
33
34
33
34
B_DB17
35
36
35
36
ADC Data Bus
TITLE:
Engineer:
Lijoy Philipose
DOCUMENT CONTROL #:
Drawn By:
Lijoy Philipose
FILE:
BlockDiagram.sch
DATE:
5
6
Revision History
ECN Number
Approved
D
C
B
ti
A
12500 TI Boulevard. Dallas, Texas 75243
ADS8481/ADS8482EVM Block Diagram
REV:
6458784
A
23-Aug-2006
SIZE:
SHEET:
OF:
1
3
6
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