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Theory of Operation 2-3
Controller Interface to HP-IB (PHI Chip)
The PHI chip provides a high-speed interface to the HP-IB via PHI/HP-IB converters for
the host system and the 280. The PHI appears to the 280 as a bank of eight addressable
registers. All interaction with the HP-IB is performed by reading from or writing to these
registers. In addition, the PHI chip provides buffering for in-bound and out-bound data
through two 8-byte, first-in, first-out buffers (FIFO's) which can be accessed by the host
processor. The lines provided by the PHI chip for interfacing to the 280 include:
• An 8-bit-wide data bus,
• Three register select lines for selecting the eight registers,
• A data direction line for specifying either reading or writing of the selected register,
• Two handshake lines to coordinate data transfer,
• An interrupt line to alert the host processor to selected events.
Four, quad instrumentation bus transceivers are used with the PHI chip for interfacing with
the HP-IB. Two transceivers are assigned for 8-bit data transfer between the HP-IB and the
PHI chip, and two are used for HP-IB commands and handshakes.
Processor and Memory
The processor on the controller is a 280A microprocessor. It is a single chip, 4 MHz, 8-bit
microprocessor. The 280A executes the programs stored in four, 2048 x 8-bit Programma-
ble Read Only Memory (PROM) chips or one, 8192 x 8-bit Read Only Memory (ROM) chip
to perform the controller functions. Also available are two, 1024 x 4-bit Random Access
Memory (RAM) chips for stack operations, scratchpad memory, and buffering the data sent
to and from the disc drive.
The 280A microprocessor is constantly monitoring the PHI chip for in-bound commands
from the HP-IB. If it receives a command, the 280A will execute the necessary programs
from ROM to implement the command. On completion, the 280A goes back to monitoring
the PHI chip for a command.
The 280A communicates with the PHI chip and several registers on the controller via its I/O
ports. The PHI chip's registers are assigned 1/
0
ports 1016 through 1716, and the controller
registers are assigned 1/ 0 ports 6016 through 6716.
The controller registers contain:
• Status inf0rmation from the disc drives,
• Control signals sent to the disc drives,
• Status of switches and error indicators on the controller,
• Control signals to enable read, write, and error detection electronics on the controller,
the serializer / deserializer (SERDES) registers, and the self-test LED display.
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