Table of Contents
Advertisement
correction process by XOR'ing the syndrome bytes
(in the DDC) with the bytes in the data field that
contain the error.
3-38.
FORMAT
There are three different ways that the DDC can
format a track:
• Internal sequential - the DDC increments the
sector number for each physically adjacent
sector.
• Buffer table - The information for each header
is stored in the buffers and transferred into the
DDC at the appropriate time by local DMA.
• Interlock - The microprocessor updates the
format parameter bytes in the DDC after each
sector is formatted.
The firmware causes the DOC to format an entire
track or, during a sparing operation, any number
of sectors on a track.
3-39.
HP-IB INTERFACE IC
The HP-IB Interface IC is used as the HP-IB inter-
face chip. It implements all of the IEEE STO 488
interface functions. The controller functions are
not used in this application. The HP-IB Interface
IC has eight internal 10-bit registers which allow
the microprocessor to initiate and monitor the
HP-IB transfers. In addition, it has an 8-byte in-
bound buffer and an 8-byte out-bound buffer for
data buffering.
Data transfers to and from the HP-IB Interface IC
on the microprocessor side are synchronous, even
though the HP-IB Interface IC was designed for
asynchronous transfers. This is necessary beca use
the microprocessor has a synchronous bus. DMA
transfers are also synchronous. Synchronous trans-
f ers are accomplished by asserting NIOGO for the
correct period of time. During a remote DMA
transfer from the buffers 0 and 1 to the HP-IB
Interface Ie, NIOGO is delayed so that the data is
valid on the DMA bus before NIOGO is asserted.
In this case, NDDRD (Not Delay Read) is used to
generate the NIOGO (Not I/O Go) signal in the
DMA PAL.
Theory Of Operation
7957/7958
The HP-IB Interface IC is operated in the 8-bit
mode since the microprocessor is an 8-bit device.
Remote DMA transfers are also 8 bits wide,
however if the transfer is from the HP-IB
Interface IC to Buffers 0 and 1, then the ninth and
tenth bits (DO and 01) are latched. Both DO and
01 are latched by DQCLK which is equivalent to
NIOGO when the transfer direction is from the
HP-IB Interface IC to the buffers. When transfer-
ring in the other direction, DQCLK remains high.
When an incoming byte is tagged with EOI or is a
secondary address, then Dl is high.
NREMGO
(Not Remote Transfer Go) will be set high at the
end of that byte transfer and cause the DMA Bus
Arbiter to inhibit any more remote DMA transfers.
The microprocessor can reset NREMGO back low
by toggling the remote DMA direction
bit
(NREMRD) low. This reenables the remote DMA
transfer. NREMGO is a status bit which can be
read by the microprocessor.
The state of NREN (Not Remote Transfer Enable)
selects the HP-IB Interface IC address lines. When
a remote transfer is active, NREN is low and the
address is fixed at 2, which is the address of the
HP-IB Interface Ie buffer (inbound and out-
bound).
When a remote transfer is not active,
NREN is high and the DMA bus address lines are
selected.
When
NREN
is high, the DDe
read/write line (NR/W) is selected. When NREN
is low, the control bit NREMRD is selected. The
microprocessor sets NREMRD low when the
remote DMA transfer is from Buffers 0 and 1 to
HP-IB Interface Ie, and sets it high when the
transfer is in the opposite direction.
3-40.
BUFFERS
One 8k by 8 RAM (Buffer
1)
resides on the upper
(or most significant) half of the DMA bus, and
another 8k by 8 RAM (Buffer 0) resides on the
lower (or least significant) half.
The addressing
and chip selects are arranged so that during remote
DMA and microprocessor transfers, Buffer
0
is ac-
cessed if the address is even, and Buffer 1 is ac-
cessed if the address is odd.
3-17
Advertisement
Table of Contents
