HP 9800 Series Service Manual page 33

2.2 Theory of Operation
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MICRO-
PROCESSOR
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DATA BUS
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:II
ROM
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MEMORY
MEMORY
MEMORY i . . - - -
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ADDRESS
HCONTROL
DECODER RAM . - -
LINES
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• MEMORY
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ADDRESS BUS
IIO CONTROL LINES
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I/O
.• INTERRUPT
LINES INTER-
k==~--jRUPT
CIRCUIT
ADDRESS
DECODE
-
I/O WRITE \iUN~
IIO READ CONTROL
CLOCK 8 DATA CONTROL
PHI CONTROL
DRIVE CONTROL OUTPUTS
........................... ............. ......... ........... ....... ......................................................... :""' : ' : "' : ""' : "' : ::' : :\:>:::":' { ?>
I/O WRITE
REGISTERS
MULTI-
PLEXORS
t
PARALLEL
OUTPUT
LEOS
CRC, READ, WRITE CONTROL LINES
SWITCHES
ERROR INDICATORS
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LOCKEDII+--.---' BACK
LOOP CIRCUllk--,
PLL
CLOCK
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CLOCK AND DATA
DATA
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SEPAR-i--
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PHI
LN
·~~UPTS
HOST SYSTEM
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PI
BSE
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CHIP
SERIALIZER ~
DE- SERIAL CLOCK OUT
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PARALLEL
SERIALIZER HWRITE DATA OUT
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SERIAL DATA
Jg~~ERATOR
ENCODEJ
INPUT
OUT
Figure 2.1. Controller Bloc .. Aagram
FLEXIBLE
DISC
DRIVE