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2-4 Theory of Operation
Read Operation
When the Z80A receives a command from the HP-IB to read a sector from the disc, it selects
the specified drive, enables the drive to read, and enables the read electronics on the
controller. The disc drive begins sending a pulse stream which represents the flux transitions
on the disc. The phase locked loop synchronizes to the clock bits recorded with the data to
generate a bit clock. The pulse stream is then clocked into the data separator circuit which
separates the pulses into clock bits and data bits according to the recording format of the
disc. The serial clock and data bits are then shifted into the SERDES shift registers and
presented to the Z80A as two 8-bit parallel bytes. The Z80A then reads the I/O ports
corresponding to the SERDES registers and stores the data in a RAM buffer. When an entire
sector has been read and is stored in the RAM buffer, the Z80A transfers the buffer to the
host system via the HP-IB.
Write Operation
When the Z80A receives a write command from the HP-IB, it fills the RAM buffer with a
sector of data from the HP-IB. It then enables the write electronics and writes eight bits of
parallel data and eight bits of parallel clock to the SERDES. The SERDES changes the
parallel clock and data bytes to serial bit streams which are input to the write encoder. The
write encoder combines the clock and data bits into a single pulse stream according to the
recording format of the disc. This pulse stream, which represents the flux transitions to be
stored on the disc, is then sent to the disc drive.
Error Detection
Several types of errors are detected by electronics on the controller. These are eRe error,
overrun error and margin error.
The Cyclic Redundancy Check (eRC) is two, 8-bit data bytes that are written on the disc
with every sector. As the serial data is sent to the write encoder, it also goes to a CRe chip
which computes the CRe for the data stream. After the last data byte is written on the disc,
the two CRC bytes are written. When a sector is read back, the separated serial data,
including the two CRe bytes, are again input to the eRC chip. The eRe bytes are computed
such that when the data field and its CRe are input to the eRe chip, the chip can detect an
'" error in the bit stream. After reading the data field, the Z80A checks a bit in the controller
status register to see if a CRe error occurred. If so, the error is reported to the host system
via HP-IB.
An overrun error occurs if the Z80A is not sending or receiving data fast enough to keep up
with the bits coming off the disc. This is detected by a logic circuit on the controller. At the
conclusion of the read or write operation, the Z80A checks a bit in the controller status
register to see if an overrun occurred, and notifies the host system accordingly.
A margin error occurs when a clock or data bit occurs too close to the edge of the clock or
data window of the bit stream. This does not indicate that the data was read incorrectly, but
only that the controller may not be able to read the sector in the future if the bits shift any
further within the window. This error is checked by the Z80A following a read operation and
reported to the host system only if the host system requests a verify or read verify operation.
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