Silicon Laboratories C8051F00 01 DK Series User Manual page 8

C8051F00x/01x-DK
6.5. Expansion I/O Connector (J2)
The 64-pin expansion I/O connector J1 provides access to most signal pins of the C8051F005 device on the target
board. A small through-hole prototyping area is also provided. All I/O signals routed to connector J2 are also routed to
through-hole connection points between J2 and the prototyping area (see Figure 4 on page 9). The signal layout pat-
tern of these connection points is identical to the adjacent J2 connector pins. See Table 5 for a list of pin descrip-
tions for J2.
Pin Description
1 +VD (digital voltage supply)
2 XTAL1
3 P1.6
4 P1.7
5 P1.4
6 P1.5
7 P1.2
8 P1.3
9 P1.0
10 P1.1
11 P0.6
12 P0.7
13 P0.4
14 P0.5
15 P0.2
16 P0.3
17 P0.0
18 P0.1
19 P2.6
20 P2.7
21 P2.4
22 P2.5
23 P2.2
24 P2.3
25 P2.0
26 P2.1
27 P3.6
8
Table 5: J2 Pin Descriptions
Rev. 0.6
Pin Description
28 P3.7
29 P3.4
30 P3.5
31 P3.2
32 P3.3
33 P3.0
34 P3.1
36 /RST
39,41,42 GND (digital ground)
45,47,63 GNDA (analog ground)
46,64 +VA (analog voltage supply)
48 DAC0
49 CP1-
50 DAC1
51 CP1+
52 CP0-
53 VREF
54 CP0+
55 AIN0
56 AIN1
57 AIN2
58 AIN3
59 AIN4
60 AIN5
61 AIN6
62 AIN7