Onkyo TX-NR906 Service Manual page 141

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -74
Q206: ENVY24MT (PCI Multi-channel Audio Controller)
TERMINAL DESCRIPTION(1/2)
I - Input Signal
O - Output Signal
B - Bidirectional Signal
OD - Open Drain
A - Analog Signal
PU - Pull-up. 50 kohm nominal
Symbol Type
AD[31:0]
B
CBE#[3:0] B
PCICLK I
DEVSEL#
B
B
FRAME#
GNT#
I
IDSEL
I
INTA# OD
B
IRDY#
B
PAR
O
REQ#
RST# I
B
STOP#
B
TRDY#
SDA B
SCLK O
TX1
O, PU
RX1 I, PU
PCI BUS INTERFACE
Description
Multiplexed PCI Address / Data Bus.
Bus Command / Byte Lane Enable. These signals are bus commands during the address phase
and byte lane enable during the data phase. These signals are output during a bus master cycle.
PCI Bus Clock.
Device Select. The VT1720T drives this signa l active when it decodes its address as the current target
of the current acces.
PCI Cycle Frame. When asserted by the bus mster, this signal indicates the beginning of a bus
transaction.During the final data phase of a bus transaction it is deasserted.
PCI Bus Grant. When active it indicates bus master is granted to the VT1720T.
Initialization Device Select. This is the chip select during the PCI configuration register accesses
PCI Interrupt Request.
Initiator Ready.
Parity.
Bus Master Control Request.
System Reset. All VT1720T registers and state machines are at default when this signal is asserted.
Target Disconnect.
Target Ready.
²
I C PORT
Serial Data.
Serial Bit Shift Clock.
MPU-401 UART
MPU-401 Transmit Data.
MPU-401 Receive Data.
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TX-NR906/NA906