Download Print this page

Renesas R5F56307CDFN User Manual

Renesas R5F56307CDFN User Manual

32-bit mcu rx family / rx600 series rx630 group

Table Of Contents

page of 1654

/ 1654
Contents
Table of Contents
Bookmarks

Table of Contents

Advertisement

Quick Links

Cover

RX630 Group

32

RENESAS 32-Bit MCU

RX Family / RX600 Series

All information contained in these materials, including products and product specifications,

represents information on the product at the time of publication and is subject to change by

Renesas Electronics Corp. without notice. Please review the latest information published by

Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.

website (http://www.renesas.com).

www.renesas.com

User's Manual: Hardware

Rev.1.50

Sep 2012

Table of Contents

Advertisement

Table of Contents

Need help?

Need help?

Do you have a question about the R5F56307CDFN and is the answer not in the manual?

Questions and answers

Summary of Contents for Renesas R5F56307CDFN

Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
Page 2 Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures.
Page 3 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence.
Page 4 Precautions when Porting Software among RX630 Group Products When porting software from one RX630-group product to another, you need to pay attention to the following restrictions along with the differences in peripheral function and so on of the individual products. 1.
Page 5 Detailed descriptions of the CPU and instruction set RX Family Series R01US0032EJ Software User’s manual: Software Application Note Examples of applications and sample programs — — Renesas Preliminary report on the specifications of a product, — — Technical Update document, etc.
Page 6 2. Description of Registers Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. The standard format and notation for bit charts and tables are described below. x.x.x ...
Page 7 3. List of Abbreviations and Acronyms Abbreviation Full Form ACIA Asynchronous Communication Interface Adapter bits per second Cyclic Redundancy Check Direct Memory Access DMAC Direct Memory Access Controller Global System for Mobile Communications Hi-Z High Impedance IEBus Inter Equipment Bus Input/Output IrDA Infrared Data Association...
Page 8: Table Of Contents
Contents Overview ............................47 Outline of Specifications ....................... 47 List of Products ........................53 Block Diagram ........................56 Pin Functions ........................57 Pin Assignments ........................62 CPU ..............................97 Features..........................97 Register Set of the CPU ....................... 98 2.2.1 General-Purpose Registers (R0 to R15) ..................99 2.2.2 Control Registers .........................
Page 9 Pipeline ..........................113 2.8.1 Overview ........................... 113 2.8.2 Instructions and Pipeline Processing ..................115 2.8.2.1 Instructions Converted into Single Micro-Operation and Pipeline Processing ....115 2.8.2.2 Instructions Converted into Multiple Micro-Operations and Pipeline Processing ..117 2.8.2.3 Pipeline Basic Operation ....................120 2.8.3 Calculation of the Instruction Processing Time ................
Page 10 6.3.3 Voltage Monitoring 1 Reset and Voltage Monitoring 2 Reset..........186 6.3.4 Deep Software Standby Reset ....................188 6.3.5 Independent Watchdog Timer Reset ..................188 6.3.6 Watchdog Timer Reset ......................188 6.3.7 Software Reset........................... 188 6.3.8 Determination of Cold/Warm Start ................... 189 6.3.9 Determination of Reset Generation Source ................
Page 11 9.2.2 System Clock Control Register 2 (SCKCR2)................218 9.2.3 System Clock Control Register 3 (SCKCR3)................219 9.2.4 PLL Control Register (PLLCR) ....................220 9.2.5 PLL Control Register 2 (PLLCR2) ................... 221 9.2.6 External Bus Clock Control Register (BCKCR) ............... 222 9.2.7 Main Clock Oscillator Control Register (MOSCCR)..............
Page 12 9.10.2 Notes on Resonator........................239 9.10.3 Notes on Board Design......................239 9.10.4 Notes on Resonator Connect Pin ....................240 9.10.5 Notes on Sub-Clock Oscillator ....................240 Frequency Measurement Circuit (MCK) ..................242 10.1 Overview..........................242 10.2 Register Descriptions......................245 10.2.1 Counter-Clock Extension Register n (SCKn) (n = 1, 2)............
Page 13 11.5.1 Setting Operating Power Consumption Control Mode.............. 280 11.6 Low Power Consumption Modes ..................281 11.6.1 Sleep Mode ..........................281 11.6.1.1 Transition to Sleep Mode ....................281 11.6.1.2 Canceling Sleep Mode ..................... 281 11.6.1.3 Sleep Mode Return Clock Source Switching Function ........... 282 11.6.2 All-Module Clock Stop Mode ....................
Page 14 13.1.1 Protect Register (PRCR)......................296 Exception Handling ........................297 14.1 Exception Events ........................ 297 14.1.1 Undefined Instruction Exception....................297 14.1.2 Privileged Instruction Exception ....................297 14.1.3 Access Exceptions ........................297 14.1.4 Floating-Point Exception......................297 14.1.5 Reset ............................297 14.1.6 Non-Maskable Interrupt ......................298 14.1.7 Interrupt .............................
Page 15 15.2.11 IRQ Pin Digital Filter Setting Register 0 (IRQFLTC0) ............316 15.2.12 IRQ Pin Digital Filter Setting Register 1 (IRQFLTC1) ............317 15.2.13 Non-Maskable Interrupt Status Register (NMISR) ..............318 15.2.14 Non-Maskable Interrupt Enable Register (NMIER) ..............320 15.2.15 Non-Maskable Interrupt Status Clear Register (NMICLR) ............321 15.2.16 NMI Pin Interrupt Control Register (NMICR)................
Page 16 Buses ............................356 16.1 Overview..........................356 16.2 Description of Buses......................358 16.2.1 CPU Buses..........................358 16.2.2 Memory Buses........................... 358 16.2.3 Internal Main Buses........................359 16.2.4 Internal Peripheral Buses......................359 16.2.5 Write Buffer Function (Internal Peripheral Bus)............... 360 16.2.6 External Bus ..........................361 16.2.7 Parallel Operation ........................
Page 17 Memory-Protection Unit (MPU)..................... 415 17.1 Overview..........................415 17.1.1 Types of Access Control......................417 17.1.2 Regions for Access Control....................... 417 17.1.3 Background Region ........................417 17.1.4 Overlap between Regions......................417 17.1.5 Instructions and Data that Span Regions................... 417 17.2 Register Descriptions......................418 17.2.1 Region-n Start Page Number Register (RSPAGEn) (n = 0 to 7) ..........
Page 18 18.2.8 DMA Offset Register (DMOFR)....................445 18.2.9 DMA Transfer Enable Register (DMCNT)................445 18.2.10 DMA Software Start Register (DMREQ) ................. 446 18.2.11 DMA Status Register (DMSTS)....................447 18.2.12 DMA Activation Source Flag Control Register (DMCSL)............448 18.2.13 DMACA Module Activation Register (DMAST) ..............449 18.3 Operation ..........................
Page 19 19.2.6 DTC Transfer Count Register B (CRB) ..................477 19.2.7 DTC Control Register (DTCCR)....................477 19.2.8 DTC Vector Base Register (DTCVBR) ..................478 19.2.9 DTC Address Mode Register (DTCADMOD)................478 19.2.10 DTC Module Start Register (DTCST)..................479 19.2.11 DTC Status Register (DTCSTS)....................480 19.3 Sources of Activation ......................
Page 20 20.3.8 Driving Ability Control Register (DSCR)................. 516 20.4 Handling of Unused Pins ....................517 20.5 Usage Notes ........................517 20.5.1 Products with Fewer than 176 Pins ................... 517 Multi-Function Pin Controller (MPC) ..................... 518 21.1 Overview..........................518 21.2 Register Descriptions......................533 21.2.1 Write-Protect Register (PWPR)....................
Page 21 Multi-Function Timer Pulse Unit 2 (MTU2a).................. 568 22.1 Overview..........................568 22.2 Register Descriptions......................573 22.2.1 Timer Control Register (TCR) ....................573 22.2.2 Timer Mode Register (TMDR)....................576 22.2.3 Timer I/O Control Register (TIOR)................... 578 22.2.4 Timer Compare Match Clear Register (TCNTCMPCLR) ............589 22.2.5 Timer Interrupt Enable Register (TIER) ...................
Page 22 22.3.4 Cascaded Operation........................627 22.3.5 PWM Modes..........................632 22.3.6 Phase Counting Mode........................ 636 22.3.7 Reset-Synchronized PWM Mode ....................642 22.3.8 Complementary PWM Mode..................... 645 22.3.9 A/D Converter Start Request Delaying Function ..............673 22.3.10 External Pulse Width Measurement ..................676 22.3.11 Dead Time Compensation ......................
Page 23 22.6.23 Notes when Complementary PWM Mode Output Protection Functions are not Used ..... 701 22.6.24 Point for Caution Regarding MTU5.TCNT and MTU5.TGR Registers........701 22.6.25 Points for Caution to Prevent Malfunctions in Synchronous Clearing for Complementary PWM Mode..................... 702 22.6.26 Continuous Output of Interrupt Signal in Response to a Compare Match........
Page 24 24.2.7 Timer General Register A (TGRA) Timer General Register B (TGRB) Timer General Register C (TGRC) Timer General Register D (TGRD) ................... 773 24.2.8 Timer Start Register (TSTR) ..................... 774 24.2.9 Timer Synchronous Register (TSYR) ..................775 24.2.10 Noise Filter Control Register (NFCR)..................776 24.3 Operation ..........................
Page 25 Programmable Pulse Generator (PPG) ..................819 25.1 Overview..........................819 25.2 Register Descriptions......................822 25.2.1 PPG Trigger Select Register (PTRSLR) ................... 822 25.2.2 Next Data Enable Registers H (NDERH) Next Data Enable Registers L (NDERL) .................. 823 25.2.3 Output Data Registers H (PODRH) Output Data Registers L (PODRL) ...................
Page 26 26.4.5 Timing of the External Reset for TCNT..................864 26.4.6 Timing of Interrupt Signal Output on an Overflow..............865 26.5 Operation with Cascaded Connection ................865 26.5.1 16-Bit Count Mode........................865 26.5.2 Compare Match Count Mode ....................865 26.6 Interrupt Sources ........................ 866 26.6.1 Interrupt Sources and DTC Activation..................
Page 27 28.2.2 Second Counter (RSECCNT)....................882 28.2.3 Minute Counter (RMINCNT)....................882 28.2.4 Hour Counter (RHRCNT) ......................883 28.2.5 Day-of-Week Counter (RWKCNT) ..................884 28.2.6 Date Counter (RDAYCNT)....................... 885 28.2.7 Month Counter (RMONCNT) ....................885 28.2.8 Year Counter (RYRCNT)......................886 28.2.9 Second Alarm Register (RSECAR)................... 886 28.2.10 Minute Alarm Register (RMINAR) ..................
Page 28 28.3.8.5 Capturing the Time ......................912 28.4 Interrupt Sources ........................ 913 28.5 Usage Notes ........................914 28.5.1 Register Writing during Counting ..................... 914 28.5.2 Use of Periodic Interrupts......................914 28.5.3 RTCOUT (1-Hz) Output ......................915 28.5.4 Transitions to Low Power Consumption Modes after Setting Registers........915 28.5.5 Points for Caution When Writing to and Reading from Registers ..........
Page 29 30.3.1.2 Auto-Start Mode ......................941 30.3.2 Control over Writing to the IWDTCR, IWDTRCR, and IWDTCSTPR Registers....942 30.3.3 Refresh Operation........................943 30.3.4 Status Flags..........................945 30.3.5 Reset Output ..........................945 30.3.6 Interrupt Source ......................... 946 30.3.7 Reading the Down-Counter Value .................... 946 30.3.8 Correspondence between Option Function Select Register 0 (OFS0) and IWDT Registers ..
Page 30 31.2.24 DCP Control Register (DCPCTR)..................... 976 31.2.25 Pipe Window Select Register (PIPESEL) ................. 978 31.2.26 Pipe Configuration Register (PIPECFG)................... 979 31.2.27 Pipe Maximum Packet Size Register (PIPEMAXP) ..............981 31.2.28 Pipe Cycle Control Register (PIPEPERI).................. 982 31.2.29 PIPEn Control Registers (PIPEnCTR) (n = 1 to 9) ..............983 31.2.30 PIPEn Transaction Counter Enable Registers (PIPEnTRE) (n = 1 to 5)........
Page 31 31.3.5.4 DMA Transfers (D0FIFO and D1FIFO Ports) .............. 1016 31.3.6 Control Transfers (DCP) ......................1017 31.3.6.1 Control Transfers ......................1017 31.3.7 Bulk Transfers (PIPE1 to PIPE5) .................... 1018 31.3.8 Interrupt Transfers (PIPE6 to PIPE9)..................1018 31.3.9 Isochronous Transfers (PIPE1 and PIPE2)................1019 31.3.9.1 Error Detection in Isochronous Transfers ..............
Page 32 32.2.26 Control Field 0 Data Register (CF0DR).................. 1072 32.2.27 Control Field 0 Compare Enable Register (CF0CR)............... 1073 32.2.28 Control Field 0 Receive Data Register (CF0RR) ..............1073 32.2.29 Primary Control Field 1 Data Register (PCF1DR)..............1073 32.2.30 Secondary Control Field 1 Data Register (SCF1DR).............. 1074 32.2.31 Control Field 1 Compare Enable Register (CF1CR)...............
Page 33 32.7.2 Clock Synchronization ......................1112 32.7.3 SSDA Output Delay ........................ 1113 32.7.4 SCI Initialization (Simple I C Mode)..................1114 32.7.5 Operation in Master Transmission (Simple I C Mode) ............1115 32.7.6 Master Reception (Simple I C Mode) ..................1117 32.8 Operation in Simple SPI Mode ..................
Page 34 32.12.11 Limitations on Simple SPI Mode .................... 1145 32.12.12 Limitation 1 on Usage of the Extended Serial Mode Control Section ........1145 32.12.13 Limitation 2 on Usage of the Extended Serial Mode Control Section ........1146 C Bus Interface (RIIC) ......................1147 33.1 Overview...........................
Page 35 33.8.2 NACK Reception Transfer Suspension Function..............1198 33.8.3 Function to Prevent Failure to Receive Data................1199 33.9 Arbitration-Lost Detection Functions................. 1201 33.9.1 Master Arbitration-Lost Detection (MALE Bit) ..............1201 33.9.2 Function to Detect Loss of Arbitration during NACK Transmission (NALE Bit) ....1203 33.9.3 Slave Arbitration-Lost Detection (SALE Bit) .................
Page 36 34.2.14 Mailbox Search Mode Register (MSMR) ................1242 34.2.15 Mailbox Search Status Register (MSSR) ................1243 34.2.16 Channel Search Support Register (CSSR)................1244 34.2.17 Acceptance Filter Support Register (AFSR) ................1245 34.2.18 Error Interrupt Enable Register (EIER)................... 1246 34.2.19 Error Interrupt Factor Judge Register (EIFR)................1247 34.2.20 Receive Error Count Register (RECR)..................
Page 37 35.2.9 RSPI Data Control Register (SPDCR) ..................1284 35.2.10 RSPI Clock Delay Register (SPCKD)..................1285 35.2.11 RSPI Slave Select Negation Delay Register (SSLND) ............1286 35.2.12 RSPI Next-Access Delay Register (SPND)................1286 35.2.13 RSPI Control Register 2 (SPCR2)................... 1287 35.2.14 RSPI Command Registers 0 to 7 (SPCMD0 to SPCMD7) .............
Page 38 35.3.13 Slave Mode Operation ......................1337 35.3.14 Loopback Mode........................1339 35.3.15 Self-Diagnosis of Parity Bit Function ..................1340 35.3.16 Interrupt Sources........................1341 35.4 Usage Note........................1342 35.4.1 Setting Module-Stop Function....................1342 35.4.2 Cautionary Note on the Low Power Consumption Functions..........1342 35.4.3 Points to Note on Starting Transfer ..................
Page 39 36.4.3 Slave Reception ........................1373 36.4.4 Master Reception........................1374 36.4.5 Slave Transmission........................1375 36.5 Operation Timing ......................1376 36.5.1 Master Transmission........................ 1376 36.5.2 Slave Reception ........................1377 36.5.3 Master Reception........................1378 36.5.4 Slave Transmission........................1379 36.6 Interrupt Sources ......................1380 36.7 Usage Notes ........................
Page 40 38.2.14 A/D Sampling State Register 23 (ADSSTR23)............... 1407 38.3 Operation .......................... 1408 38.3.1 Scanning Operation ......................... 1408 38.3.2 Single Scan Mode........................1408 38.3.2.1 Basic Operation ......................1408 38.3.2.2 A/D Conversion when selecting Temperature Sensor Output/Internal Reference Voltage .......................... 1409 38.3.3 Continuous Scan Mode......................
Page 41 39.2.4 A/D Control Register 2 (ADCR2) ................... 1428 39.2.5 A/D Sampling State Register (ADSSTR)................1428 39.2.6 A/D Self-Diagnostic Register (ADDIAGR)................1429 39.3 Operation .......................... 1430 39.3.1 Single Channel Mode ......................1431 39.3.2 Scan Mode ..........................1432 39.3.2.1 Continuous Scan Mode ....................1432 39.3.2.2 Single Scan Mode ......................
Page 42 40.3 Operation .......................... 1455 40.3.1 Measure against Interference between D/A and A/D Conversion .......... 1456 40.4 Usage Notes ........................1457 40.4.1 Module-Stop Function Setting....................1457 40.4.2 Operation of the D/A Converter in Module-Stop State............1457 40.4.3 Operation of the D/A Converter in Software Standby Mode ..........1457 40.4.4 Note on Entering Deep Software Standby Mode ..............
Page 43 43.2.9 E2 DataFlash P/E Enable Register 1 (DFLWE1) ..............1481 43.2.10 FCU RAM Enable Register (FCURAME)................1482 43.2.11 Flash Status Register 0 (FSTATR0)..................1483 43.2.12 Flash Status Register 1 (FSTATR1)..................1485 43.2.13 Flash P/E Mode Entry Register (FENTRYR) ................. 1486 43.2.14 Flash Protection Register (FPROTR) ..................
Page 44 43.8.4 ID Code Protection (Boot Mode) .................... 1527 43.8.5 UB Code A ..........................1528 43.8.6 Configuration of Commands and Responses................1528 43.8.7 Inquiry/Selection Command Wait ................... 1529 43.8.8 ID Code Wait State........................1540 43.8.9 Programming/Erasure Command Wait ................... 1541 43.9 USB Boot Mode ........................
Page 45 45.9 Oscillation Stop Detection Timing..................1608 45.10 Battery Backup Function Characteristics................1608 45.11 ROM (Flash Memory for Code Storage) Characteristics ..........1609 45.12 E2 Flash Characteristics....................1610 Appendix 1. Port States in Each Processing Mode ................1612 Appendix 2. Package Dimensions ...................... 1615 REVISION HISTORY ...........................
Page 46 Features RX630 Group Renesas MCUs R01UH0040EJ0150 Rev.1.50 100-MHz 32-bit RX MCU, on-chip FPU, 165 DMIPS, Sep 28, 2012 up to 2-MB flash memory, USB 2.0 full-speed function interface, CAN, 10- & 12-bit A/D converter, RTC, up to 22 comms interfaces Features PLQP0176KB-A 24 ×...
Page 47: Overview
RX630 Group 1. Overview Overview Outline of Specifications Table 1.1 lists the specifications in outline, and Table 1.2 lists the functions of products. Table 1.1 shows the outline of maximum specifications, and the number of peripheral module channels differs depending on the pin number on the package and the ROM capacity. For details, see Table 1.2, Comparison of Functions for Different Packages.
Page 48 RX630 Group 1. Overview Table 1.1 Outline of Specifications (2/5) Classification Module/Function Description  Module stop function Low power Low power  Four low power consumption modes consumption consumption facilities Sleep mode, all-module clock stop mode, software standby mode, and deep software standby mode ...
Page 49 RX630 Group 1. Overview Table 1.1 Outline of Specifications (3/5) Classification Module/Function Description  (16 bits × 6 channels) × 2 units Timers 16-bit timer pulse unit  Maximum of 16 pulse-input/output possible (TPUa)  Select from among seven or eight counter-input clock signals for each channel ...
Page 50 RX630 Group 1. Overview Table 1.1 Outline of Specifications (4/5) Classification Module/Function Description  Includes a UDC (USB Device Controller) and transceiver for USB 2.0 Communication USB 2.0 function  Single port function module (USBa)  Compliance with the USB 2.0 specification ...
Page 51 RX630 Group 1. Overview Table 1.1 Outline of Specifications (5/5) Classification Module/Function Description  1 unit (1 unit × 8 channels) 10-bit A/D converter (ADb)  10-bit resolution  Conversion time: 1.0 µs per channel (in operation with PCLK at 50 MHz) ...
Page 52 RX630 Group 1. Overview Table 1.2 Comparison of Functions for Different Packages Functions RX630 Group 177 Pins, 145 Pins, Package 176 Pins 144 Pins 100 Pins 80 Pins External bus External bus width 32 bits 16 bits Not supported DMA controller Ch.
Page 53: List Of Products
Table 1.3 List of Products (1/2) Operating Frequency Group Part No. Package ROM Capacity RAM Capacity E2 Data Flash (Max.) RX630 R5F56307CDFN PLQP0080KB-A* 384 Kbytes 64 Kbytes 32 Kbytes 100 MHz R5F56307DDFN PLQP0080KB-A* 384 Kbytes 64 Kbytes 32 Kbytes 100 MHz...
Page 54 RX630 Group 1. Overview Table 1.3 List of Products (2/2) Operating Frequency Group Part No. Package ROM Capacity RAM Capacity E2 Data Flash (Max.) RX630 R5F5630DDDLK PTLG0145KA-A* 1.5 Mbytes 128 Kbytes 32 Kbytes 100 MHz R5F5630DCDFC PLQP0176KB-A 1.5 Mbytes 128 Kbytes 32 Kbytes 100 MHz R5F5630DDDFC...
Page 55 7: 384 Kbytes/64 Kbytes/32 Kbytes Group name 30: RX630 Group Series name RX600 Series Type of memory F: Flash memory version Renesas MCU Renesas semiconductor product Figure 1.1 How to Read the Product Part Number R01UH0040EJ0150 Rev.1.50 Page 55 of 1654 Sep 28, 2012...
Page 56: Block Diagram
RX630 Group 1. Overview Block Diagram Figure 1.2 shows a block diagram. E2 DataFlash WDTA IWDTa SCIc × 12 channels SCId × 1 channel USBa × 1 port Port 0 RSPI (unit 0) Port 1 RSPI (unit 1) RSPI (unit 2) Port 2 CAN ×...
Page 57: Pin Functions
RX630 Group 1. Overview Pin Functions Table 1.4 lists the pin functions. Table 1.4 Pin Functions (1/5) Classifications Pin Name Description Power supply Input Power supply pin. Connect it to the system power supply. Connect this pin to VSS via a 0.1-µF capacitor. The capacitor should be placed close to the pin Connect this pin to VSS via a 0.1- ...
Page 58 RX630 Group 1. Overview Table 1.4 Pin Functions (2/5) Classifications Pin Name Description Bus control Output Strobe signal which indicates that reading from the external bus interface space is in progress Output Strobe signal which indicates that writing to the external bus interface space is in progress, in 1-write strobe mode WR0# to WR3# Output...
Page 59 RX630 Group 1. Overview Table 1.4 Pin Functions (3/5) Classifications Pin Name Description 16-bit timer pulse unit TIOCA0, TIOCB0 The TGRA0 to TGRD0 input capture input/output compare output/ TIOCC0, TIOCD0 PWM output pins TIOCA1, TIOCB1 The TGRA1 and TGRB1 input capture input/output compare output/ PWM output pins TIOCA2, TIOCB2 The TGRA2 and TGRB2 input capture input/output compare output/...
Page 60 RX630 Group 1. Overview Table 1.4 Pin Functions (4/5) Classifications Pin Name Description  Asynchronous mode/clock synchronous mode Serial communications interface (SCId) SCK12 Input/output pin for the clock RXD12 Input Input pin for received data TXD12 Output Output pin for transmitted data CTS12# Input Input pin for controlling the start of transmission and reception...
Page 61 RX630 Group 1. Overview Table 1.4 Pin Functions (5/5) Classifications Pin Name Description 10-bit A/D converter AN0 to AN7 Input Input pins for the analog signals to be processed by the A/D converter ANEX0 Output Extended analog output pin ANEX1 Input Extended analog input pin ADTRG#...
Page 62: Pin Assignments
RX630 Group 1. Overview Pin Assignments Figure 1.3 to Figure 1.10 show the pin assignments. Table 1.5 to Table 1.11 show the lists of pins and pin functions. RX630 Group PTLG0177KA-A (177-Pin TFLGA) (Upper perspective view) VSS_ USB0_ VCC_ USB0_ BSCANP VREFL0 VREFH0...
Page 63 RX630 Group 1. Overview RX630 Group PLBG0176GA-A (176-Pin LFBGA) (Upper perspective view) VSS_ USB0_ VCC_ USB0_ BSCANP VREFL0 VREFH0 RES# AVCC0 VREFH EMLE XCOUT AVSS0 VREFL VBATT XCIN XTAL EXTAL Note: • This figure indicates the power supply pins and I/O port pins. For the pin configuration, see Table 1.5, List of Pins and Pin Functions (177-Pin TFLGA, 176-Pin LFBGA).
Page 64 RX630 Group 1. Overview RX630 Group PLQP0176KB-A (176-Pin LQFP) (Top View) VSS_USB USB0_DP USB0_DM VCC_USB VREFL0 VREFH0 AVCC0 Note: • This figure indicates the power supply pins and I/O port pins. For the pin configuration, see Table 1.6, List of Pins and Pin Functions (176-Pin LQFP).
Page 65 RX630 Group 1. Overview RX630 Group PTLG0145KA-A (145-Pin TFLGA) (Upper perspective view) VSS_ USB0_ VCC_ USB0_ VREFL0 EMLE VBATT BSCANP VREFH0 AVCC0 XCOUT RES# AVSS0 VREFH VREFL XCIN XTAL EXTAL Note: • This figure indicates the power supply pins and I/O port pins. For the pin configuration, see Table 1.7, List of Pins and Pin Functions (145-Pin TFLGA).
Page 66 RX630 Group 1. Overview RX630 Group PLQP0144KA-A (144-Pin LQFP) (Top View) VSS_USB USB0_DP USB0_DM VCC_USB VREFL0 VREFH0 AVCC0 Note: • This figure indicates the power supply pins and I/O port pins. For the pin configuration, see Table 1.8, List of Pins and Pin Functions (144-Pin LQFP).
Page 67 RX630 Group 1. Overview RX630 Group PTLG0100KA-A (100-Pin TFLGA) (Top View) VCC_ USB0_ VSS_ USB0_ 4 VREFL0 VREFH0 VBATT AVCC0 RES# 2 VREFH AVSS0 VREFL XCOUT EMLE XCIN XTAL EXTAL Note: • This figure indicates the power supply pins and I/O port pins. For the pin configuration, see Table 1.7, List of Pins and Pin Functions (145-Pin TFLGA).
Page 68 RX630 Group 1. Overview RX630 Group PLQP0100KB-A VSS_USB (100-Pin LQFP) USB0_DP USB0_DM (Top View) VCC_USB VREFL0 VREFH0 AVCC0 AVSS0 Note: • This figure indicates the power supply pins and I/O port pins. For the pin configuration, see Table 1.10, List of Pins and Pin Functions (100-Pin LQFP). Figure 1.9 Pin Assignment (100-Pin LQFP) R01UH0040EJ0150 Rev.1.50...
Page 69 RX630 Group 1. Overview RX630 Group VSS_USB PLQP0080KB-A USB0_DP (80-Pin LQFP) USB0_DM VCC_USB (Top View) VREFL0 VREFH0 AVCC0 AVSS0 Note: • This figure indicates the power supply pins and I/O port pins. For the pin configuration, see Table 1.11, List of Pins and Pin Functions (80-Pin LQFP). Figure 1.10 Pin Assignment (80-Pin LQFP) R01UH0040EJ0150 Rev.1.50...
Page 70 RX630 Group 1. Overview Table 1.5 List of Pins and Pin Functions (177-Pin TFLGA, 176-Pin LFBGA) (1/5) Pin Number Timer Communications 177-Pin TFLGA Power Supply 176-Pin Clock System (MTU, TPU, TMR, PPG, (SCIc, SCId, RSPI, RIIC, S12AD, LFBGA Control I/O Port RTC, POE) CAN, IEB, USB) Interrupt...
Page 71 RX630 Group 1. Overview Table 1.5 List of Pins and Pin Functions (177-Pin TFLGA, 176-Pin LFBGA) (2/5) Pin Number Timer Communications 177-Pin TFLGA Power Supply 176-Pin Clock System (MTU, TPU, TMR, PPG, (SCIc, SCId, RSPI, RIIC, S12AD, LFBGA Control I/O Port RTC, POE) CAN, IEB, USB) Interrupt...
Page 72 RX630 Group 1. Overview Table 1.5 List of Pins and Pin Functions (177-Pin TFLGA, 176-Pin LFBGA) (3/5) Pin Number Timer Communications 177-Pin TFLGA Power Supply 176-Pin Clock System (MTU, TPU, TMR, PPG, (SCIc, SCId, RSPI, RIIC, S12AD, LFBGA Control I/O Port RTC, POE) CAN, IEB, USB) Interrupt...
Page 73 RX630 Group 1. Overview Table 1.5 List of Pins and Pin Functions (177-Pin TFLGA, 176-Pin LFBGA) (4/5) Pin Number Timer Communications 177-Pin TFLGA Power Supply 176-Pin Clock System (MTU, TPU, TMR, PPG, (SCIc, SCId, RSPI, RIIC, S12AD, LFBGA Control I/O Port RTC, POE) CAN, IEB, USB) Interrupt...
Page 74 RX630 Group 1. Overview Table 1.5 List of Pins and Pin Functions (177-Pin TFLGA, 176-Pin LFBGA) (5/5) Pin Number Timer Communications 177-Pin TFLGA Power Supply 176-Pin Clock System (MTU, TPU, TMR, PPG, (SCIc, SCId, RSPI, RIIC, S12AD, LFBGA Control I/O Port RTC, POE) CAN, IEB, USB) Interrupt...
Page 75 RX630 Group 1. Overview Table 1.6 List of Pins and Pin Functions (176-Pin LQFP) (1/5) Pin Number Timer Communications Power Supply 176-Pin Clock System (MTU, TPU, TMR, PPG, (SCIc, SCId, RSPI, RIIC, S12AD, LQFP Control I/O Port RTC, POE) CAN, IEB, USB) Interrupt AD, DA AVSS0...
Page 76 RX630 Group 1. Overview Table 1.6 List of Pins and Pin Functions (176-Pin LQFP) (2/5) Pin Number Timer Communications Power Supply 176-Pin Clock System (MTU, TPU, TMR, PPG, (SCIc, SCId, RSPI, RIIC, S12AD, LQFP Control I/O Port RTC, POE) CAN, IEB, USB) Interrupt AD, DA MTIOC3D/MTCLKD/...
Page 77 RX630 Group 1. Overview Table 1.6 List of Pins and Pin Functions (176-Pin LQFP) (3/5) Pin Number Timer Communications Power Supply 176-Pin Clock System (MTU, TPU, TMR, PPG, (SCIc, SCId, RSPI, RIIC, S12AD, LQFP Control I/O Port RTC, POE) CAN, IEB, USB) Interrupt AD, DA A23/CS0#...
Page 78 RX630 Group 1. Overview Table 1.6 List of Pins and Pin Functions (176-Pin LQFP) (4/5) Pin Number Timer Communications Power Supply 176-Pin Clock System (MTU, TPU, TMR, PPG, (SCIc, SCId, RSPI, RIIC, S12AD, LQFP Control I/O Port RTC, POE) CAN, IEB, USB) Interrupt AD, DA MTIOC0D/MTCLKD/...
Page 79 RX630 Group 1. Overview Table 1.6 List of Pins and Pin Functions (176-Pin LQFP) (5/5) Pin Number Timer Communications Power Supply 176-Pin Clock System (MTU, TPU, TMR, PPG, (SCIc, SCId, RSPI, RIIC, S12AD, LQFP Control I/O Port RTC, POE) CAN, IEB, USB) Interrupt AD, DA A22/D22...
Page 80 RX630 Group 1. Overview Table 1.7 List of Pins and Pin Functions (145-Pin TFLGA) (1/4) Pin Number Timer Communications Power Supply 145-Pin Clock System (MTU, TPU, TMR, PPG, (SCIc, SCId, RSPI, RIIC, S12AD, TFLGA Control I/O Port RTC, POE) CAN, IEB, USB) Interrupt AD, DA AVSS0...
Page 81 RX630 Group 1. Overview Table 1.7 List of Pins and Pin Functions (145-Pin TFLGA) (2/4) Pin Number Timer Communications Power Supply 145-Pin Clock System (MTU, TPU, TMR, PPG, (SCIc, SCId, RSPI, RIIC, S12AD, TFLGA Control I/O Port RTC, POE) CAN, IEB, USB) Interrupt AD, DA CTS7#/RTS7#/SS7#...
Page 82 RX630 Group 1. Overview Table 1.7 List of Pins and Pin Functions (145-Pin TFLGA) (3/4) Pin Number Timer Communications Power Supply 145-Pin Clock System (MTU, TPU, TMR, PPG, (SCIc, SCId, RSPI, RIIC, S12AD, TFLGA Control I/O Port RTC, POE) CAN, IEB, USB) Interrupt AD, DA TIOCB2/PO23...
Page 83 RX630 Group 1. Overview Table 1.7 List of Pins and Pin Functions (145-Pin TFLGA) (4/4) Pin Number Timer Communications Power Supply 145-Pin Clock System (MTU, TPU, TMR, PPG, (SCIc, SCId, RSPI, RIIC, S12AD, TFLGA Control I/O Port RTC, POE) CAN, IEB, USB) Interrupt AD, DA A21/CS2#/...
Page 84 RX630 Group 1. Overview Table 1.8 List of Pins and Pin Functions (144-Pin LQFP) (1/4) Pin Number Timer Communications Power Supply 144-Pin Clock System (MTU, TPU, TMR, PPG, (SCIc, SCId, RSPI, RIIC, S12AD, LQFP Control I/O Port RTC, POE) CAN, IEB, USB) Interrupt AD, DA AVSS0...
Page 85 RX630 Group 1. Overview Table 1.8 List of Pins and Pin Functions (144-Pin LQFP) (2/4) Pin Number Timer Communications Power Supply 144-Pin Clock System (MTU, TPU, TMR, PPG, (SCIc, SCId, RSPI, RIIC, S12AD, LQFP Control I/O Port RTC, POE) CAN, IEB, USB) Interrupt AD, DA MTIOC3A/MTIOC3B/...
Page 86 RX630 Group 1. Overview Table 1.8 List of Pins and Pin Functions (144-Pin LQFP) (3/4) Pin Number Timer Communications Power Supply 144-Pin Clock System (MTU, TPU, TMR, PPG, (SCIc, SCId, RSPI, RIIC, S12AD, LQFP Control I/O Port RTC, POE) CAN, IEB, USB) Interrupt AD, DA CS4#...
Page 87 RX630 Group 1. Overview Table 1.8 List of Pins and Pin Functions (144-Pin LQFP) (4/4) Pin Number Timer Communications Power Supply 144-Pin Clock System (MTU, TPU, TMR, PPG, (SCIc, SCId, RSPI, RIIC, S12AD, LQFP Control I/O Port RTC, POE) CAN, IEB, USB) Interrupt AD, DA D11[A11/D11]...
Page 88 RX630 Group 1. Overview Table 1.9 List of Pins and Pin Functions (100-Pin TFLGA) (1/3) Pin Number Timer Communications Power Supply 100-Pin Clock System (MTU, TPU, TMR, PPG, (SCIc, SCId, RSPI, RIIC, S12AD, TFLGA Control I/O Port RTC, POE) CAN, IEB, USB) Interrupt AD, DA IRQ13...
Page 89 RX630 Group 1. Overview Table 1.9 List of Pins and Pin Functions (100-Pin TFLGA) (2/3) Pin Number Timer Communications Power Supply 100-Pin Clock System (MTU, TPU, TMR, PPG, (SCIc, SCId, RSPI, RIIC, S12AD, TFLGA Control I/O Port RTC, POE) CAN, IEB, USB) Interrupt AD, DA TRST#...
Page 90 RX630 Group 1. Overview Table 1.9 List of Pins and Pin Functions (100-Pin TFLGA) (3/3) Pin Number Timer Communications Power Supply 100-Pin Clock System (MTU, TPU, TMR, PPG, (SCIc, SCId, RSPI, RIIC, S12AD, TFLGA Control I/O Port RTC, POE) CAN, IEB, USB) Interrupt AD, DA MTIOC0B/MTCLKB/...
Page 91 RX630 Group 1. Overview Table 1.10 List of Pins and Pin Functions (100-Pin LQFP) (1/3) Pin Number Timer Communications Power Supply 100-Pin Clock System (MTU, TPU, TMR, PPG, (SCIc, SCId, RSPI, RIIC, S12AD, LQFP Control I/O Port RTC, POE) CAN, IEB, USB) Interrupt AD, DA VREFH...
Page 92 RX630 Group 1. Overview Table 1.10 List of Pins and Pin Functions (100-Pin LQFP) (2/3) Pin Number Timer Communications Power Supply 100-Pin Clock System (MTU, TPU, TMR, PPG, (SCIc, SCId, RSPI, RIIC, S12AD, LQFP Control I/O Port RTC, POE) CAN, IEB, USB) Interrupt AD, DA MTIOC0B/TIOCA5/TMO3/...
Page 93 RX630 Group 1. Overview Table 1.10 List of Pins and Pin Functions (100-Pin LQFP) (3/3) Pin Number Timer Communications Power Supply 100-Pin Clock System (MTU, TPU, TMR, PPG, (SCIc, SCId, RSPI, RIIC, S12AD, LQFP Control I/O Port RTC, POE) CAN, IEB, USB) Interrupt AD, DA MTIOC0D/MTCLKD/...
Page 94 RX630 Group 1. Overview Table 1.11 List of Pins and Pin Functions (80-Pin LQFP) (1/3) Pin Number Timer Communications Power Supply 100-Pin Clock System (MTU, TPU, TMR, PPG, (SCIc, SCId, RSPI, RIIC, S12AD, LQFP Control I/O Port RTC, POE) CAN, IEB, USB) Interrupt AD, DA VREFH...
Page 95 RX630 Group 1. Overview Table 1.11 List of Pins and Pin Functions (80-Pin LQFP) (2/3) Pin Number Timer Communications Power Supply 100-Pin Clock System (MTU, TPU, TMR, PPG, (SCIc, SCId, RSPI, RIIC, S12AD, LQFP Control I/O Port RTC, POE) CAN, IEB, USB) Interrupt AD, DA MTIOC3B/MTCLKD/...
Page 96 RX630 Group 1. Overview Table 1.11 List of Pins and Pin Functions (80-Pin LQFP) (3/3) Pin Number Timer Communications Power Supply 100-Pin Clock System (MTU, TPU, TMR, PPG, (SCIc, SCId, RSPI, RIIC, S12AD, LQFP Control I/O Port RTC, POE) CAN, IEB, USB) Interrupt AD, DA IRQ9-DS...
Page 97: Cpu
RX630 Group 2. CPU The RX630 Group is an MCU with the high-speed, high-performance RX CPU as its core. A variable-length instruction format has been adopted for the RX CPU. Allocating the more frequently used instructions to the shorter instruction lengths facilitates the development of efficient programs that take up less memory. The CPU has 73 basic instructions and 8 floating-point operation instructions, and nine DSP instructions, for a total of 90 instructions.
Page 98: Register Set Of The Cpu
RX630 Group 2. CPU Register Set of the CPU The RX CPU has sixteen general-purpose registers, nine control registers, and one accumulator used for DSP instructions. General-purpose register R0 (SP)* Control register (Interrupt stack pointer) (User stack pointer) INTB (Interrupt table register) (Program counter) (Processor status word) (Backup PC)
Page 99: General-Purpose Registers (R0 To R15)
RX630 Group 2. CPU 2.2.1 General-Purpose Registers (R0 to R15) This CPU has sixteen general-purpose registers (R0 to R15). R1 to R15 can be used as data registers or address registers. R0, a general-purpose register, also functions as the stack pointer (SP). The stack pointer is switched to operate as the interrupt stack pointer (ISP) or user stack pointer (USP) by the value of the stack pointer select bit (U) in the processor status word (PSW).
Page 100: Program Counter (Pc)
RX630 Group 2. CPU 2.2.2.3 Program Counter (PC) Contents of addresses FFFFFFFCh to FFFFFFFFh Value after reset: The program counter (PC) indicates the address of the instruction being executed. 2.2.2.4 Processor Status Word (PSW) — — — — IPL[3:0] — —...
Page 101: Backup Pc (Bpc)
RX630 Group 2. CPU Symbol Bit Name Description b31 to b28 — Reserved These bits are read as 0. The write value should be 0. Note 1. In user mode, writing to the IPL[3:0], PM, U, and I bits by an MVTC or a POPC instruction is ignored. Writing to the IPL[3:0] bits by an MVTIPL instruction generates a privileged instruction exception.
Page 102: Backup Psw (Bpsw)
RX630 Group 2. CPU 2.2.2.6 Backup PSW (BPSW) Undefined Value after reset: The backup PSW (BPSW) is provided to speed up response to interrupts. After a fast interrupt has been generated, the contents of the processor status word (PSW) are saved in the BPSW. The allocation of bits in the BPSW corresponds to that in the PSW.
Page 103 RX630 Group 2. CPU Symbol Bit Name Description — Reserved This bit is read as 0. The write value should be 0. Invalid Operation Exception Enable 0: Invalid operation exception is masked. 1: Invalid operation exception is enabled. Overflow Exception Enable 0: Overflow exception is masked.
Page 104 RX630 Group 2. CPU (1) Rounding to the nearest value is specified as the default mode and returns the most accurate value. (2) Modes such as rounding towards 0, rounding towards +, and rounding towards – are used to ensure precision when interval arithmetic is employed.
Page 105: Register Associated With Dsp Instructions
RX630 Group 2. CPU 2.2.3 Register Associated with DSP Instructions 2.2.3.1 Accumulator (ACC) Range for reading by MVFACMI b48 b47 b16 b15 Range for reading and writing by MVTACHI and MVFACHI Range for writing by MVTACLO Value after reset: Undefined The accumulator (ACC) is a 64-bit register used for DSP instructions.
Page 106: Switching Between Processor Modes
RX630 Group 2. CPU 2.3.4 Switching Between Processor Modes Manipulating the processor mode select bit (PM) in the processor status word (PSW) switches the processor mode. However, rewriting to the PM bit by executing an MVTC or a POPC instruction is prohibited. Switch the processor mode by following the procedures described below.
Page 107: Endian
RX630 Group 2. CPU Endian For the RX CPU, instructions are little endian, but the treatment of data is selectable as little or big endian. 2.5.1 Switching the Endian As arrangements of bytes, the RX630 Group supports both big endian, where the higher-order byte (MSB) is at location 0, and little endian, where the lower-order byte (LSB) is at location 0.
Page 108 RX630 Group 2. CPU Table 2.3 32-Bit Write Operations when Little Endian has been Selected Operation Address Writing a 32-bit unit Writing a 32-bit unit Writing a 32-bit unit Writing a 32-bit unit Writing a 32-bit unit of dest to address 0 to address 1 to address 2 to address 3...
Page 109 RX630 Group 2. CPU Table 2.6 16-Bit Read Operations when Big Endian has been Selected Operation Reading Reading Reading Reading Reading Reading Reading Address a 16-bit unit from a 16-bit unit from a 16-bit unit from a 16-bit unit from a 16-bit unit from a 16-bit unit from a 16-bit unit from...
Page 110: Access To I/O Registers
RX630 Group 2. CPU Table 2.10 8-Bit Read Operations when Big Endian has been Selected Operation Reading an 8-bit unit Reading an 8-bit unit Reading an 8-bit unit Reading an 8-bit unit Address of src from address 0 from address 1 from address 2 from address 3 Address 0...
Page 111: Data Arrangement
RX630 Group 2. CPU 2.5.4 Data Arrangement 2.5.4.1 Data Arrangement in Registers Figure 2.2 shows the relation between the sizes of registers and bit numbers. Byte (8-bit) data Word (16-bit) data Longword (32-bit) data Figure 2.2 Data Arrangement in Registers 2.5.4.2 Data Arrangement in Memory Data in memory have three sizes: byte (8-bit), word (16-bit), and longword (32-bit).
Page 112: Vector Table
RX630 Group 2. CPU Vector Table There are two types of vector table: fixed and relocatable. Each vector in the vector table consists of four bytes and specifies the address where the corresponding exception handling routine starts. 2.6.1 Fixed Vector Table The fixed vector table is allocated to a fixed address range.
Page 113: Operation Of Instructions
RX630 Group 2. CPU INTB IntBase IntBase+4 IntBase+8 Interrupt vectors are allocated in this order. IntBase+1020 Figure 2.5 Relocatable Vector Table Operation of Instructions 2.7.1 Data Prefetching by the RMPA Instruction and the String-Manipulation Instructions The RMPA instruction and the string-manipulation instructions except the SSTR instruction (that is, SCMPU, SMOVB, SMOVF, SMOVU, SUNTIL, and SWHILE instructions) may prefetch data from the memory to speed up the read processing.
Page 114 RX630 Group 2. CPU (2) D stage (decoding stage) The CPU decodes instructions in the D stage and converts them into micro-operations. The CPU reads the register information (RF) in this stage and executes a bypass process (BYP) if the result of the preceding instruction will be used in a subsequent instruction.
Page 115: Instructions And Pipeline Processing
RX630 Group 2. CPU 2.8.2 Instructions and Pipeline Processing The operands in the table below indicate the following meaning. #IMM: Immediate flag: bit, flag Rs, Rs2, Rd, Rd2, Ri, Rb: General-purpose register CR: Control register dsp: displacement pcdsp: displacement 2.8.2.1 Instructions Converted into Single Micro-Operation and Pipeline Processing The table below lists the instructions that are converted into a single micro-operation.
Page 116 RX630 Group 2. CPU Figure 2.7 to Figure 2.9 show the operation of instructions that are converted into a basic single micro-operation. 4 stages ADD R1, R2 Note: • Multi-cycle instructions (DIV, DIVU) are executed in multiple cycles in the E stage. DIV R3, R4 Figure 2.7 Operation for Register-Register, Immediate-Register...
Page 117: Instructions Converted Into Multiple Micro-Operations And Pipeline Processing
RX630 Group 2. CPU 2.8.2.2 Instructions Converted into Multiple Micro-Operations and Pipeline Processing The table below lists the instructions that are converted into multiple micro-operations. The number of cycles in the table indicates the number of cycles during no-wait memory access. Table 2.14 Instructions that are Converted into Multiple Micro-Operations (1/2) Mnemonic (indicates the common operation when...
Page 118 RX630 Group 2. CPU Table 2.14 Instructions that are Converted into Multiple Micro-Operations (2/2) Mnemonic (indicates the common operation when Reference Instruction the size is omitted) Figure Number of Cycles  SCMPU String manipulation instructions* — 2+4×floor(n/4)+4×(n%4) n: Number of comparison bytes* ...
Page 119 RX630 Group 2. CPU Figure 2.10 to Figure 2.15 show the operation of instructions that are converted into basic multiple micro-operations. Note: • mop: Micro-operation, stall: Pipeline stall Bypass process ADD [R1], R2 (mop1) load stall (mop2) add Figure 2.10 Arithmetic/Logic Instruction (Memory Source Operand) Load data Bit manipulation,...
Page 120: Pipeline Basic Operation
RX630 Group 2. CPU 2.8.2.3 Pipeline Basic Operation In the ideal pipeline processing, each stage is executed in one cycle, though all instructions may not be pipelined in due to the processing in each stage and the branch execution. The CPU controls the pipeline stage with the IF stage in the unit of instructions, while the D and subsequent stages in the unit of micro-operations.
Page 121 RX630 Group 2. CPU (2) Pipeline Flow with no Stall (a) Bypass process Even when the result of the preceding instruction will be used in a subsequent instruction, the operation processing between registers is pipelined in by the bypass process. ADD R1, R2 (mop) add Bypass process...
Page 122: Calculation Of The Instruction Processing Time
RX630 Group 2. CPU (d) When the load data is not used by the subsequent instruction When the load data is not used by the subsequent instruction, the subsequent operations are in fact executed earlier and the operation processing ends (out-of-order completion). (mop) load MOV [R1], R2 ADD R4, R5...
Page 123: Operating Modes
RX630 Group 3. Operating Modes Operating Modes Operating Mode Types and Selection There are two types of operating-mode selection: one is be selected by the level on pins at the time of release from the reset state, and the other is selected by software after release from the reset state. Table 3.1 shows the relationship between levels on the mode-setting pins (MD, PC7) on release from the reset state and the operating mode selected at that time.
Page 124: Register Descriptions
RX630 Group 3. Operating Modes Register Descriptions 3.2.1 Mode Monitor Register (MDMONR) Address(es): 0008 0000h — — — — — — — — — — — — — — — Value after reset: 0/1* Symbol Bit Name Description MD Pin Status Flag 0: The MD pin is low.
Page 125: System Control Register 0 (Syscr0)
RX630 Group 3. Operating Modes 3.2.3 System Control Register 0 (SYSCR0) Address(es): 0008 0006h KEY[7:0] — — — — — — EXBE ROME Value after reset: Symbol Bit Name Description ROME On-Chip ROM Enable 0: The on-chip ROM is disabled. 1: The on-chip ROM is enabled.
Page 126: System Control Register 1 (Syscr1)
RX630 Group 3. Operating Modes 3.2.4 System Control Register 1 (SYSCR1) Address(es): 0008 0008h — — — — — — — — — — — — — — — RAME Value after reset: Symbol Bit Name Description RAME RAM Enable 0: The RAM is disabled.
Page 127: Details Of Operating Modes
RX630 Group 3. Operating Modes Details of Operating Modes 3.3.1 Single-Chip Mode In single-chip mode, the external bus is disabled (SYSCR0.EXBE bit = 0) so that all I/O port pins are available for use as input or output port pins, inputs or outputs for peripheral functions, or as interrupt inputs. If the high level is on the MD pin at the time of release from the reset state, the chip starts in single-chip mode.
Page 128 RX630 Group 3. Operating Modes After programming the prescribed values for UB code A and the UB code B, the chip starts up in user boot mode if the low level is on the MD pin and the high level is on the PC7 pin on release from the reset state. For UB code A and UB code b, see section 7, Option-Setting Memory .
Page 129: Transitions Of Operating Modes
RX630 Group 3. Operating Modes Transitions of Operating Modes 3.4.1 Operating Mode Transitions Determined by the Mode-Setting Pins Figure 3.1 shows operating mode transitions determined by the settings of the MD pin and the PC7 pin. Reset MD=High RES#=High RES#=Low MD=Low RES#=Low PC7=High...
Page 130: Operating Mode Transitions According To Register Setting
RX630 Group 3. Operating Modes 3.4.2 Operating Mode Transitions According to Register Setting Figure 3.2 shows operating mode transitions according to the setting of the ROME and EXBE bits in SYSCR0. Release from reset Single-chip mode User boot mode EXBE=1 On-chip ROM enabled extended mode On-chip ROM: Enabled (ROME = 1) On-chip ROM: Enabled (ROME = 1)
Page 131: Address Space
RX630 Group 4. Address Space Address Space Address Space This LSI has a 4-Gbyte address space, consisting of the range of addresses from 0000 0000h to FFFF FFFFh. That is, linear access to an address space of up to 4 Gbytes is possible, and this contains both program and data areas. Figure 4.1 shows the memory maps in the respective operating modes.
Page 132 RX630 Group 4. Address Space On-chip ROM enabled On-chip ROM disabled Single-chip mode* extended mode extended mode 0000 0000h 0000 0000h 0000 0000h RAM* RAM* RAM* 0002 0000h 0002 0000h 0002 0000h Reserved area* Reserved area* Reserved area* 0008 0000h 0008 0000h 0008 0000h Peripheral I/O registers...
Page 133: External Address Space
RX630 Group 4. Address Space External Address Space The external address space is divided into up to eight CS areas (CS0 to CS7), each corresponding to the CSn# signal output from a CSn# (n = 0 to 7) pin. Figure 4.2 shows the address ranges corresponding to the individual CS areas (CS0 to CS7) in on-chip ROM disabled extended mode.
Page 134: I/O Registers
RX630 Group 5. I/O Registers I/O Registers This section gives information on the on-chip I/O register addresses. The information is given as shown below. Notes on writing to registers are also given at the end. (1) I/O register addresses (address order) ...
Page 135 RX630 Group 5. I/O Registers  Longword-size I/O registers MOV.L #SFR_ADDR, R1 MOV.L #SFR_DATA, [R1] [R1].L, R1 ;; Next process If multiple registers are written to and a subsequent instruction should be executed after the write operations are entirely completed, only read the I/O register that was last written to and execute the operation using the value; it is not necessary to read or execute operation for all the registers that were written to.
Page 136: I/O Register Addresses (Address Order)
RX630 Group 5. I/O Registers I/O Register Addresses (Address Order) Table 5.1 List of I/O Registers (Address Order) (1/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page...
Page 137 RX630 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (2/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page 0008 2014h DMAC0 DMA address mode register DMAMD...
Page 138 RX630 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (3/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page 0008 3018h CS1 wait control register 2 CS1WCR2 1, 2 BCLK...
Page 139 RX630 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (4/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page 0008 6438h Region-7 start page number register RSPAGE7 1ICLK...
Page 140 RX630 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (5/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page 0008 7044h Interrupt request register 068 IR068 2 ICLK...
Page 141 RX630 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (6/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page 0008 7093h Interrupt request register 147 IR147 2 ICLK...
Page 142 RX630 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (7/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page 0008 70C7h Interrupt request register 199 IR199 2 ICLK...
Page 143 RX630 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (8/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page 0008 7127h DTC activation enable register 039 DTCER039 2 ICLK...
Page 144 RX630 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (9/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page 0008 719Ah DTC activation enable register 154 DTCER154 2 ICLK...
Page 145 RX630 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (10/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page 0008 71F1h DTC activation enable register 241 DTCER241 2 ICLK...
Page 146 RX630 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (11/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page 0008 7327h Interrupt source priority register 039 IPR039 2 ICLK...
Page 147 RX630 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (12/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page 0008 73A1h Interrupt source priority register 161 IPR161 2 ICLK...
Page 148 RX630 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (13/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page 0008 7505h IRQ control register 5 IRQCR5 2 ICLK...
Page 149 RX630 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (14/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page 0008 8101h TPUA Timer synchronous register TSYR...
Page 150 RX630 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (15/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page 0008 8156h TPU4 Timer counter TCNT...
Page 151 RX630 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (16/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page 0008 81B4h TPU9 Timer interrupt enable register TIER...
Page 152 RX630 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (17/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page 0008 8206h TMR0 Time constant register B TCORB...
Page 153 RX630 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (18/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page 0008 8329h RIIC1 C bus status register 2 ICSR2...
Page 154 RX630 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (19/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page 0008 8373h RIIC3 C bus receive data register ICDRR...
Page 155 RX630 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (20/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page 0008 83CAh RSPI2 RSPI bit rate register SPBR...
Page 156 RX630 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (21/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page 0008 8639h MTU4 Timer buffer operation transfer mode register TBTM 2, 3 PCLKB...
Page 157 RX630 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (22/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page 0008 880Ah MTU2 Timer general register B TGRB...
Page 158 RX630 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (23/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page 0008 903Ah S12AD A/D data register 13 ADDR13...
Page 159 RX630 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (24/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page 0008 A02Dh SCI1 SPI mode register SPMR...
Page 160 RX630 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (25/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page 0008 A0A7h SCI5 Serial extended mode register SEMR...
Page 161 RX630 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (26/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page 0008 A121h SCI9 Bit rate register 2, 3 PCLKB...
Page 162 RX630 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (27/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page 0008 A80Ah IEBus reception master address register 2 IEMA2 3, 4 PCLKB...
Page 163 RX630 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (28/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page 0008 C002h PORT2 Port direction register 2, 3 PCLKB...
Page 164 RX630 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (29/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page 0008 C04Ah PORTA Port input data register PIDR...
Page 165 RX630 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (30/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page 0008 C092h PORT9 Open drain control register 0 ODR0...
Page 166 RX630 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (31/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page 0008 C0EAh PORTA Driving ability control register DSCR...
Page 167 RX630 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (32/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page 0008 C168h P50 pin function control register P50PFS 2, 3 PCLKB...
Page 168 RX630 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (33/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page 0008 C1A8h PD0 pin function control register PD0PFS 2, 3 PCLKB...
Page 169 RX630 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (34/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page 0008 C2A0h to SYSTEM Deep standby backup register 0 to 31 DPSBKR0 to...
Page 170 RX630 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (35/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page 0008 C440h Time capture control register 0 RTCCR0 2, 3 PCLKB...
Page 171 RX630 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (36/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page 0009 0858h CAN0 Test control register 2, 3 PCLKB...
Page 172 RX630 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (37/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page 0009 284Bh CAN2 Transmit FIFO pointer control register TFPCR...
Page 173 RX630 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (38/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page 000A 003Ah USB0 BEMP interrupt status register BEMPENB...
Page 174 RX630 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (39/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page 000A 0056h USB0 USB request value register USBVAL...
Page 175 RX630 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (40/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page 000A 0072h USB0 Pipe 2 control register PIPE2CTR...
Page 176 RX630 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (41/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page 000A 0094h USB0 Pipe 2 transaction counter enable register PIPE2TRE...
Page 177 RX630 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (42/42) Number of Access States Module Register Number Access Related Reference ICLK PCLK ICLK  PCLK Address Symbol Register Name Symbol of Bits Size Function Page 007F C402h FLASH Flash mode register FMODR...
Page 178: Resets
RX630 Group 6. Resets Resets Overview There are nine types of resets: RES# pin reset, power-on reset, voltage-monitoring 0 reset, voltage-monitoring 1 reset, voltage-monitoring 2 reset, deep software standby reset, independent watchdog timer reset, watchdog timer reset, and software reset. Table 6.1 lists the reset names and sources.
Page 179 RX630 Group 6. Resets The internal state and pins are initialized by a reset. Table 6.2 lists the reset targets to be initialized. Table 6.2 Targets to be Initialized by Each Reset Source (1/2) Reset Source RES# Voltage- Independent Watchdog Voltage- Voltage- Power-On...
Page 180 RX630 Group 6. Resets Table 6.2 Targets to be Initialized by Each Reset Source (2/2) Reset Source RES# Voltage- Independent Watchdog Voltage- Voltage- Power-On Monitoring Watchdog Timer Monitoring Monitoring Deep Software Software Targets to be Initialized Reset Reset 0 Reset Timer Reset Reset 1 Reset...
Page 181: Register Descriptions
RX630 Group 6. Resets When a reset is canceled, the reset exception handling starts. For details on the reset exception handling, see section 14, Exception Handling . Table 6.3 lists the pin related to the reset. Table 6.3 Pin Related to Reset Pin Name Function RES#...
Page 182 RX630 Group 6. Resets LVD0RF Flag (Voltage-Monitoring 0 Reset Detect Flag) The LVD0RF flag indicates that VCC voltage has fallen below Vdet0. [Setting condition]  When Vdet0-level VCC voltage is detected. [Clearing conditions]  When a reset listed in Table 6.2 occurs. ...
Page 183: Reset Status Register 1 (Rstsr1)
RX630 Group 6. Resets 6.2.2 Reset Status Register 1 (RSTSR1) Address(es): 0008 C291h — — — — — — — CWSF Value after reset: 0/1* Symbol Bit Name Description CWSF Cold/Warm Start Determination Flag 0: Cold start R(/W) 1: Warm start b7 to b1 —...
Page 184: Software Reset Register (Swrr)
RX630 Group 6. Resets IWDTRF Flag (Independent Watchdog Timer Reset Detect Flag) The IWDTRF flag indicates that an independent watchdog timer reset has occurred. [Setting condition]  When an independent watchdog timer reset occurs. [Clearing conditions]  When a reset listed in Table 6.2 occurs. ...
Page 185: Operation
RX630 Group 6. Resets Operation 6.3.1 RES# pin Reset This is a reset generated by the RES# pin. When the RES# pin is driven low, all the processing in progress is aborted and the LSI enters a reset state. In order to unfailingly reset the LSI, the RES# pin should be held low for the specified power supply stabilization time at a power-on.
Page 186: Voltage Monitoring 1 Reset And Voltage Monitoring 2 Reset
RX630 Group 6. Resets Vdet0* VPOR* External voltage VCC Power-on reset state Voltage-monitoring 0 reset state RES# pin POR detection signal (Low is valid) Setting by OFS1.LVDAS LVD0 enable/disable signal (Low is valid) Voltage detection 0 signal (Low is valid) tPOR* tLVD0* Internal reset signal...
Page 187 RX630 Group 6. Resets Timing for release from the voltage monitoring 1 reset state is selectable with the voltage monitoring 1 reset negate select bit (LVD1RN) in the LVD1CR0. When the LVD1CR0.LVD1RN bit is 0 and VCC has fallen to or below Vdet1, the CPU is released from the internal reset state and starts reset exception handling once the LVD1 reset time (tLVD1) has elapsed after VCC has risen above Vdet1.
Page 188: Deep Software Standby Reset
RX630 Group 6. Resets 6.3.4 Deep Software Standby Reset This is an internal reset generated when deep software standby mode is canceled by an interrupt. When a deep software standby mode cancelation source is generated, a deep software standby reset is generated. The deep software standby reset is canceled after tDSBY (return time after deep software standby mode cancelation) has elapsed.
Page 189: Determination Of Cold/Warm Start
RX630 Group 6. Resets 6.3.8 Determination of Cold/Warm Start By reading the CWSF flag in RSTSR1, the type of reset processing caused can be identified; that is, whether a power-on reset has caused the reset processing (cold start) or a reset signal input during operation has caused the reset processing (warm start).
Page 190: Determination Of Reset Generation Source
RX630 Group 6. Resets 6.3.9 Determination of Reset Generation Source Reading RSTSR0 and RSTSR2 determines which reset was used to execute the reset exception handling. Figure 6.4 shows an example of the flow to identify a reset generation source. Reset exception handling RSTSR2.
Page 191: Option-Setting Memory
RX630 Group 7. Option-Setting Memory Option-Setting Memory Overview Option-setting memory refers to a set of registers that are provided for selecting the state of the microcontroller after a reset. The option-setting memory is allocated in the ROM. Figure 7.1 shows the option-setting memory area. Addresses FF7F FFE8h to FF7F FFEFh UB code A...
Page 192: Register Descriptions
RX630 Group 7. Option-Setting Memory Register Descriptions 7.2.1 Option Function Select Register 0 (OFS0) Address(es): FFFF FF8Ch WDTRS WDTTOPS[1:0] WDTST — — — WDTRPSS[1:0] WDTRPES[1:0] WDTCKS[3:0] — TIRQS Value after reset: The value set by the user IWDTS IWDTR IWDTTOPS[1:0] IWDTS —...
Page 193 RX630 Group 7. Option-Setting Memory Symbol Bit Name Description b19, b18 WDTTOPS[1:0] WDT Timeout Period Select b19 b18 0 0: 1024 cycles (03FFh) 0 1: 4096 cycles (0FFFh) 1 0: 8192 cycles (1FFFh) 1 1: 16384 cycles (3FFFh) b23 to b20 WDTCKS[3:0] WDT Clock Frequency 0 0 0 1: PCLK/4...
Page 194 RX630 Group 7. Option-Setting Memory window start position, only the value for the window start position is effective. The counter values corresponding to the settings for the start and end positions of the window in the IWDTRPSS[1:0] and IWDTRPES[1:0] bits vary with the setting of the IWDTTOPS[1:0] bits. For details, refer to section 30, Independent Watchdog Timer (IWDTa) .
Page 195 RX630 Group 7. Option-Setting Memory WDTRPES[1:0] Bits (WDT Window End Position Select) These bits select the position of the end of the window on the down-counter as 0%, 25%, 50%, or 75% of the value being counted by the counter. The value of the window end position must be smaller than the value of the window start position (window start position >...
Page 196: Option Function Select Register 1 (Ofs1)
RX630 Group 7. Option-Setting Memory 7.2.2 Option Function Select Register 1 (OFS1) Address(es): FFFF FF88h — — — — — — — — — — — — — — — — Value after reset: The value set by the user HOCO —...
Page 197: Endian Select Register B (Mdeb), Endian Select Register S (Mdes)
RX630 Group 7. Option-Setting Memory 7.2.3 Endian Select Register B (MDEB), Endian Select Register S (MDES) Address(es): FF7F FFF8h: MDEB (in user boot mode) FFFF FF80h: MDES (in single-chip mode) — — — — — — — — — — —...
Page 198: Ub Codes
RX630 Group 7. Option-Setting Memory UB Codes UB codes A and B are required if user boot mode is to be employed. When the USB boot mode is used continuously, these codes should not be changed. The MCU will start up in user boot mode on release from the reset state if the four conditions below are satisfied.
Page 199: Voltage Detection Circuit (Lvda)
RX630 Group 8. Voltage Detection Circuit (LVDA) Voltage Detection Circuit (LVDA) The voltage detection circuit (LVDA) monitors the voltage level input to the VCC pin using a program. Overview In voltage detection 0, whether to enable or disable the reset of voltage monitoring 0 can be selected after the reset using the option function select register 1 (OFS1).
Page 200 RX630 Group 8. Voltage Detection Circuit (LVDA) LVDAS Voltage detection 0 reset signal Vdet0 Internal reference voltage (for detecting Vdet0) LVD1E LVD1CMPE Voltage detection 1 signal Vdet1 Internal reference voltage Level selection (for detecting Vdet1) circuit LVD1LVL[3:0] LVD2E LVD2CMPE Voltage detection 2 signal Vdet2 Internal reference voltage Level selection...
Page 201 RX630 Group 8. Voltage Detection Circuit (LVDA) Voltage monitoring 1 interrupt/reset circuit LVD1FSAMP[1:0] The setting of the LVD1DET bit will be 0 if 0 (undetected) is written in the =00b program. =01b =10b =11b Voltage detection 1 circuit LOCO LVD1E LVD1SR LVD1RIE LVD1CMPE...
Page 202: Register Descriptions
RX630 Group 8. Voltage Detection Circuit (LVDA) Register Descriptions 8.2.1 Voltage Monitoring 1 Circuit Control Register 1 (LVD1CR1) Address(es): 0008 00E0h LVD1IDTSEL — — — — — — [1:0] Value after reset: Symbol Bit Name Description b1, b0 LVD1IDTSEL Voltage Monitoring 1 Interrupt b1 b0 0 0 : When VCC ...
Page 203: Voltage Monitoring 2 Circuit Control Register 1 (Lvd2Cr1)
RX630 Group 8. Voltage Detection Circuit (LVDA) 8.2.3 Voltage Monitoring 2 Circuit Control Register 1 (LVD2CR1) Address(es): 0008 00E2h LVD2IDTSEL — — — — — — [1:0] Value after reset: Symbol Bit Name Description b1, b0 LVD2IDTSEL Voltage Monitoring 2 Interrupt b1 b0 0 0: When VCC ...
Page 204: Voltage Monitoring Circuit Control Register (Lvcmpcr)
RX630 Group 8. Voltage Detection Circuit (LVDA) 8.2.5 Voltage Monitoring Circuit Control Register (LVCMPCR) Address(es): 0008 C297h — LVD2E LVD1E — — — — — Value after reset: Symbol Bit Name Description b4 to b0 — Reserved These bits are read as 0. The write value should be 0. LVD1E Voltage Detection 1 Enable 0: Voltage detection 1 circuit disabled...
Page 205: Voltage Monitoring 1 Circuit Control Register 0 (Lvd1Cr0)
RX630 Group 8. Voltage Detection Circuit (LVDA) 8.2.7 Voltage Monitoring 1 Circuit Control Register 0 (LVD1CR0) Address(es): 0008 C29Ah LVD1R LVD1FSAMP LVD1C LVD1D LVD1RI LVD1RI — [1:0] FDIS Value after reset: x: Undefined Symbol Bit Name Description LVD1RIE Voltage Monitoring 1 0: Disabled Interrupt/Reset Enable 1: Enabled...
Page 206: Voltage Monitoring 2 Circuit Control Register 0 (Lvd2Cr0)
RX630 Group 8. Voltage Detection Circuit (LVDA) LVD1RN Bit (Voltage Monitoring 1 Reset Negate Select) If the LVD1RN bit is to be set to 1 (negation follows a stabilization time after assertion of the LVD1 reset signal), set the LOCOCR.LCSTP bit to 0 (the LOCO operates). Furthermore, if a transition to software standby or deep software standby is to be made, the only possible value for the LVD1RN bit is 0 (negation follows a stabilization time after VCC >...
Page 207 RX630 Group 8. Voltage Detection Circuit (LVDA) LVD2RI Bit (Voltage Monitoring 2 Circuit Mode Select) When the LVD2RI it is 1 (voltage monitoring 2 reset enabled) or when the LVD1CR0.LVD1RI bit is 1 (voltage monitoring 1 reset enabled), a transition to deep software standby mode cannot be made, instead a transition to software standby mode is made.
Page 208: Vcc Input Voltage Monitor
RX630 Group 8. Voltage Detection Circuit (LVDA) VCC Input Voltage Monitor 8.3.1 Monitoring Vdet0 Monitoring Vdet0 is not possible. 8.3.2 Monitoring Vdet1 Table 8.2 lists the procedures for setting up monitoring against Vdet1. After the settings are completed, results of comparison by voltage monitoring 1 can be monitored by using the LVD1SR.LVD1MON flag.
Page 209: Reset From Voltage Monitor 0
RX630 Group 8. Voltage Detection Circuit (LVDA) Reset from Voltage Monitor 0 When using the reset from voltage monitor 0, clear the voltage detection 0 circuit start bit (OFS1.LVDAS) to 0 (enabling the voltage monitor 0 reset after a reset). Figure 8.4 shows an example of operations for a voltage monitoring 0 reset.
Page 210: Interrupt And Reset From Voltage Monitor 1
RX630 Group 8. Voltage Detection Circuit (LVDA) Interrupt and Reset from Voltage Monitor 1 Table 8.4 lists the procedures for setting bits related to the voltage monitor 1 interrupt and voltage monitor 1 reset so that voltage monitoring operates. Table 8.5 shows the procedure for setting bits related to the voltage monitor 1 interrupt and voltage monitor 1 reset so that voltage monitoring stops.
Page 211 RX630 Group 8. Voltage Detection Circuit (LVDA) Vdet1 Lower limit on VCC voltage (VCCmin)* LVD1MON bit when LVD1DFDIS bit is set to 0 (digital filter enabled) 1n+2 to 2n+3 cycles of 1n+2 to 2n+3 cycles of the LOCO the LOCO LVD1DET bit LVD1DFDIS bit is set to 0 (digital filter enabled) and LVD1IDTSEL[1:0] bits...
Page 212: Interrupt And Reset From Voltage Monitor 2
RX630 Group 8. Voltage Detection Circuit (LVDA) Interrupt and Reset from Voltage Monitor 2 Table 8.6 shows the procedures for setting bits related to the voltage monitor 2 interrupt and voltage monitor 2 reset so that voltage monitoring operates. Table 8.7 shows the procedure for setting bits related to the voltage monitor 2 interrupt and voltage monitor 2 reset so that voltage monitoring stops.
Page 213 RX630 Group 8. Voltage Detection Circuit (LVDA) Vdet2 Lower limit on VCC voltage (VCCmin)* LVD2MON bit when LVD2DFDIS bit is set to 0 (digital filter enabled) 1n+2 to 2n+3 cycles of 1n+2 to 2n+3 cycles of the LOCO the LOCO LVD2DET bit LVD2DFDIS bit is set to 0 (digital filter enabled) and LVD2IDTSEL[1:0]...
Page 214: Clock Generation Circuit
RX630 Group 9. Clock Generation Circuit Clock Generation Circuit Overview The RX630 Group incorporates a clock generation circuit. Table 9.1 lists the specifications of the clock generation circuit. Figure 9.1 shows a block diagram of the clock generation circuit. Table 9.1 Specifications of Clock Generation Circuit Item Specification...
Page 215 RX630 Group 9. Clock Generation Circuit SCKCR FCK[3:0] FlashIF clock (FCLK) To FlashIF SCKCR ICK[3:0] System clock (ICLK) To CPU, DMAC, DTC, ROM, PLIDIV[1:0] STC[5:0] and RAM PLLCR PLLCR Frequency Frequency divider circuit divider SCKCR PCKB[3:0] CKSEL[2:0] SCKCR3 Peripheral module clock Oscillation (PCLKB) Stop detection...
Page 216: Register Descriptions
RX630 Group 9. Clock Generation Circuit Table 9.2 lists the input/output pins of the clock generation circuit. Table 9.2 Input/Output Pins of Clock Generation Circuit Pin Name Description XTAL Output These pins are used to connect a crystal resonator. The EXTAL pin can also be used to input an external clock.
Page 217 RX630 Group 9. Clock Generation Circuit Symbol Bit Name Description b27 to b24 ICK[3:0] System Clock (ICLK) 0 0 0 0: ×1/1 2, *4, *5 Select 0 0 0 1: ×1/2 0 0 1 0: ×1/4 0 0 1 1: ×1/8 0 1 0 0: ×1/16 0 1 0 1: ×1/32 0 1 1 0: ×1/64...
Page 218: System Clock Control Register 2 (Sckcr2)
RX630 Group 9. Clock Generation Circuit 9.2.2 System Clock Control Register 2 (SCKCR2) Address(es): 0008 0024h — — — — — — — — UCK[3:0] IEBCK[3:0] Value after reset: Symbol Bit Name Description b3 to b0 IEBCK[3:0] IEBUS Clock (IECLK) 0 0 0 1: ×1/2 Select * 0 0 1 0: ×1/4...
Page 219: System Clock Control Register 3 (Sckcr3)
RX630 Group 9. Clock Generation Circuit 9.2.3 System Clock Control Register 3 (SCKCR3) Address(es): 0008 0026h — — — — — CKSEL[2:0] — — — — — — — — Value after reset: Symbol Bit Name Description b7 to b0 —...
Page 220: Pll Control Register (Pllcr)
RX630 Group 9. Clock Generation Circuit 9.2.4 PLL Control Register (PLLCR) Address(es): 0008 0028h — — STC[5:0] — — — — — — PLIDIV[1:0] Value after reset: Symbol Bit Name Description b1, b0 PLIDIV[1:0] PLL Input Frequency b1 b0 0 0: ×1 Division Ratio Select 0 1: ×1/2 1 0: ×1/4...
Page 221: Pll Control Register 2 (Pllcr2)
RX630 Group 9. Clock Generation Circuit 9.2.5 PLL Control Register 2 (PLLCR2) Address(es): 0008 002Ah — — — — — — — PLLEN Value after reset: Symbol Bit Name Description PLLEN PLL Stop Control 0: PLL is operating. 1: PLL is stopped. b7 to b1 —...
Page 222: External Bus Clock Control Register (Bckcr)
RX630 Group 9. Clock Generation Circuit 9.2.6 External Bus Clock Control Register (BCKCR) Address(es): 0008 0030h BCLKD — — — — — — — Value after reset: Symbol Bit Name Description BCLKDIV BCLK Pin Output Select 0: BCLK 1: 1/2 BCLK b7 to b1 —...
Page 223: Main Clock Oscillator Control Register (Mosccr)
RX630 Group 9. Clock Generation Circuit 9.2.7 Main Clock Oscillator Control Register (MOSCCR) Address(es): 0008 0032h — — — — — — — MOSTP Value after reset: Symbol Bit Name Description MOSTP Main Clock Oscillator Stop 0: Main clock oscillator is operating. 1: Main clock oscillator is stopped.
Page 224: Sub-Clock Oscillator Control Register (Sosccr)
RX630 Group 9. Clock Generation Circuit 9.2.8 Sub-Clock Oscillator Control Register (SOSCCR) Address(es): 0008 0033h — — — — — — — SOSTP Value after reset: Symbol Bit Name Description SOSTP Sub-Clock Oscillator Stop 0: Sub-clock oscillator is operating. 1: Sub-clock oscillator is stopped. b7 to b1 —...
Page 225: Low-Speed On-Chip Oscillator Control Register (Lococr)
RX630 Group 9. Clock Generation Circuit 9.2.9 Low-Speed On-Chip Oscillator Control Register (LOCOCR) Address(es): 0008 0034h — — — — — — — LCSTP Value after reset: Symbol Bit Name Description LCSTP LOCO Stop 0: LOCO is operating. 1: LOCO is stopped. b7 to b1 —...
Page 226: Iwdt-Dedicated On-Chip Oscillator Control Register (Ilococr)
RX630 Group 9. Clock Generation Circuit 9.2.10 IWDT-Dedicated On-Chip Oscillator Control Register (ILOCOCR) Address(es): 0008 0035h — — — — — — — ILCSTP Value after reset: Symbol Bit Name Description ILCSTP IWDT-Dedicated On-Chip 0: IWDT-Dedicated On-Chip Oscillator is operating. Oscillator 1: IWDT-Dedicated On-Chip Oscillator is stopped.
Page 227: High-Speed On-Chip Oscillator Control Register (Hococr)
RX630 Group 9. Clock Generation Circuit 9.2.11 High-Speed On-Chip Oscillator Control Register (HOCOCR) Address(es): 0008 0036h — — — — — — — HCSTP Value after reset: 0/1* Note 1. The HCSTP bit value after a reset is 0 when the HOCO oscillation enable bit in the option function select register 1 (OFS1.HOCOEN) is 0.
Page 228: Oscillation Stop Detection Control Register (Ostdcr)
RX630 Group 9. Clock Generation Circuit 9.2.12 Oscillation Stop Detection Control Register (OSTDCR) Address(es): 0008 0040h OSTDI OSTDE — — — — — — Value after reset: Symbol Bit Name Description OSTDIE Oscillation Stop Detection 0: The oscillation stop detection interrupt is disabled. Oscillation stop Interrupt Enable detection is not notified to the POE.
Page 229: Oscillation Stop Detection Status Register (Ostdsr)
RX630 Group 9. Clock Generation Circuit 9.2.13 Oscillation Stop Detection Status Register (OSTDSR) Address(es): 0008 0041h — — — — — — — OSTDF Value after reset: Symbol Bit Name Description OSTDF Oscillation Stop Detection Flag 0: The main clock oscillation stop has not been detected. R(/W) 1: The main clock oscillation stop has been detected.
Page 230: Main Clock Oscillator Forced Oscillation Control Register (Mofcr)
RX630 Group 9. Clock Generation Circuit 9.2.14 Main Clock Oscillator Forced Oscillation Control Register (MOFCR) Address(es): 0008 C293h MOFXI — — — — — — — Value after reset: Symbol Bit Name Description MOFXIN Main Clock Oscillator Forced 0: Oscillator is not controlled by this bit. Oscillation 1: The main clock oscillator is forcedly oscillated.
Page 231: High-Speed On-Chip Oscillator Power Supply Control Register (Hocopcr)
RX630 Group 9. Clock Generation Circuit 9.2.15 High-Speed On-Chip Oscillator Power Supply Control Register (HOCOPCR) Address(es): 0008 C294h HOCO — — — — — — — PCNT Value after reset: Symbol Bit Name Description HOCOPCNT High-Speed On-Chip Oscillator 0: Turns the power supply of the HOCO on. Power Supply Control 1: Turns the power supply of the HOCO off.
Page 232 RX630 Group 9. Clock Generation Circuit EXTAL XTAL = 10 to 22 pF (reference values) Figure 9.2 Example of Crystal Resonator Connection Table 9.3 Damping Resistance (Reference Values) Frequency (MHz) Rd (  ) Figure 9.3 shows an equivalent circuit of the crystal resonator. Use a crystal resonator that has the characteristics shown in Table 9.4 .
Page 233: External Clock Input
RX630 Group 9. Clock Generation Circuit 9.3.2 External Clock Input Figure 9.4 shows examples of connection of external clock input. To leave the XTAL pin open, make the parasitic capacitance less than 5 pF. EXTAL External clock input XTAL Open (a) Example of connection with the XTAL pin open EXTAL External clock input...
Page 234: Handling Of Pins When Sub-Clock Is Not Used
RX630 Group 9. Clock Generation Circuit XCIN XCOUT C1 = C2 = 10 pF (reference values) Figure 9.5 Connection Example of 32.768-kHz Crystal Resonator Figure 9.6 shows an equivalent circuit for the 32.768-kHz crystal resonator. Use a crystal resonator that has the characteristics listed in Table 9.5 .
Page 235: Oscillation Stop Detection Function
RX630 Group 9. Clock Generation Circuit Oscillation Stop Detection Function 9.5.1 Oscillation Stop Detection and Operation after Detection The oscillation stop detection function is used to detect the main clock oscillator stop and to supply LOCO clock pulses from the low-speed on-chip oscillator as the system clock source instead of the main clock or PLL clock. An oscillation stop detection interrupt request can be generated when an oscillation stop is detected.
Page 236: Oscillation Stop Detection Interrupts
RX630 Group 9. Clock Generation Circuit Start Switch to SCKCR3.CKSEL[2:0] = 000b (selecting the LOCO) Setting OSTDCR.OSTDIE = 0 Reading OSTDSR.OSTDF = 1 Setting OSTDSR.OSTDF = 0 OSTDSR.OSTDF = 0 Try again? Switch to SCKCR3.CKSEL[2:0] = 010b (selecting the main clock oscillator) Note: On return from the oscillation-stopped state, the factor responsible for stopping the main clock oscillation circuit must be removed on the user system to allow the return of oscillation.
Page 237: Pll Circuit
RX630 Group 9. Clock Generation Circuit PLL Circuit The PLL circuit has a function to multiply the frequency from the oscillator. Internal Clock Clock sources of internal clock signals are the main clock, sub-clock, HOCO clock, LOCO clock, PLL clock, dedicated clock for the IWDT, and the external clock for JTAG.
Page 238: Usb Clock
RX630 Group 9. Clock Generation Circuit always be performed while the PSTOP1 bit in SCKCR is 1. When the BCKCR.BCLKDIV bit is set to 1, the BCLK clock divided by 2 is output from the BCLK pin. The BCLK frequency is specified by the BCK[3:0] bits in SCKCR, the CKSEL[2:0] bits in SCKCR3, and the STC[5:0] and PLIDIV[1:0] bits in PLLCR.
Page 239: Pin Settings When An Oscillator Is Connected
RX630 Group 9. Clock Generation Circuit Pin Settings When an Oscillator is Connected (1) Main clock Set P36 and P37 as input pins and then clear the main clock oscillator stop bit (MOSTP in MOSCCR) to 0 so that the clock runs, or set the main clock oscillator forced oscillation bit (MOFXIN in MOFCR) to 1 so that it is forcibly made to oscillate.
Page 240: Notes On Resonator Connect Pin
RX630 Group 9. Clock Generation Circuit Prohibited Signal A Signal B Prohibited XTAL EXTAL Figure 9.9 Notes on Board Design for Oscillation Circuit (Applies to the Sub-Clock Oscillator, in Case of the Main Clock Oscillator) 9.10.4 Notes on Resonator Connect Pin When the main clock is not used, the EXTAL and XTAL pins can be used as general ports P36 and P37.
Page 241 RX630 Group 9. Clock Generation Circuit  When the sub-clock is the system clock, even if the RCR3.RTCEN bit is set to 1 and the sub-clock is already oscillating, wait for at least five cycles of the sub-clock after the SOSCCR.SOSTP bit changes from 1 (stopped) to 0 (operating) before starting to use the sub-clock as the system clock ...
Page 242: Frequency Measurement Circuit (Mck)
RX630 Group 10. Frequency Measurement Circuit (MCK) Frequency Measurement Circuit (MCK) The respective clock count extension circuits of the internal MTU (system 1) or unit 0 of TPU (system 2) can be used to monitor the main clock, sub-clock, LOCO (for system use), PLL, and HOCO for abnormal frequencies. 10.1 Overview Table 10.1 lists the specifications of the frequency measurement circuit.
Page 243 RX630 Group 10. Frequency Measurement Circuit (MCK) MTU0 (compare match) Counter-clock extension circuit 1 TCNT MTCLKD external pin input TGRA LOCO (system) MTCLKD Main clock Sub clock SCK1.SCK[1:0] MTU1 (input capture) TCNT Interrupt Peripheral module clock PCLK TGRA Figure 10.1 Block Diagram of Frequency Measurement Circuit with MTU (System 1) TPU (unit 0) TPU0 (compare match)
Page 244 RX630 Group 10. Frequency Measurement Circuit (MCK) System clock ICLK PCLK BCLK Monitoring timing generation timer System clock LOCO for system monitoring timer (125 kHz ± 10%) Timer general register (operates by PCLK/1) (divides reference clock frequency) Reference clock channel 0 channel 1 Synchronized by PCLK/1 (1) Reference clock is set as clock source of channel 0.
Page 245: Register Descriptions
RX630 Group 10. Frequency Measurement Circuit (MCK) 10.2 Register Descriptions 10.2.1 Counter-Clock Extension Register n (SCKn) (n = 1, 2) Address(es): 0008 C880h: SCK1, 0008 C890h: SCK2 — — — — — — SCK[1:0] Value after reset: Symbol Bit Name Description b1, b0 SCK[1:0]...
Page 246: Operation
RX630 Group 10. Frequency Measurement Circuit (MCK) 10.3 Operation Figure 10.4 illustrates a flowchart of the frequency measurement circuit. Figure 10.5 illustrates an example of the MTU/TPU operation. Frequency measurement circuit Select reference clock by counter-clock extension register n Set channel 0 and channel 1 Start count operation of channel 0 and channel 1 WAIT...
Page 247 RX630 Group 10. Frequency Measurement Circuit (MCK) TCNT (channel 0) TGRA (channel 0) TSTR.CST0 MTCLKD/TCLKD TCNT (channel 1) TSTR.CST1 PCLK* TGRA (channel 1) TCNT: Timer counter TGRA: Timer general register A CSTi: Counter start i bit in the timer start register Note 1.
Page 248: Usage Notes
RX630 Group 10. Frequency Measurement Circuit (MCK) 10.4 Usage Notes 10.4.1 Setting the Module-Stop Control Registers The module-stop control registers can be used to place modules in and release modules from the module-stopped state. The several modules that realize frequency measurement are all stopped in their initial state. Releasing the modules from the stopped state makes operations for frequency measurement possible.
Page 249: Low Power Consumption
RX630 Group 11. Low Power Consumption Low Power Consumption 11.1 Overview The RX630 Group has several functions for reducing power consumption, including switching of clock signals to reduce power consumption, BCLK output control, stopping modules, functions for low power consumption in normal operation, and transitions to low power consumption states.
Page 250 RX630 Group 11. Low Power Consumption Table 11.2 Entering and Exiting Low Power Consumption Modes and Operating States in Each Mode (2/2) Entering and Exiting Low Power Consumption Modes and Operating All-Module Clock Stop Deep Software Standby States Sleep Mode Mode Software Standby Mode Mode...
Page 251 RX630 Group 11. Low Power Consumption SBYCR.SSBY = 0 Reset state Sleep mode WAIT instruction* RES# pin = High* SBYCR.SSBY = 0 All interrupts MSTPCRA.ACSE = 1 MSTPCRA = FFFF FF[C-F]Fh MSTPCRB = FFFF FFFFh MSTPCRC[31:16] = FFFFh WAIT instruction* Interrupt* All-module clock stop mode Normal operation mode...
Page 252: Register Descriptions
RX630 Group 11. Low Power Consumption 11.2 Register Descriptions 11.2.1 Standby Control Register (SBYCR) Address(es): 0008 000Ch SSBY — — — — — — — — — — — — — — Value after reset: Symbol Bit Name Description b13 to b0 —...
Page 253: Module Stop Control Register A (Mstpcra)
RX630 Group 11. Low Power Consumption 11.2.2 Module Stop Control Register A (MSTPCRA) Address(es): 0008 0010h MSTPA MSTPA MSTPA MSTPA MSTPA MSTPA MSTPA — ACSE — — — — — — — Value after reset: MSTPA MSTPA MSTPA MSTPA MSTPA MSTPA MSTPA MSTPA...
Page 254: Module Stop Control Register B (Mstpcrb)
RX630 Group 11. Low Power Consumption Symbol Bit Name Description MSTPA24 Module Stop A24 Writing to and reading from this bit is enabled. When a transition to all-module clock stop mode is made, be sure that 1 has been written to this bit.
Page 255 RX630 Group 11. Low Power Consumption Symbol Bit Name Description MSTPB4 Serial Communication Target module: SCId (SCI12) Interface SCId Module 0: The module-stop state is canceled Stop 1: Transition to the module-stop state is made b7 to b5 — Reserved These bits are read as 1.
Page 256: Module Stop Control Register C (Mstpcrc)
RX630 Group 11. Low Power Consumption 11.2.4 Module Stop Control Register C (MSTPCRC) Address(es): 0008 0018h MSTPC MSTPC MSTPC MSTPC MSTPC MSTPC MSTPC MSTPC MSTPC — — — — — — — Value after reset: MSTPC MSTPC — — — —...
Page 257: Operating Power Control Register (Opccr)
RX630 Group 11. Low Power Consumption 11.2.5 Operating Power Control Register (OPCCR) Address(es): 0008 00A0h OPCM — — — — OPCM[2:0] Value after reset: Symbol Bit Name Description b2 to b0 OPCM[2:0] Operating Power Control b2 b1 b0 0 0 0: High-speed operating mode Mode Select 1 1 0: Low-speed operating mode 1 1 1 1: Low-speed operating mode 2...
Page 258 RX630 Group 11. Low Power Consumption Table 11.3 Relationship between Operating Power Control Mode, Operating Range, and Power Consumption Operating Frequency Range Operating Voltage Range Flash Operating Power OPCM[2:0] Flash Flash Flash memory Read memory Control Mode Bits memory memory Read ICLK FCLK...
Page 259: Sleep Mode Return Clock Source Switching Register (Rstckcr)
RX630 Group 11. Low Power Consumption OPCMTSF Flag (Operating Power Control Mode Transition Status Flag) The OPCMTSF flag indicates the switching control state when the operating power control mode is switched. When a write access is attempted to change the operating power control mode, the OPCMTSF flag is set to 1. The flag becomes 0 after a transition to the changed control mode is completed.
Page 260: Main Clock Oscillator Wait Control Register (Moscwtcr)
RX630 Group 11. Low Power Consumption 11.2.7 Main Clock Oscillator Wait Control Register (MOSCWTCR) Address(es): 0008 00A2h — — — MSTS[4:0] Value after reset: Symbol Bit Name Description b4 to b0 MSTS[4:0] Main Clock Oscillator Wait 0 0 0 0 0: Waiting time = 2 cycles Time Select 0 0 0 0 1: Waiting time = 4 cycles 0 0 0 1 0: Waiting time = 8 cycles...
Page 261: Sub-Clock Oscillator Wait Control Register (Soscwtcr)
RX630 Group 11. Low Power Consumption 11.2.8 Sub-Clock Oscillator Wait Control Register (SOSCWTCR) Address(es): 0008 00A3h — — — SSTS[4:0] Value after reset: Symbol Bit Name Description b4 to b0 SSTS[4:0] Sub-Clock Oscillator Wait 0 0 0 0 0: Waiting time = 2 cycles Time Select 0 0 0 0 1: Waiting time = 4 cycles 0 0 0 1 0: Waiting time = 8 cycles...
Page 262 RX630 Group 11. Low Power Consumption At this time, when the sub-clock stabilization time is calculated from the formula in Table 45.11 , SUBOSCWT SUBOSC 65536[cycles] 2000[ms] 32.768[kHz] 4000[ms] 4 s are required from the time the sub-clock starts oscillating until it is usable. ...
Page 263: Pll Wait Control Register (Pllwtcr)
RX630 Group 11. Low Power Consumption 11.2.9 PLL Wait Control Register (PLLWTCR) Address(es): 0008 00A6h — — — PSTS[4:0] Value after reset: Symbol Bit Name Description b4 to b0 PSTS[4:0] PLL Wait Time Select 0 0 0 0 0: Waiting time = 16 cycles 0 0 0 0 1: Waiting time = 32 cycles 0 0 0 1 0: Waiting time = 64 cycles 0 0 0 1 1: Waiting time = 512 cycles...
Page 264 RX630 Group 11. Low Power Consumption  When the PLL starts operating before oscillation of the main clock has become stable To satisfy the relation waiting time  (tMAINOSC + tPLL1) × fPLL = (10000 [μs] + 500 [μs]) x 200 [MHz] = 2100000 [cycles], set the PSTS[4:0] bits to 01111b (4194304 cycles).
Page 265: Deep Standby Control Register (Dpsbycr)
RX630 Group 11. Low Power Consumption 11.2.10 Deep Standby Control Register (DPSBYCR) Address(es): 0008 C280h DPSBY IOKEE DEEPCUT — — — — [1:0] Value after reset: Symbol Bit Name Description b1, b0 DEEPCUT Deep Cut b1 b0 0 0: Power is supplied to the RAM (RAM0* ) and USB resume detecting unit in [1:0] deep software standby mode...
Page 266 RX630 Group 11. Low Power Consumption DPSBY Bit (Deep Software Standby) The DPSBY bit controls transitions to deep software standby mode. When the WAIT instruction is executed while the SBYCR.SSBY and DPSBY bits are both 1, the LSI enters deep software standby mode through software standby mode.
Page 267: Deep Standby Interrupt Enable Register 0 (Dpsier0)
RX630 Group 11. Low Power Consumption 11.2.11 Deep Standby Interrupt Enable Register 0 (DPSIER0) Address(es): 0008 C282h DIRQ7 DIRQ6 DIRQ5 DIRQ4 DIRQ3 DIRQ2 DIRQ1 DIRQ0 Value after reset: Symbol Bit Name Description DIRQ0E IRQ0-DS Pin Enable 0: Canceling deep software standby mode by the IRQ0-DS pin is disabled 1: Canceling deep software standby mode by the IRQ0-DS pin is enabled DIRQ1E IRQ1-DS Pin Enable...
Page 268: Deep Standby Interrupt Enable Register 1 (Dpsier1)
RX630 Group 11. Low Power Consumption 11.2.12 Deep Standby Interrupt Enable Register 1 (DPSIER1) Address(es): 0008 C283h DIRQ1 DIRQ1 DIRQ1 DIRQ1 DIRQ11 DIRQ1 DIRQ9 DIRQ8 Value after reset: Symbol Bit Name Description DIRQ8E IRQ8-DS Pin Enable 0: Canceling deep software standby mode by the IRQ8-DS pin is disabled 1: Canceling deep software standby mode by the IRQ8-DS pin is enabled DIRQ9E IRQ9-DS Pin Enable...
Page 269: Deep Standby Interrupt Enable Register 2 (Dpsier2)
RX630 Group 11. Low Power Consumption 11.2.13 Deep Standby Interrupt Enable Register 2 (DPSIER2) Address(es): 0008 C284h DUSBI DRIICC DRIICD DNMIE DRTCA DRTCII DLVD2I DLVD1I Value after reset: Symbol Bit Name Description DLVD1IE LVD1 Deep Standby Cancel Signal 0: Disable canceling deep software standby mode by the Enable voltage monitoring 1 signal 1: Enable canceling deep software standby mode by the...
Page 270: Deep Standby Interrupt Enable Register 3 (Dpsier3)
RX630 Group 11. Low Power Consumption 11.2.14 Deep Standby Interrupt Enable Register 3 (DPSIER3) Address(es): 0008 C285h DCANI — — — — — — — Value after reset: Symbol Bit Name Description DCANIE CRX1-DS Deep Standby 0: Canceling deep software standby mode by the CRX1-DS pin is Cancel Signal Enable disabled 1: Canceling deep software standby mode by the CRX1-DS pin is...
Page 271: Deep Standby Interrupt Flag Register 0 (Dpsifr0)
RX630 Group 11. Low Power Consumption 11.2.15 Deep Standby Interrupt Flag Register 0 (DPSIFR0) Address(es): 0008 C286h DIRQ7 DIRQ6 DIRQ5 DIRQ4 DIRQ3 DIRQ2 DIRQ1 DIRQ0 Value after reset: Symbol Bit Name Description DIRQ0F IRQ0-DS Deep Standby Cancel Flag 0: No cancel request by the IRQ0-DS pin is generated R(/W) 1: A cancel request by the IRQ0-DS pin is generated DIRQ1F...
Page 272: Deep Standby Interrupt Flag Register 1 (Dpsifr1)
RX630 Group 11. Low Power Consumption 11.2.16 Deep Standby Interrupt Flag Register 1 (DPSIFR1) Address(es): 0008 C287h DIRQ1 DIRQ1 DIRQ1 DIRQ1 DIRQ11 DIRQ1 DIRQ9 DIRQ8 Value after reset: Symbol Bit Name Description DIRQ8F IRQ8-DS Deep Standby Cancel 0: No cancel request by the IRQ8-DS pin is generated R(/W) Flag 1: A cancel request by the IRQ8-DS pin is generated...
Page 273: Deep Standby Interrupt Flag Register 2 (Dpsifr2)
RX630 Group 11. Low Power Consumption 11.2.17 Deep Standby Interrupt Flag Register 2 (DPSIFR2) Address(es): 0008 C288h DUSBI DRIICC DRIICD DNMIF DRTCA DRTCII DLVD2I DLVD1I Value after reset: Symbol Bit Name Description DLVD1IF LVD1 Deep Standby Cancel 0: No cancel request by the voltage monitor 1 signal is generated R(/W) Flag 1: A cancel request by the voltage monitor 1 signal is generated...
Page 274 RX630 Group 11. Low Power Consumption DRTCAIF Flag (RTC Alarm Interrupt Deep Standby Cancel Flag) This flag indicates that a cancel request by the RTC alarm interrupt signal has been generated. [Setting condition]  A cancel request by the RTC alarm interrupt signal is generated [Clearing condition] ...
Page 275: Deep Standby Interrupt Flag Register 3 (Dpsifr3)
RX630 Group 11. Low Power Consumption 11.2.18 Deep Standby Interrupt Flag Register 3 (DPSIFR3) Address(es): 0008 C289h DCANI — — — — — — — Value after reset: Symbol Bit Name Description DCANIF CRX1-DS Deep Standby 0: No cancel request by the CRX1-DS pin is generated R(/W) Cancel Flag 1: A cancel request by the CRX1-DS pin is generated...
Page 276: Deep Standby Interrupt Edge Register 0 (Dpsiegr0)
RX630 Group 11. Low Power Consumption 11.2.19 Deep Standby Interrupt Edge Register 0 (DPSIEGR0) Address(es): 0008 C28Ah DIRQ7 DIRQ6 DIRQ5 DIRQ4 DIRQ3 DIRQ2 DIRQ1 DIRQ0 Value after reset: Symbol Bit Name Description DIRQ0EG IRQ0-DS Edge Select 0: A cancel request is generated at a falling edge 1: A cancel request is generated at a rising edge DIRQ1EG IRQ1-DS Edge Select...
Page 277: Deep Standby Interrupt Edge Register 1 (Dpsiegr1)
RX630 Group 11. Low Power Consumption 11.2.20 Deep Standby Interrupt Edge Register 1 (DPSIEGR1) Address(es): 0008 C28Bh DIRQ1 DIRQ1 DIRQ1 DIRQ1 DIRQ11 DIRQ1 DIRQ9 DIRQ8 Value after reset: Symbol Bit Name Description DIRQ8EG IRQ8-DS Edge Select 0: A cancel request is generated at a falling edge 1: A cancel request is generated at a rising edge DIRQ9EG IRQ9-DS Edge Select...
Page 278: Deep Standby Interrupt Edge Register 2 (Dpsiegr2)
RX630 Group 11. Low Power Consumption 11.2.21 Deep Standby Interrupt Edge Register 2 (DPSIEGR2) Address(es): 0008 C28Ch DRIICC DRIICD DNMIE DLVD2 DLVD1 — — — Value after reset: Symbol Bit Name Description DLVD1EG LVD1 Edge Select 0: A cancel request is generated when VCC < Vdet1 (fall) is detected 1: A cancel request is generated when VCC ...
Page 279: Deep Standby Backup Register (Dpsbkry) (Y = 0 To 31)
RX630 Group 11. Low Power Consumption 11.2.23 Deep Standby Backup Register (DPSBKRy) (y = 0 to 31) Address(es): 0008 C2A0h to 0008 C2BFh Value after reset: x: Undefined DPSBKRy is a 32-byte readable/writable register to store data during deep software standby mode. The value of this register is retained even in deep software standby mode where RAM data is not retained.
Page 280: Function For Lower Operating Power Consumption
RX630 Group 11. Low Power Consumption 11.5 Function for Lower Operating Power Consumption By selecting an appropriate operating power consumption control mode according to the operating frequency and operating voltage, power consumption can be reduced in normal operation, sleep mode and all-module clock stop mode. 11.5.1 Setting Operating Power Consumption Control Mode Examples of the procedures for switching operating power consumption control modes are shown below:...
Page 281: Low Power Consumption Modes
RX630 Group 11. Low Power Consumption 11.6 Low Power Consumption Modes 11.6.1 Sleep Mode 11.6.1.1 Transition to Sleep Mode When the WAIT instruction is executed while the SBYCR.SSBY bit is 0, the CPU enters sleep mode. In sleep mode, the CPU stops operating but the contents of its internal registers are retained.
Page 282: Sleep Mode Return Clock Source Switching Function
RX630 Group 11. Low Power Consumption 11.6.1.3 Sleep Mode Return Clock Source Switching Function To switch the clock source used on return from sleep mode, the clock used after return needs to be set by the sleep mode return clock source switching register (RSTCKCR) and the wait control register needs to be set for each clock source. When the return interrupt is generated, after oscillation settling of the oscillator specified as the return clock, the clock source is automatically switched, and then operation returns from sleep mode.
Page 283: Canceling All-Module Clock Stop Mode
RX630 Group 11. Low Power Consumption 11.6.2.2 Canceling All-Module Clock Stop Mode Release from all-module clock-stop mode is initiated by an external pin interrupt (the NMI or IRQ0 to IRQ15), a peripheral interrupt (8-bit timer * , RTC alarm, RTC interval, IWDT * , USB suspend/resume, voltage monitoring 1, voltage monitoring 2, or oscillator-stopped detection interrupt), a RES# pin reset, a power-on reset, a voltage monitoring reset, or an independent watchdog timer reset, and the transition to the normal program execution state proceeds via...
Page 284: Canceling Software Standby Mode
RX630 Group 11. Low Power Consumption Note 1. For details, see section 2, CPU. Note 2. For details, see section 15, Interrupt controller (ICUb). 11.6.3.2 Canceling Software Standby Mode Release from software standby mode is initiated by an external pin interrupt (the NMI or IRQ0 to IRQ15), peripheral interrupts (the RTC alarm, RTC interval, IWDT, USB suspend/resume, voltage monitoring 1, and voltage monitoring 2 interrupts), an RES# pin reset, a power-on reset, a voltage monitoring reset, or an independent watchdog timer reset.
Page 285: Example Of Software Standby Mode Application
RX630 Group 11. Low Power Consumption 11.6.3.3 Example of Software Standby Mode Application Figure 11.2 shows an example where a transition to software standby mode is made at the falling edge of the IRQn pin, and software standby mode is canceled at the rising edge of the IRQn pin. In this example, an IRQn interrupt is accepted with the IRQCRi.IRQMD[1:0] bits of the ICU set to 01b (falling edge), and then the IRQCRi.IRQMD[1:0] bits are set to 10b (rising edge).
Page 286: Deep Software Standby Mode
RX630 Group 11. Low Power Consumption 11.6.4 Deep Software Standby Mode 11.6.4.1 Transition to Deep Software Standby Mode When the WAIT instruction is executed with the SBYCR.SSBY bit set to 1, a transition to software standby mode * made. At this time, when the DPSBYCR.DPSBY bit is set to 1, a transition to deep software standby mode is made. On deep software standby mode, the CPU, internal peripheral modules (except for parts of the RTC alarm, RTC interval, SCL2-DS, SDA2-DS, CRX1-DS, and USB suspend/resume detecting unit), RAM1 * , and all functions of the oscillators...
Page 287: Canceling Deep Software Standby Mode
RX630 Group 11. Low Power Consumption 11.6.4.2 Canceling Deep Software Standby Mode Release from deep software standby mode is initiated by any of the external pin interrupt source pins (the NMI, IRQ0- DS to IRQ15-DS, SCL2-DS SDA2-DS, or CRX1-DS), peripheral interrupts (the RTC alarm, RTC interval, USB suspend/resume, voltage monitoring 1, and voltage monitoring 2 interrupts), an RES# pin reset, a power-on reset, or a voltage monitoring 0 reset.
Page 288: Example Of Deep Software Standby Mode Application
RX630 Group 11. Low Power Consumption 11.6.4.4 Example of Deep Software Standby Mode Application Figure 11.3 shows an example where a transition to deep software standby mode is made at the falling edge of the IRQn-DS pin, and deep software standby mode is canceled at the rising edge of the IRQn-DS pin. In this example, an IRQn interrupt is accepted with the IRQCRi.IRQMD[1:0] bits of the ICU set to 01b (falling edge).
Page 289: Flowchart To Use Deep Software Standby Mode
RX630 Group 11. Low Power Consumption 11.6.4.5 Flowchart to Use Deep Software Standby Mode Figure 11.4 shows an example of a flowchart to use deep software standby mode. In this example, the RSTSR0.DPSRSTF flag of the reset function is read after the reset exception handling to determine whether a reset was generated by the RES# pin or by the cancellation of deep software standby mode.
Page 290: Usage Notes
RX630 Group 11. Low Power Consumption 11.7 Usage Notes 11.7.1 I/O Port States I/O port states are retained in software standby mode and deep software standby mode. Therefore, the supply current is not reduced while output signals are held high. 11.7.2 Module-Stop State of DMAC and DTC Before setting the MSTPCRA.MSTPA28 bit to 1, clear the DMAST.DMST bit of the DMAC and the DTCST.DTCST bit...
Page 291: Canceling All-Module Clock Stop Mode
RX630 Group 11. Low Power Consumption 11.7.9 Canceling All-Module Clock Stop Mode If the ICLK is set so as to be slower than the PCLKB, a TMR interrupt cannot be used to cancel all-module clock stop mode. To use the TMR interrupt as the all-module clock stop mode cancelling source, change the ICLK so as to be faster than the PCLKB before all-module clock stop mode is entered.
Page 292: Battery Backup Function
RX630 Group 12. Battery Backup Function Battery Backup Function 12.1 Overview When the voltage at the VCC pin is dropped, power can be supplied to the realtime clock (RTC) and sub-clock oscillator from the dedicated battery backup power pin (VBATT pin). When the voltage drop at the VCC pin is detected, connection to power is switched to the VBATT pin.
Page 293: Operation
RX630 Group 12. Battery Backup Function 12.2 Operation 12.2.1 Battery Backup Function When the voltage at the VCC pin is dropped, power can be supplied to the RTC and sub-clock oscillator from the VBATT pin. When the power supply reduction from the VCC pin is detected, connection to power is switched to the power supply from the VBATT pin.
Page 294: Usage Notes
RX630 Group 12. Battery Backup Function 12.3 Usage Notes 1. When the VBATT pin is not in use, connect the VBATT pin to the VCC pin. 2. When the voltage level at the VBATT is lower than the guaranteed operation range, operation of the sub-clock and RTC cannot be guaranteed.
Page 295: Register Write Protection Function
RX630 Group 13. Register Write Protection Function Register Write Protection Function The register write protection function protects important registers from being overwritten for in case a program runs out of control. The registers to be protected are set with the protect register (PRCR). Table 13.1 lists the association between the PRCR bits and the registers to be protected.
Page 296: Register Descriptions
RX630 Group 13. Register Write Protection Function 13.1 Register Descriptions 13.1.1 Protect Register (PRCR) Address(es): 0008 03FEh PRKEY[7:0] — — — — PRC3 — PRC1 PRC0 Value after reset: Symbol Bit Name Function PRC0 Protect Bit 0 Enables writing to the registers related to the clock generation circuit. 0: Write disabled 1: Write enabled PRC1...
Page 297: Exception Handling
RX630 Group 14. Exception Handling Exception Handling 14.1 Exception Events During execution of a program by the CPU, the occurrence of a certain event may cause execution of that program to be suspended and execution of another program to be started. Such kinds of events are called exception events. The RX CPU supports seven types of exceptions.
Page 298: Non-Maskable Interrupt
RX630 Group 14. Exception Handling 14.1.6 Non-Maskable Interrupt The non-maskable interrupt is generated by input of a non-maskable interrupt signal to the CPU and is only used when a fatal fault is considered to have occurred in the system. Never use the non-maskable interrupt with an attempt to return to the program that was being executed at the time of interrupt generation after the exception handling routine is ended.
Page 299: Exception Handling Procedure
RX630 Group 14. Exception Handling 14.2 Exception Handling Procedure In the exception handling, part of the processing is handled automatically by hardware and part of it is handled by a program (exception handling routine) that has been written by the user. Figure 14.2 shows the processing procedure when an exception other than a reset is accepted.
Page 300: Acceptance Of Exception Events
RX630 Group 14. Exception Handling handling routine must be saved on the stack by a user program at the start of the exception handling routine. On completion of processing by an exception handling routine, registers saved on the stack are restored and the RTE instruction is executed to restore execution from the exception handling routine to the original program.
Page 301: Vector And Site For Saving The Values In The Pc And Psw
RX630 Group 14. Exception Handling 14.3.2 Vector and Site for Saving the Values in the PC and PSW The vector for each type of exception and the site for saving the values of the program counter (PC) and processor status word (PSW) are listed in Table 14.2 .
Page 302: Hardware Pre-Processing
RX630 Group 14. Exception Handling (2) Hardware Post-Processing for Execution of RTE and RTFI Instructions (a) Restoring PSW  For a fast interrupt BPSW  PSW  For exceptions other than a fast interrupt Stack  PSW (b) Restoring PC ...
Page 303: Reset
RX630 Group 14. Exception Handling 5. The fetched vector is set to the PC and processing branches to the exception handling routine. 14.5.5 Reset 1. The control registers are initialized. 2. The vector is fetched from address FFFF FFFCh. 3. The fetched vector is set to the PC. 14.5.6 Non-Maskable Interrupt 1.
Page 304: Return From Exception Handling Routine
RX630 Group 14. Exception Handling 14.6 Return from Exception Handling Routine Executing the instruction listed in Table 14.3 at the end of the corresponding exception handling routine restores the values of the program counter (PC) and processor status word (PSW) that were saved on the stack or in the control registers (BPC and BPSW) immediately before the exception handling sequence.
Page 305: Interrupt Controller (Icub)
RX630 Group 15. Interrupt controller (ICUb) Interrupt controller (ICUb) 15.1 Overview The interrupt controller receives interrupt signals from the peripheral modules and external pins, sends interrupts to the CPU, and activates the DTC and DMAC. Table 15.1 lists the specifications of the interrupt controller, and Figure 15.1 shows a block diagram of the interrupt controller.
Page 306 RX630 Group 15. Interrupt controller (ICUb) Interrupt Controller Clock Voltage monitoring 2 interrupt Clock restoration request Generation Voltage monitoring 1 interrupt IWDT underflow/refresh error Circuit WDT underflow/refresh error Oscillation stop detection interrupt Clock restoration Clock restoration enable level determination Digital NMI pin Detection filter...
Page 307: Register Descriptions
RX630 Group 15. Interrupt controller (ICUb) 15.2 Register Descriptions 15.2.1 Interrupt Request Register n (IRn) (n = interrupt vector number) Address(es): 0008 7010h to 0008 70FDh — — — — — — — Value after reset: Symbol Bit Name Description Interrupt Status Flag 0: No interrupt request is generated R/(W)
Page 308: Interrupt Request Enable Register M (Ierm) (M = 02H To 1Fh)
RX630 Group 15. Interrupt controller (ICUb) (2) Level detection [Setting conditions]  The flag remains set to 1 while an interrupt request is being sent from the corresponding peripheral module or IRQi pin. For interrupt generation by the various peripheral modules, refer to the sections describing the modules. ...
Page 309: Interrupt Source Priority Register N (Iprn) (N = 000 To 253)
RX630 Group 15. Interrupt controller (ICUb) 15.2.3 Interrupt Source Priority Register n (IPRn) (n = 000 to 253) Address(es): 0008 7300h to 0008 73FDh — — — — IPR[3:0] Value after reset: Symbol Bit Name Description b3 to b0 IPR[3:0] Interrupt Priority Level Select 0 0 0 0: Level 0 (interrupt disabled)* 0 0 0 1: Level 1...
Page 310: Fast Interrupt Set Register (Fir)
RX630 Group 15. Interrupt controller (ICUb) 15.2.4 Fast Interrupt Set Register (FIR) Address(es): 0008 72F0h FIEN — — — — — — — FVCT[7:0] Value after reset: Symbol Bit Name Description b7 to b0 FVCT[7:0] Fast Interrupt Vector Number Specify the vector number of an interrupt source to be a fast interrupt.
Page 311: Software Interrupt Activation Register (Swintr)
RX630 Group 15. Interrupt controller (ICUb) 15.2.5 Software Interrupt Activation Register (SWINTR) Address(es): 0008 72E0h — — — — — — — SWINT Value after reset: Symbol Bit Name Description SWINT Software Interrupt Activation This bit is read as 0. Writing 1 issues a software interrupt request. R/(W) Writing 0 to this bit has no effect.
Page 312: Dmac Activation Request Select Register M (Dmrsrm) (M = Dmac Channel Number)
RX630 Group 15. Interrupt controller (ICUb) 15.2.7 DMAC Activation Request Select Register m (DMRSRm) (m = DMAC channel number) Address(es): DMRSR0 0008 7400h, DMRSR1 0008 7404h DMRSR2 0008 7408h, DMRSR3 0008 740Ch DMRS[7:0] Value after reset: Symbol Bit Name Description b7 to b0 DMRS[7:0] DMAC Activation Source...
Page 313: Irq Control Register I (Irqcri) (I = 0 To 15)
RX630 Group 15. Interrupt controller (ICUb) 15.2.8 IRQ Control Register i (IRQCRi) (i = 0 to 15) Address(es): 0008 7500h to 0008 750Fh — — — — IRQMD[1:0] — — Value after reset: Symbol Bit Name Description b1, b0 — Reserved These bits are read as 0.
Page 314: Irq Pin Digital Filter Enable Register 0 (Irqflte0)
RX630 Group 15. Interrupt controller (ICUb) 15.2.9 IRQ Pin Digital Filter Enable Register 0 (IRQFLTE0) Address(es): 0008 7510h FLTEN FLTEN FLTEN FLTEN FLTEN FLTEN FLTEN FLTEN Value after reset: Symbol Bit Name Description FLTEN0 IRQ0 Digital Filter Enable 0: Digital filter is disabled. 1: Digital filter is enabled.
Page 315: Irq Pin Digital Filter Enable Register 1 (Irqflte1)
RX630 Group 15. Interrupt controller (ICUb) 15.2.10 IRQ Pin Digital Filter Enable Register 1 (IRQFLTE1) Address(es): 0008 7511h FLTEN FLTEN FLTEN FLTEN FLTEN FLTEN FLTEN FLTEN Value after reset: Symbol Bit Name Description FLTEN8 IRQ8 Digital Filter Enable 0: Digital filter is disabled. 1: Digital filter is enabled.
Page 316: Irq Pin Digital Filter Setting Register 0 (Irqfltc0)
RX630 Group 15. Interrupt controller (ICUb) 15.2.11 IRQ Pin Digital Filter Setting Register 0 (IRQFLTC0) Address(es): 0008 7514h FCLKSEL7[1:0] FCLKSEL6[1:0] FCLKSEL5[1:0] FCLKSEL4[1:0] FCLKSEL3[1:0] FCLKSEL2[1:0] FCLKSEL1[1:0] FCLKSEL0[1:0] Value after reset: Symbol Bit Name Description b1, b0 FCLKSEL0[1:0] IRQ0 Digital Filter Sampling Clock 0 0: PCLK 0 1: PCLK/8 b3, b2...
Page 317: Irq Pin Digital Filter Setting Register 1 (Irqfltc1)
RX630 Group 15. Interrupt controller (ICUb) 15.2.12 IRQ Pin Digital Filter Setting Register 1 (IRQFLTC1) Address(es): 0008 7516h FCLKSEL15[1:0] FCLKSEL14[1:0] FCLKSEL13[1:0] FCLKSEL12[1:0] FCLKSEL11[1:0] FCLKSEL10[1:0] FCLKSEL9[1:0] FCLKSEL8[1:0] Value after reset: Symbol Bit Name Description b1, b0 FCLKSEL8[1:0] IRQ8 Digital Filter Sampling Clock 0 0: PCLK 0 1: PCLK/8 b3, b2...
Page 318: Non-Maskable Interrupt Status Register (Nmisr)
RX630 Group 15. Interrupt controller (ICUb) 15.2.13 Non-Maskable Interrupt Status Register (NMISR) Address(es): 0008 7580h LVD2S LVD1S IWDTS — — WDTST OSTST NMIST Value after reset: Symbol Bit Name Description NMIST NMI Status Flag 0: NMI pin interrupt is not requested. 1: NMI pin interrupt is requested.
Page 319 RX630 Group 15. Interrupt controller (ICUb) WDTST Flag (WDT Underflow/Refresh Error Status Flag) This flag indicates the WDT underflow/refresh error interrupt request. The WDTST flag is read-only, and cleared by the NMICLR.WDTCLR bit. [Setting condition]  When the WDT underflow/refresh error interrupt is generated [Clearing condition] ...
Page 320: Non-Maskable Interrupt Enable Register (Nmier)
RX630 Group 15. Interrupt controller (ICUb) 15.2.14 Non-Maskable Interrupt Enable Register (NMIER) Address(es): 0008 7581h LVD2E LVD1E IWDTE WDTE — — OSTEN NMIEN Value after reset: Symbol Bit Name Description NMIEN NMI Pin Interrupt Enable 0: NMI pin interrupt is disabled R/(W) 1: NMI pin interrupt is enabled OSTEN...
Page 321: Non-Maskable Interrupt Status Clear Register (Nmiclr)
RX630 Group 15. Interrupt controller (ICUb) LVD2EN Bit (Voltage-Monitoring 2 Interrupt Enable) This bit enables the voltage-monitoring 2 interrupt. A 1 can be written to this bit only once, and subsequent write accesses are no longer enabled. Writing 0 to this bit is disabled. 15.2.15 Non-Maskable Interrupt Status Clear Register (NMICLR) Address(es): 0008 7582h...
Page 322: Nmi Pin Interrupt Control Register (Nmicr)
RX630 Group 15. Interrupt controller (ICUb) LVD2CLR Bit (LVD2 Clear) Writing 1 to the LVD2CLR bit clears the NMISR.LVD2ST flag. This bit is read as 0. 15.2.16 NMI Pin Interrupt Control Register (NMICR) Address(es): 0008 7583h — — — — NMIMD —...
Page 323: Nmi Pin Digital Filter Setting Register (Nmifltc)
RX630 Group 15. Interrupt controller (ICUb) 15.2.18 NMI Pin Digital Filter Setting Register (NMIFLTC) Address(es): 0008 7594h — — — — — — NFCLKSEL[1:0] Value after reset: Symbol Bit Name Description b1, b0 NFCLKSEL[1:0] NMI Digital Filter Sampling b1 b0 0 0: PCLK Clock 0 1: PCLK/8...
Page 324: Group M Interrupt Source Register (Grpm) (M: Group Number)
RX630 Group 15. Interrupt controller (ICUb) 15.2.19 Group m Interrupt Source Register (GRPm) (m: group number)  GRP00, GRP01, GRP02 Address(es): GRP00 0008 C300h, GRP01 0008 C304h, GRP02 0008 C308h — — — — — — — — — — —...
Page 325 RX630 Group 15. Interrupt controller (ICUb)  GRP12 Address(es): GRP12 0008 C330h — — — — — — — — — — — — — — — — Value after reset: IS15 IS14 IS13 IS12 IS11 IS10 Value after reset: Symbol Bit Name Description...
Page 326 RX630 Group 15. Interrupt controller (ICUb) [Clearing condition]  The ISj flag is cleared to 0 by writing 1 to the interrupt source clear bit in group m interrupt clear register (GCRm.CLRj). (2) Group 12 [Setting condition]  The ISj flag remains 1 while the corresponding peripheral module interrupt request is being sent and GENm.ENj is [Clearing conditions] ...
Page 327: Group M Interrupt Enable Register (Genm) (M = Group Number)
RX630 Group 15. Interrupt controller (ICUb) 15.2.20 Group m Interrupt Enable Register (GENm) (m = group number)  GEN00, GEN01, GEN02 Address(es): GEN00 0008 C340h, GEN01 0008 C344h, GEN02 0008 C348h — — — — — — — — — —...
Page 328 RX630 Group 15. Interrupt controller (ICUb)  GEN12 Address(es): GEN12 0008 C370h — — — — — — — — — — — — — — — — Value after reset: EN15 EN14 EN13 EN12 EN11 EN10 Value after reset: Symbol Bit Name Description...
Page 329: Group M Interrupt Clear Register (Gcrm) (M = Group Number)
RX630 Group 15. Interrupt controller (ICUb) 15.2.21 Group m Interrupt Clear Register (GCRm) (m = group number)  GCR00, GCR01, GCR02 Address(es): GCR00 0008 C380h, GCR01 0008 C384h, GCR02 0008 C388h — — — — — — — — — —...
Page 330: Unit Selecting Register (Sel)
RX630 Group 15. Interrupt controller (ICUb) 15.2.22 Unit Selecting Register (SEL) Address(es): 0008 C3C0h — — — — — — — — — — — — — — — — Value after reset: — — — — — — — —...
Page 331: Vector Table
RX630 Group 15. Interrupt controller (ICUb) 15.3 Vector Table There are two types of interrupts detected by the interrupt controller: maskable interrupts and non-maskable interrupts. When the CPU accepts an interrupt or non-maskable interrupt, it acquires a four-byte vector address from the vector table.
Page 332 RX630 Group 15. Interrupt controller (ICUb) Table 15.3 Interrupt Vector Table (1/6) Source of Vector Form of Interrupt Request Vector Address Interrupt Generation Name No.* Offset Detection DTCER — For an unconditional trap 0 0000h — × × × × ×...
Page 333 RX630 Group 15. Interrupt controller (ICUb) Table 15.3 Interrupt Vector Table (2/6) Source of Vector Form of Interrupt Request Vector Address Interrupt Generation Name No.* Offset Detection DTCER ○ ○ ○ RSPI2 SPRI2 00B4h Edge × × IER05.IEN5 IPR045 DTCER045 ○...
Page 334 RX630 Group 15. Interrupt controller (ICUb) Table 15.3 Interrupt Vector Table (3/6) Source of Vector Form of Interrupt Request Vector Address Interrupt Generation Name No.* Offset Detection DTCER — Reserved 016Ch — × × × × × — — — ○...
Page 335 RX630 Group 15. Interrupt controller (ICUb) Table 15.3 Interrupt Vector Table (4/6) Source of Vector Form of Interrupt Request Vector Address Interrupt Generation Name No.* Offset Detection DTCER ○ ○ ○ TPU3 TGI3A 0218h Edge × × IER10.IEN6 IPR134 DTCER134 ○...
Page 336 RX630 Group 15. Interrupt controller (ICUb) Table 15.3 Interrupt Vector Table (5/6) Source of Vector Form of Interrupt Request Vector Address Interrupt Generation Name No.* Offset Detection DTCER ○ ○ ○* TMR1 CMIA1 02B4h Edge × × IER15.IEN5 IPR173 DTCER173 ○...
Page 337 RX630 Group 15. Interrupt controller (ICUb) Table 15.3 Interrupt Vector Table (6/6) Source of Vector Form of Interrupt Request Vector Address Interrupt Generation Name No.* Offset Detection DTCER ○ ○ ○ SCI1 RXI1 0364h Edge × × IER1B.IEN1 IPR217 DTCER217 ○...
Page 338: Fast Interrupt Vector Table
RX630 Group 15. Interrupt controller (ICUb) 15.3.2 Fast Interrupt Vector Table The address of the entry in the interrupt vector table that corresponds to the vector number of the fast interrupt is placed in the fast interrupt vector register (FINTV) of the CPU. 15.3.3 Non-maskable Interrupt Vector Table The non-maskable interrupt vector table is at FFFF FFF8h.
Page 339 RX630 Group 15. Interrupt controller (ICUb) (3) List of Interrupt Requests for Each Group Table 15.4 lists the interrupt requests by group. Table 15.4 Group m Interrupt Requests (1/2) Interrupt Request Source Vector Interrupt GCRm.CLRj Group Request Name GENm.ENj Bit GRPm.ISj Flag Flag (IRn.IR)
Page 340: Unit Selection
RX630 Group 15. Interrupt controller (ICUb) Table 15.4 Group m Interrupt Requests (2/2) Interrupt Request Source Vector Interrupt Group Request Name GENm.ENj Bit GRPm.ISj Flag (IRn.IR) Group 12 SCI0 ERI0 (SCI0 reception error) GEN12.EN0 GRP12.IS0 SCI1 ERI1 (SCI1 reception error) GEN12.EN1 GRP12.IS1 SCI2...
Page 341: Interrupt Operation
RX630 Group 15. Interrupt controller (ICUb) Table 15.5 Unit n Interrupt Sources (n = 0 to 5) MTU2 Unit Pair No. Interrupt Request Interrupt Request Vector (selected by Source Source SEL.CNj bit) Interrupt Request Name Interrupt Request Name Interrupt Type (IRn.IR) Unit pair 0 TPU6...
Page 342: Operation Of Status Flags For Edge-Detected Interrupts
RX630 Group 15. Interrupt controller (ICUb) Grouped interrupt requests are classified into two groups; edge detection interrupt request group and level detection interrupt request group, and retained in the GRPm register (m = group number, 0 to 6 or 12). In both groups, the IRn.IR flag operates as the level interrupt.
Page 343 RX630 Group 15. Interrupt controller (ICUb) While the IRn.IR flag is 1 after an interrupt request is generated, the interrupt request that is generated again will be ignored. * Figure 15.6 shows the timing for IRn.IR flag re-setting. Note 1. When the transmission or reception interrupt of the SCI, RSPI, or RIIC is generated with the IRn.IR flag being 1, the interrupt request is retained.
Page 344: Operation Of Status Flags For Level-Detected Interrupts
RX630 Group 15. Interrupt controller (ICUb) 15.5.1.2 Operation of Status Flags for Level-Detected Interrupts Figure 15.8 shows the operation of the interrupt status flag (IR flag) in IRn in the case of level detection of an interrupt from a peripheral module or an external pin. The IR flag in IRn remains set to 1 as long as the interrupt signal is asserted.
Page 345: Edge Detection Group Interrupts And Interrupt Status Flags
RX630 Group 15. Interrupt controller (ICUb) 15.5.1.3 Edge Detection Group Interrupts and Interrupt Status Flags Edge detection interrupt requests are grouped into groups 0 to 6. The IRn.IR flag corresponding to the groups operates assuming the interrupt requests as level detection interrupts. Figure 15.10 shows an operation example in which an edge detection interrupt request is generated and Figure 15.11 shows an operation example in which multiple edge detection interrupt requests allocated to a group are generated.
Page 346 RX630 Group 15. Interrupt controller (ICUb) Start interrupt handling Interrupt has been generated Confirmation of GRPm.ISj Interrupt has not been generated Write 1 to the GCRm.CLRj bit Confirmation of the interrupt Interrupt has not request source for GRPm.ISj been generated Interrupt has been Confirm generated...
Page 347: Level Detection Group Interrupts And Interrupt Status Flags
RX630 Group 15. Interrupt controller (ICUb) 15.5.1.4 Level Detection Group Interrupts and Interrupt Status Flags Level detection interrupt requests are grouped into group 12. The IRn.IR flag corresponding to the group operates assuming the interrupt requests as level detection interrupts. Figure 15.14 shows an operation example in which a level detection interrupt request is generated and Figure 15.15 shows an operation example in which multiple level detection interrupt requests of a group are generated.
Page 348: Unit Selection And Interrupt Status Flags
RX630 Group 15. Interrupt controller (ICUb) Start interrupt handling Interrupt has not been generated Interrupt has been generated Confirm GRPm.ISj Interrupt has not been generated Confirm interrupt request source for GRPm.ISj Interrupt has been generated IRn.IR = 1 Confirm IRn.IR flag IRn.IR = 0 Clear interrupt request source, and perform interrupt request source processing...
Page 349: Enabling And Disabling Interrupt Sources
RX630 Group 15. Interrupt controller (ICUb) 15.5.2 Enabling and Disabling Interrupt Sources Enabling requests from a given interrupt source requires the following settings. 1. In the case of interrupt requests from peripheral modules, setting the interrupt enable bit for the peripheral module to permit the output of interrupt requests from the source 2.
Page 350: Selecting Interrupt Request Destinations
RX630 Group 15. Interrupt controller (ICUb) 15.5.3 Selecting Interrupt Request Destinations Possible settings for the request destination of each interrupt are fixed. That is, settings for request destination other than those indicated in Table 15.3, Interrupt Vector Table , are not possible. Do not make an interrupt request destination setting that is not indicated by a O in Table 15.3 .
Page 351: Determining Priority
RX630 Group 15. Interrupt controller (ICUb) Table 15.6 Operation at DMAC/DTC Activation Remaining Interrupt Number of Request Transfer Operation per Destination DISEL Operations Request Interrupt Request Destination after Transfer DMA transfer  ≠ 0 DMAC Cleared on interrupt acceptance by the CPU DMAC CPU interrupt DMA transfer ...
Page 352: Fast Interrupt
RX630 Group 15. Interrupt controller (ICUb) (2) Determining Priority when the DTC is the Request Destination of the Interrupt Signal The IPR[3:0] bits in IPRn have no effect. An interrupt source with a smaller vector number takes precedence. (3) Determining Priority when the DMAC is the Request Destination of the Interrupt Signal The IPR[3:0] bits in IPRn have no effect.
Page 353: External Pin Interrupts
RX630 Group 15. Interrupt controller (ICUb) 15.5.7 External Pin Interrupts The procedure for using the signal on an external pin as an interrupt is as follows. 1. Clear the IERm.IENj bit to 0 (interrupt request disabled). 2. Clear the IRQFLTCn.FCLKSELi[1:0] bits (n = 0 or 1, i = 0 to 15) to 0 (digital filter disabled). 3.
Page 354: Return From Power-Down States
RX630 Group 15. Interrupt controller (ICUb) 15.7 Return from Power-Down States The interrupt sources that can be used to return operation from sleep mode, all-module clock stop mode, or software standby mode are listed in Table 15.3, Interrupt Vector Table . For details, refer to section 11, Low Power Consumption .
Page 355: Return From Software Standby Mode
RX630 Group 15. Interrupt controller (ICUb) 15.7.3 Return from Software Standby Mode The interrupt controller can return operation from a non-maskable interrupt or an interrupt that enables the return from the software standby mode. The conditions for the return are listed below. ...
Page 356: Buses
RX630 Group 16. Buses Buses 16.1 Overview Table 16.1 lists the bus specifications, Figure 16.1 shows the bus configuration, and Table 16.2 lists the addresses assigned for each bus. Table 16.1 Bus Specifications Bus Type Description  Connected to the CPU (for instructions) CPU bus Instruction bus ...
Page 357 RX630 Group 16. Buses ICLK synchronization Instruction bus Operand bus Memory bus 1 Memory bus 2 Bus error monitoring section DTC/ DMAC (m) Internal main bus 1 Internal main bus 2 Internal peripheral Internal peripheral bus 1 buses 2 and 3 Internal peripheral bus 6 BCLK Peripheral...
Page 358: Description Of Buses
RX630 Group 16. Buses Table 16.2 Addresses Assigned for Each Bus Area On-Chip ROM Mode On-Chip ROM Mode Address Enabled Disabled Enabled Disabled 0000 0000h to 0001 FFFFh Memory bus 1 0002 0000h to 0007 FFFFh Reserved area 0008 0000h to 0008 7FFFh Internal peripheral bus 1 Peripheral I/O registers 0008 8000h to 0009 FFFFh...
Page 359: Internal Main Buses
RX630 Group 16. Buses 16.2.3 Internal Main Buses The internal main buses consist of a bus for use by the CPU (internal main bus 1) and a bus for use by the other bus- master modules, i.e. the DTC, DMAC DMAC (internal main bus 2). Bus requests for instruction fetching and operand access are arbitrated through internal main bus 1.
Page 360: Write Buffer Function (Internal Peripheral Bus)
RX630 Group 16. Buses Priority order fixed: Internal main bus 1 (R11) (R11) (R11) (R13) (R13) Internal main bus 2 Priority order toggled: Internal main bus 1 (R11) (R12) (R22) Internal main bus 2 (1), (2) : The priority order does not change because the priority of the accepted request is low. Request issued;...
Page 361: External Bus
RX630 Group 16. Buses 16.2.6 External Bus Table 16.5 lists the specifications of the external bus. The external bus controller arbitrates requests for bus mastership from internal main bus 1, and internal main bus 2.. The priority order of these two buses can be set using the external bus priority control bits (BPEB[1:0]) in the bus priority control register (BUSPRI).
Page 362 RX630 Group 16. Buses Table 16.6 lists the input/output pins of the external bus. Table 16.6 Pin Configuration of the External Bus Pin Name Description A23 to A0* Output Address output pins D31 to D0 Data input/output pins D31 to D0 pins are enabled when the 32-bit bus space is specified. D15 to D0 pins are enabled when the 16-bit bus space is specified.
Page 363: Parallel Operation
RX630 Group 16. Buses 16.2.7 Parallel Operation Parallel operation is possible when different bus-master modules are requesting access to different slave modules. For example, if the CPU is fetching an instruction from ROM and an operand from RAM, the DMAC is able to handle transfer between a peripheral bus and the external bus at the same time.
Page 364: Register Descriptions
RX630 Group 16. Buses 16.3 Register Descriptions 16.3.1 CSn Control Register (CSnCR) (n = 0 to 7) Address(es): CS0CR 0008 3802h EMOD — — — MPXEN — — — — — BSIZE[1:0] — — — EXENB Value after reset: Address(es): CS1CR 0008 3812h, CS2CR 0008 3822h, CS3CR 0008 3832h, CS4CR 0008 3842h, CS5CR 0008 3852h, CS6CR 0008 3862h, CS7CR 0008 3872h EMOD —...
Page 365: Csn Recovery Cycle Register (Csnrec) (N = 0 To 7)
RX630 Group 16. Buses BSIZE[1:0] Bits (External Bus Width Select) These bits specify the data bus width of each area. The data bus width of area 0 (CS0) after a reset depends on the setting of the bus width in operating mode. When the address/data multiplexed I/O interface is selected with the MPXEN bit, the BSIZE[1:0] bits should not be set to the 32-bit bus space.
Page 366 RX630 Group 16. Buses Do not write to the CSnREC register while access to the CSn area is in progress. When the preceding bus access is a separate bus access, CSnREC is valid when the recovery cycle insertion is enabled with the separate bus recovery cycle insertion enable bit (RCVENj (j = 0 to 7)) in CSRECEN.
Page 367: Cs Recovery Cycle Insertion Enable Register (Csrecen)
RX630 Group 16. Buses 16.3.3 CS Recovery Cycle Insertion Enable Register (CSRECEN) Address(es): 0008 3880h RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN RCVEN Value after reset: Symbol Bit Name Description RCVEN0 Separate Bus Recovery Cycle Insertion Enable 0: Recovery cycle insertion is disabled.
Page 368 RX630 Group 16. Buses Table 16.7 Insertion of Recovery Cycles External Address Corresponding Bits Access Type Space Insertion of Recovery Cycles (Separate/Multiplexed) Read access after read access Same area Recovery cycles specified by the RCVEN0/RCVENM0 RRCV[3:0] bits are inserted. Different area Recovery cycles specified by the RCVEN1/RCVENM1 RRCV[3:0] bits are inserted.
Page 369: Csn Mode Register (Csnmod) (N = 0 To 7)
RX630 Group 16. Buses 16.3.4 CSn Mode Register (CSnMOD) (n = 0 to 7) Address(es): CS0MOD 0008 3002h, CS1MOD 0008 3012h, CS2MOD 0008 3022h, CS3MOD 0008 3032h, CS4MOD 0008 3042h, CS5MOD 0008 3052h, CS6MOD 0008 3062h, CS7MOD 0008 3072h PRMO PWEN EWEN WRMO...
Page 370 RX630 Group 16. Buses PRENB Bit (Page Read Access Enable) This bit enables or disables page read accesses. Note: • When the address/data multiplexed I/O interface is selected with the MPXEN bit in CSnCR, this bit should not be set to enable page read accesses. Page read accesses are not supported in the address/data multiplexed I/O interface.
Page 371: Csn Wait Control Register 1 (Csnwcr1) (N = 0 To 7)
RX630 Group 16. Buses 16.3.5 CSn Wait Control Register 1 (CSnWCR1) (n = 0 to 7) Address(es): CS0WCR1 0008 3004h, CS1WCR1 0008 3014h, CS2WCR1 0008 3024h, CS3WCR1 0008 3034h, CS3WCR1 0008 3044h, CS5WCR1 0008 3054h, CS6WCR1 0008 3064h, CS7WCR1 0008 3074h —...
Page 372 RX630 Group 16. Buses Symbol Bit Name Description b20 to b16 CSWWAIT[4:0] Normal Write Cycle Wait Select 0 0 0 0 0: No wait is inserted. 0 0 0 0 1: Wait with a length of 1 clock cycle is inserted. 0 0 0 1 0: Wait with a length of 2 clock cycles are inserted.
Page 373 RX630 Group 16. Buses Do not write to the CSnWCR1 register while access to the CSn area is in progress. Set each of these bits within a range of the restrictions described in section 16.5.7 (1) Limitations on Using Separate Bus Interface or section 16.5.7 (2) Limitations on Using Address/Data Multiplexed Bus Interface , according to the bus interface used.
Page 374: Csn Wait Control Register 2 (Csnwcr2) (N = 0 To 7)
RX630 Group 16. Buses 16.3.6 CSn Wait Control Register 2 (CSnWCR2) (n = 0 to 7) Address(es): CS0WCR2 0008 3008h, CS1WCR2 0008 3018h, CS2WCR2 0008 3028h, CS3WCR2 0008 3038h, CS4WCR2 0008 3048h, CS5WCR2 0008 3058h, CS6WCR2 0008 3068h, CS7WCR2 0008 3078h —...
Page 375 RX630 Group 16. Buses Symbol Bit Name Description b22 to b20 WRON[2:0] WR Assert Wait Select 0 0 0: No wait is inserted. 0 0 1: Wait with a length of 1 clock cycle is inserted. 0 1 0: Wait with a length of 2 clock cycles are inserted. 0 1 1: Wait with a length of 3 clock cycles are inserted.
Page 376 RX630 Group 16. Buses CSnWCR1.CSWWAIT[4:0] value and CSnWCR2.AWAIT[1:0] value + 2 ≤ CSnWCR2.WDON[2:0] value ≤ CSnWCR1.CSWWAIT[4:0] value. RDON[2:0] Bits (RD Assert Wait Select) These bits specify the number of wait cycles to be inserted before the RD# signal is asserted. Note: •...
Page 377: Bus Error Status Clear Register (Berclr)
RX630 Group 16. Buses 16.3.7 Bus Error Status Clear Register (BERCLR) Address(es): 0008 1300h STSCL — — — — — — — Value after reset: Symbol Bit Name Description STSCLR Status Clear 0: Invalid (W)* 1: Bus error status register cleared b7 to b1 —...
Page 378: Bus Error Status Register 1 (Bersr1)
RX630 Group 16. Buses 16.3.9 Bus Error Status Register 1 (BERSR1) Address(es): 0008 1308h — MST[2:0] — — Value after reset: Symbol Bit Name Description Illegal Address Access 0: Illegal address access not made 1: Illegal address access made Timeout 0: Timeout not generated 1: Timeout generated b3, b2...
Page 379: Bus Priority Control Register (Buspri)
RX630 Group 16. Buses 16.3.11 Bus Priority Control Register (BUSPRI) Address(es): 0008 1310h — — BPEB[1:0] BPFB[1:0] — — BPGB[1:0] BPIB[1:0] BPRO[1:0] BPRA[1:0] Value after reset: Symbol Bit Name Description b1, b0 BPRA[1:0] Memory Bus 1 (RAM) Priority b1 b0 R(/W) 0 0: The order of priority is fixed.
Page 380 RX630 Group 16. Buses When the priority order is fixed, internal main bus 2 has priority over internal main bus 1. When the priority order is toggled, a bus has a lower priority when the request of that bus is accepted. BPGB[1:0] Bits (Internal Peripheral Bus 2 and 3 Priority Control) These bits specify the priority order for internal peripheral buses 2 and 3.
Page 381: Endian And Data Alignment
RX630 Group 16. Buses 16.4 Endian and Data Alignment The external bus has a data-alignment function to control which byte of the data bus (D31 to D24, D23 to D16, D15 to D8, or D7 to D0) is used according to the bus specifications of the area to be accessed (8-bit, 16-bit, or 32-bit bus space), data size, and endian format when accessing the external address space (the CS).
Page 382 RX630 Group 16. Buses WR3#/BC3# WR2#/BC2# WR1#/BC1# WR0#/BC0# Number Data Bus Unit of Access Bus Cycle Address Data Data Size Address Access First 8 bits 4n+1 First 8 bits 8 bits 4n+2 First 8 bits 4n+3 First 8 bits First 16 bits First 8 bits...
Page 383 RX630 Group 16. Buses WR1#/BC1# WR0#/BC0# Access Number of Data Bus Bus Cycle Unit of Data Address Data Size Address Access First 8 bits 4n+1 First 8 bits 8 bits 4n+2 First 8 bits 4n+2 4n+3 First 8 bits 4n+2 First 16 bits First...
Page 384 RX630 Group 16. Buses WR1#/BC1# WR0#/BC0# Access Number of Data Bus Bus Cycle Unit of Data Address Data Size Address Access First 8 bits 4n+1 First 8 bits 8 bits 4n+2 First 8 bits 4n+2 4n+3 First 8 bits 4n+2 First 16 bits First...
Page 385 RX630 Group 16. Buses (3) 8-Bit Bus Space When an 8-bit bus space is selected by the BSIZE[1:0] bits in CSnCR, the address buses A23 to A0 are enabled to output address signals in byte units. In 8-bit bus space, only the WR0# pin is valid regardless of write access mode, and always outputs the low level during write access.
Page 386 RX630 Group 16. Buses WR1#/BC1# WR0#/BC0# Access Number of Data Bus Bus Cycle Unit of Data Address Data Size Address Access First 8 bits 4n+1 First 8 bits 4n+1 8 bits 4n+2 First 8 bits 4n+2 4n+3 First 8 bits 4n+3 First 8 bits...
Page 387: Operation Of Cs Area Controller
RX630 Group 16. Buses 16.5 Operation of CS Area Controller 16.5.1 Separate Bus The various periods in the timing charts are described below. The CS area controller (CSC) operates in synchronization with the external bus clock (BCLK). The operation cycles, such as wait cycles specified with the CSC register, are counted on BCLK.
Page 388 RX630 Group 16. Buses For write access, setting the write data output extension cycle select bits (WDOFF) controls extension of the period where the address and output data are valid. (d) Tdw1 to Tdwn (Write-Data Output Extension Clock Cycles) For write access, if the setting for write-data output extension wait is a value other than zero, clock cycles of write-data output extension are inserted from the cycle that follows the cycle where the strobe signal is valid (Tend).
Page 389 RX630 Group 16. Buses Next bus access can be started Tend External bus clock (BCLK) Normal read cycle wait (CSRWAIT) Read-access CS extension cycle (CSROFF) Address (A23 to A0) (A23 to A0) CS assert wait (CSON) Chip select (CSn#) Byte control (BCm#) RD assert wait (RDON) Data read...
Page 390 RX630 Group 16. Buses Tend Tend External bus clock (BCLK) Address (A23 to A0) (A23 to A0) Normal write cycle wait (CSWWAIT): 2 Normal read cycle wait (CSRWAIT): 2 Write-access CS extension cycle Read-access CS extension (CSWOFF): 1 CS assert wait (CSON): 0 cycle (CSROFF): 1 Chip select/byte control...
Page 391 RX630 Group 16. Buses Tend Tend External bus clock (BCLK) Normal read cycle wait (CSRWAIT): 2 Address to D0) (A23 to A0) Read-access CS extension cycle (CSROFF): 1 CSRWAIT: 2 CSROFF: 1 Chip select (CSn#) Byte control (BCm#) RD assert wait (RDON): 1 RDON: 1 Data read (RD#)
Page 392 RX630 Group 16. Buses Figure 16.17 and Figure 16.18 show examples of normal read and write accesses to a 32-bit bus space in 16 bits. Tend External bus clock (BCLK) Normal read cycle wait (CSRWAIT): 4 Address (A23 to A0) Read-access CS extension cycle (CSROFF): 2 Chip select (CSn#)
Page 393 RX630 Group 16. Buses Tend External bus clock (BCLK) Normal write cycle wait (CSWWAIT): 4 Address (A23 to A0) Write-access CS extension cycle (CSWOFF): 2 Chip select (CSn#) CS assert wait (CSON): 1 Data write 3 (WR3#) Data write 2 (WR2#) WR assert wait (WRON): 2 Data write 1...
Page 394 RX630 Group 16. Buses Figure 16.19 to Figure 16.23 show examples of normal accesses made with the 1/2 BCLK selected with the BCLK pin output select bit. Tend Tend BCLK pin output External bus clock (BCLK) Address to D0) (A23 to A0) Write-access CS extension cycle Normal read cycle wait Normal write cycle wait...
Page 395 RX630 Group 16. Buses Tend Tend BCLK pin output External bus clock (BCLK) Address (A23 to A0) to D0) Write-access CS extension Normal write cycle wait (CSWWAIT): 3 CSWWAIT: 3 cycle (CSWOFF): 1 CSWOFF : 1 Chip select (CSn#) CS assert wait (CSON): 1 CSON: 1 Byte control (BCm#)
Page 396 RX630 Group 16. Buses Tend Tend BCLK pin output External bus clock (BCLK) Address (A23 to D0) (A23 to A0) Write-access CS extension cycle Normal write cycle wait (CSWOFF): 1 (CSWWAIT): 3 CSWWAIT: 3 CSWOFF: 1 Chip select (CSn#) CS assert wait (CSON): 1 CSON: 1 Byte control (BCm#)
Page 397 RX630 Group 16. Buses Next bus access can be started Tend Tpw1 Tpwn Tend External bus clock (BCLK) Read-access CS extension cycle Normal read cycle wait (CSRWAIT) Page read cycle wait (CSPRWAIT) (CSROFF) Address (A23 to D0) (A23 to A0) CS assert wait (CSON) Chip select (CSn#)
Page 398 RX630 Group 16. Buses Figure 16.26 and Figure 16.27 show examples of operations for access to a 16-bit bus space in 32 bits. The values of the wait control registers are example settings. In practice, the register settings will correspond to the specifications of connected devices.
Page 399 RX630 Group 16. Buses CSWWAIT: 4 CSPWWAIT: 4 Tend Tdw1 Tpw1 Tend External bus clock (BCLK) Address (A23 to A0) CSWOFF: 1 Chip select (CSn#) Byte control (BC3#, BC2#) Byte control (BC1#, BC0#) WRON: 1 WRON: 1 Data write (WR#) Data bus (D31 to D16) WDON: 1...
Page 400 RX630 Group 16. Buses Figure 16.28 and Figure 16.29 show examples of page access operations performed with the 1/2 BCLK selected with the BCLK pin output select bit. CSRWAIT: 5 CSRWAIT: 3 Tend Tpw1 Tpw2 Tpw3 Tend BCLK pin output External bus clock (BCLK) Address...
Page 401 RX630 Group 16. Buses CSPWWAIT: 4 CSWWAIT: 4 Tend Tdw1 Tpw1 Tpw2 Tpw3 Tpw4 Tend BCLK pin output External bus clock (BCLK) Address (A23 to A0) CSWOFF: 1 Chip select (CSn#) Byte control (BC3#, BC2#) Byte control (BC1#, BC0#) WRON: 1 WRON: 1 Data write0 (WR0#)
Page 402: Address/Data Multiplexed Bus
RX630 Group 16. Buses 16.5.2 Address/Data Multiplexed Bus When the address/data multiplexed I/O interface select bit (MPXEN) in CSnCR is set to 1, addresses and data can be multiplexing input/output to/from the D15 to D0 pins in the corresponding area. Using this function enables direct connection of this LSI to peripheral LSIs requiring address/data multiplexing.
Page 403 RX630 Group 16. Buses Figure 16.30 to Figure 16.32 show examples of operations with the address/data multiplexed I/O interface. Address cycle Data cycle Tend External bus clock (BCLK) Address Address cycle wait (AWAIT) Address/data bus 1 cycle fixed Address latch (ALE) RD assert wait (RDON) Data read...
Page 404 RX630 Group 16. Buses Address cycle Data cycle Address cycle Data cycle Twn Tend Tn1 Twn Tend Tn1 BCLK output External bus clock (BCLK) Address Write data output wait (WDON): 4 Data output extension cycle Address cycle wait (AWAIT): 1 Address cycle wait (AWAIT): 1 (WDOFF): 1 Address/data...
Page 405: External Wait Function
RX630 Group 16. Buses 16.5.3 External Wait Function Wait cycles can be extended by the WAIT# signal over the length of normal access cycle wait (specified by the CSRWAIT[4:0] and CSWWAIT[4:0] bits in CSnWCR1) and page access cycle wait (specified by the CSPRWAIT[2:0] and CSPWWAIT[2:0] bits in CSnWCR1).
Page 406 RX630 Group 16. Buses (Tend) (Tend) Tend Tdw1 … Tend Tdw1 Tpw1 … Tpwn External bus clock (BCLK) Address (A23 to A0) (A23 to D0) Chip select (CSn#) Data read (RD#) WR assert wait (WRON) WR assert wait (WRON) Data write (WRm#) Page write cycle wait (CSPWWAIT) Write cycle wait (CSWWAIT)
Page 407: Insertion Of Recovery Cycles
RX630 Group 16. Buses 16.5.4 Insertion of Recovery Cycles Recovery cycles can be inserted between consecutive rounds of external bus access by setting the recovery cycle insertion enable bit in CSRECEN to 1. The number of recovery cycles to be inserted after read cycles and write cycles can be separately set for each area using CSnREC.
Page 408 RX630 Group 16. Buses Figure 16.36 to Figure 16.38 show examples of recovery cycle insertion with the separate bus interface. CS0 write recovery CS0 read recovery CS0 write CS0 read (CS0REC.WRCV[3:0]): 4 (CS0REC.RRCV[3:0]): 4 CS1 read Tw1 Tw2 Tend Tw1 Tw2 Tend Tw1 Tw2 Tw3 Tend External bus clock (BCLK)
Page 409 RX630 Group 16. Buses CS0 write recovery CS1 read recovery (CS0REC.WRCV[3:0]): 2 (CS1REC.RRCV[3:0]): 2 CS0 write (1) CS0 write (2) CS1 read (1) CS1 read (2) Tw1 Tw2 Tpw1 Tpw2 Tend Tpw3 Tend Tr1 Tw1 Tw2 Tw3 Tend Tpw1 Tpw2 Tpw3 Tend External bus clock...
Page 410: No Access State
RX630 Group 16. Buses CS0 write recovery CS0 read recovery (CS0REC.WRCV[3:0]): 3 (CS0REC.RRCV[3:0]): 2 CS1 read CS0 write CS0 read Tw1 Tw2 Tend Tw1 Tw2 Tw3 Tw4 Tend Tw1 Tw2 Tw3 Tend External bus clock (BCLK) Address Address/data bus Address latch (ALE) Chip select 0 (CS0#)
Page 411: Write Buffer Function (External Bus)
RX630 Group 16. Buses 16.5.6 Write Buffer Function (External Bus) The internal main bus is released by writing data to the write buffer before the write access is completed, which allows the next round of bus access to start. However, if the following round of bus access is to an external address space or to a register of the external bus controller, it is suspended until the external bus operations already in progress are completed.
Page 412 RX630 Group 16. Buses (2) Limitations on Using Address/Data Multiplexed Bus Interface  In the address/data multiplexed I/O space, page accesses are invalid. If a page access setting is specified, the setting is ignored and the normal read or write operation is performed. ...
Page 413: Bus Error Monitoring Section
RX630 Group 16. Buses 16.6 Bus Error Monitoring Section The bus error monitoring section monitors the individual areas for bus errors, and when a bus error occurs, the error is indicated to the bus master. 16.6.1 Types of Bus Error There are two types of bus error: illegal address access and timeout.
Page 414: Conditions Leading To Bus Errors
RX630 Group 16. Buses 16.6.3 Conditions Leading to Bus Errors Table 16.11 lists the types of bus errors for each area in the respective address space. If an illegal address access error or timeout is detected when no bus error has occurred (bus error status register n (BERSRn;...
Page 415: Memory-Protection Unit (Mpu)
RX630 Group 17. Memory-Protection Unit (MPU) Memory-Protection Unit (MPU) 17.1 Overview The RX CPU incorporates a memory-protection unit that checks the addresses of CPU access to the overall address space (0000 0000h to FFFF FFFFh). Access-control information can be set for up to eight regions, and permission for access to each region is in accord with this information.
Page 416 RX630 Group 17. Memory-Protection Unit (MPU) CPU instruction address CPU operand access address Processor mode Access control Background access-control register End page number register Start page number register Region 0 Start page number End page number Access control Region 7 Region 0 Region 7 ...
Page 417: Types Of Access Control
RX630 Group 17. Memory-Protection Unit (MPU) 17.1.1 Types of Access Control There are three types of access control information: permission for instruction execution, permission to read operands, and permission to write operands. Violations of these types of access control are only detected when programs are running in user mode.
Page 418: Register Descriptions
RX630 Group 17. Memory-Protection Unit (MPU) 17.2 Register Descriptions 17.2.1 Region-n Start Page Number Register (RSPAGEn) (n = 0 to 7) Addresses: RSPAGE0 0008 6400h, RSPAGE1 0008 6408h, RSPAGE2 0008 6410h, RSPAGE3 0008 6418h RSPAGE4 0008 6420h, RSPAGE5 0008 6428h, RSPAGE6 0008 6430h, RSPAGE7 0008 6438h RSPN[27:0] Value after reset: RSPN[27:0]...
Page 419: Region-N End Page Number Register (Repagen) (N = 0 To 7)
RX630 Group 17. Memory-Protection Unit (MPU) 17.2.2 Region-n End Page Number Register (REPAGEn) (n = 0 to 7) Addresses: REPAGE0 0008 6404h, REPAGE1 0008 640Ch, REPAGE2 0008 6414h, REPAGE3 0008 641Ch REPAGE4 0008 6424h, REPAGE5 0008 642Ch, REPAGE6 0008 6434h, REPAGE7 0008 643Ch REPN[27:0] Value after reset: REPN[27:0]...
Page 420: Memory-Protection Enable Register (Mpen)
RX630 Group 17. Memory-Protection Unit (MPU) 17.2.3 Memory-Protection Enable Register (MPEN) Address: 0008 6500h — — — — — — — — — — — — — — — — Value after reset: — — — — — — — —...
Page 421: Background Access Control Register (Mpbac)
RX630 Group 17. Memory-Protection Unit (MPU) 17.2.4 Background Access Control Register (MPBAC) Address: 0008 6504h — — — — — — — — — — — — — — — — Value after reset: — — — — — — —...
Page 422: Memory-Protection Error Status-Clearing Register (Mpeclr)
RX630 Group 17. Memory-Protection Unit (MPU) 17.2.5 Memory-Protection Error Status-Clearing Register (MPECLR) Address: 0008 6508h — — — — — — — — — — — — — — — — Value after reset: — — — — — — —...
Page 423: Memory-Protection Error Status Register (Mpests)
RX630 Group 17. Memory-Protection Unit (MPU) 17.2.6 Memory-Protection Error Status Register (MPESTS) Address: 0008 650Ch — — — — — — — — — — — — — — — — Value after reset: — — — — — — —...
Page 424: Data Memory-Protection Error Address Register (Mpdea)
RX630 Group 17. Memory-Protection Unit (MPU) 17.2.7 Data Memory-Protection Error Address Register (MPDEA) Address: 0008 6514h DEA[31:0] Value after reset: DEA[31:0] Value after reset: x: Undefined Symbol Bit Name Function b31 to b0 DEA[31:0] Data Memory-Protection Error Address Data memory-protection error address DEA[31:0] Bits (Data Memory-Protection Error Address) These bits retain the address for which operand access generated a memory-protection error.
Page 425: Region Search Operation Register (Mpops)
RX630 Group 17. Memory-Protection Unit (MPU) 17.2.9 Region Search Operation Register (MPOPS) Address: 0008 6524h — — — — — — — — — — — — — — — Value after reset: Symbol Bit Name Function Region Search Operation [Reading] 0: Fixed value for reading [Writing]...
Page 426: Instruction-Hit Region Register (Mhiti)
RX630 Group 17. Memory-Protection Unit (MPU) 17.2.11 Instruction-Hit Region Register (MHITI) Address: 0008 6528h — — — — — — — — HITI[7:0] Value after reset: — — — — — — — — — — — — UHACI[2:0] — Value after reset: Symbol Bit Name...
Page 427: Data-Hit Region Register (Mhitd)
RX630 Group 17. Memory-Protection Unit (MPU) UHACI[2:0] Bits (Instruction-Hit Region Access Control Bits in User Mode) These bits hold the user-mode access control bits (REPAGEn.UAC[2:0]) for the region where the instruction memory- protection error was generated. If the error was generated in an overlap between regions, the value stored here is the logical OR of the user-mode access control bits for the corresponding regions (including the background region).
Page 428 RX630 Group 17. Memory-Protection Unit (MPU) Symbol Bit Name Function b23 to b16 HITD[7:0] Data-Hit Region When the data memory-protection error generated (DA) bit = 1, [b23:b16] = 0000 0000b indicates that attempted access to the background region led to a data memory- protection error.
Page 429: Functions
RX630 Group 17. Memory-Protection Unit (MPU) 17.3 Functions 17.3.1 Memory Protection Memory protection means monitoring, in accord with the access-control information that has been set for the individual access-control regions and the background region, whether or not access by programs running in user mode violates the access-control settings.
Page 430: Flow For Determination Of Access By The Memory-Protection Function
RX630 Group 17. Memory-Protection Unit (MPU) 17.3.4 Flow for Determination of Access by the Memory-Protection Function Figure 17.2 shows the flow of determination in the case of data access and Figure 17.3 shows the flow of determination in the case of instruction access. Data access by the CPU Processor mode? Supervisor mode...
Page 431 RX630 Group 17. Memory-Protection Unit (MPU) Instruction access by the CPU Processor mode? Supervisor mode Permit instruction access User mode Is memory protection enabled? Permit instruction access Is access to an access- control region? Determination in accord with Determination in accord with Access prohibited Access prohibited the access-control information...
Page 432: Procedures For Using Memory Protection
RX630 Group 17. Memory-Protection Unit (MPU) 17.4 Procedures for Using Memory Protection 17.4.1 Setting Access-Control Information Access-control information for the various regions is set in supervisor mode. Settings for up to eight access-control regions are made in the region-n start page number registers (RSPAGEn) and region-n end page number registers (REPAGEn), where n = 0 to 7.
Page 433 RX630 Group 17. Memory-Protection Unit (MPU) When a data memory-protection error is generated Access-exception processing by the CPU saves the address of the instruction that led to the memory-protection error on the stack. Furthermore, the address of the operand for which access led to a memory-protection error is stored in the data memory-protection error address register (MPDEA) and the region information for the region where the memory- protection error was generated is stored in the data-hit region register (MHITD).
Page 434: Dma Controller (Dmaca)
RX630 Group 18. DMA Controller (DMACA) DMA Controller (DMACA) The RX630 Group incorporates a 4-channel direct memory access controller (DMAC). The DMAC is a module to transfer data without the CPU. When a DMA transfer request is generated, the DMAC transfers data stored at the transfer source address to the transfer destination address.
Page 435 RX630 Group 18. DMA Controller (DMACA) DMAC Activation control DMAC registers DMAC channels (CH0 to CH3) DMSAR DMA start transfer DMDAR request request DMCRA arbitration DMCRB DMOFR DMTMD Interrupt DMAMD controller DMSTS DMCNT DMAC response Interrupt request Register control DMAC response control DMAC core Source address...
Page 436: Register Descriptions
RX630 Group 18. DMA Controller (DMACA) 18.2 Register Descriptions 18.2.1 DMA Source Address Register (DMSAR) Address(es): DMAC0.DMSAR 0008 2000h, DMAC1.DMSAR 0008 2040h DMAC2.DMSAR 0008 2080h, DMAC3.DMSAR 0008 20C0h Value after reset: Value after reset: Description Setting Range b31 to b0 Specifies the transfer source start address.
Page 437: Dma Transfer Count Register (Dmcra)
RX630 Group 18. DMA Controller (DMACA) 18.2.3 DMA Transfer Count Register (DMCRA) Address(es): DMAC0.DMCRA 0008 2008h, DMAC1.DMCRA 0008 2048h DMAC2.DMCRA 0008 2088h, DMAC3.DMCRA 0008 20C8h  Normal transfer mode DMCRAH — — — — — — Value after reset: DMCRAL Value after reset: ...
Page 438: Dma Block Transfer Count Register (Dmcrb)
RX630 Group 18. DMA Controller (DMACA) (2) Repeat Transfer Mode (MD[1:0] Bits in DMACm.DMTMD = 01b) DMCRAH specifies the repeat size and DMCRAL functions as a 10-bit transfer counter. The number of transfer operations is one when the setting is 001h, 1023 when it is 3FFh, and 1024 when it is 000h. In repeat transfer mode, a value in the range of 000h to 3FFh (1 to 1024) can be set for DMCRAH and DMCRAL.
Page 439: Dma Transfer Mode Register (Dmtmd)
RX630 Group 18. DMA Controller (DMACA) 18.2.5 DMA Transfer Mode Register (DMTMD) Address(es): DMAC0.DMTMD 0008 2010h, DMAC1.DMTMD 0008 2050h DMAC2.DMTMD 0008 2090h, DMAC3.DMTMD 0008 20D0h MD[1:0] DTS[1:0] — — SZ[1:0] — — — — — — DCTG[1:0] Value after reset: Symbol Bit Name Description...
Page 440: Dma Interrupt Setting Register (Dmint)
RX630 Group 18. DMA Controller (DMACA) 18.2.6 DMA Interrupt Setting Register (DMINT) Address(es): DMAC0.DMINT 0008 2013h, DMAC1.DMINT 0008 2053h DMAC2.DMINT 0008 2093h, DMAC3.DMINT 0008 20D3h — — — DTIE ESIE RPTIE SARIE DARIE Value after reset: Symbol Bit Name Description DARIE Destination Address 0: Disables an interrupt request for an extended repeat area overflow on...
Page 441 RX630 Group 18. DMA Controller (DMACA) RPTIE Bit (Repeat Size End Interrupt Enable) When this bit is set to 1 in repeat transfer mode, the DTE bit in DMCNT is cleared to 0 after completion of a 1-repeat size data transfer. At the same time, the ESIF flag in DMSTS is set to 1 to indicate that the repeat size end interrupt request has been generated.
Page 442: Dma Address Mode Register (Dmamd)
RX630 Group 18. DMA Controller (DMACA) 18.2.7 DMA Address Mode Register (DMAMD) Address(es): DMAC0.DMAMD 0008 2014h, DMAC1.DMAMD 0008 2054h DMAC2.DMAMD 0008 2094h, DMAC3.DMAMD 0008 20D4h SM[1:0] — SARA[4:0] DM[1:0] — DARA[4:0] Value after reset: Symbol Bit Name Description b4 to b0 DARA[4:0] Destination Address Extended Specifies the extended repeat area on the destination address.
Page 443 RX630 Group 18. DMA Controller (DMACA) SARA[4:0] Bits (Source Address Extended Repeat Area) These bits specify the extended repeat area on the source address. The extended repeat area function is realized by updating the specified lower address bits with the remaining upper address bits fixed. The size of the extended repeat area can be any power of two between 2 bytes and 128 Mbytes.
Page 444 RX630 Group 18. DMA Controller (DMACA) Table 18.2 SARA[4:0] or DARA[4:0] Settings and Corresponding Repeat Areas SARA4 to SARA0 or DARA4 to DARA0 Extended Repeat Area 00000b Not specified 00001b 2 bytes specified as extended repeat area by the lower 1 bit of the address 00010b 4 bytes specified as extended repeat area by the lower 2 bits of the address 00011b...
Page 445: Dma Offset Register (Dmofr)
RX630 Group 18. DMA Controller (DMACA) 18.2.8 DMA Offset Register (DMOFR) Address(es): DMAC0.DMOFR 0008 2018h Value after reset: Value after reset: Description Setting Range b31 to b0 Specifies the offset when offset addition is selected 0000 0000h to 00FF FFFFh (0 bytes to (16 M – 1) bytes) as the address update mode for transfer source or FF00 0000h to FFFF FFFFh (–16 Mbytes to –1 byte) destination.
Page 446: Dma Software Start Register (Dmreq)
RX630 Group 18. DMA Controller (DMACA) 18.2.10 DMA Software Start Register (DMREQ) Address(es): DMAC0.DMREQ 0008 201Dh, DMAC1.DMREQ 0008 205Dh DMAC2.DMREQ 0008 209Dh, DMAC3.DMREQ 0008 20DDh SWRE — — — CLRS — — — Value after reset: Symbol Bit Name Description SWREQ DMA Software Start 0: DMA transfer is not requested.
Page 447: Dma Status Register (Dmsts)
RX630 Group 18. DMA Controller (DMACA) 18.2.11 DMA Status Register (DMSTS) Address(es): DMAC0.DMSTS 0008 201Eh, DMAC1.DMSTS 0008 205Eh DMAC2.DMSTS 0008 209Eh, DMAC3.DMSTS 0008 20DEh — — DTIF — — — ESIF Value after reset: Symbol Bit Name Description ESIF Transfer Escape End Interrupt 0: A transfer escape end interrupt has not been generated.
Page 448: Dma Activation Source Flag Control Register (Dmcsl)
RX630 Group 18. DMA Controller (DMACA) DTIF Flag (Transfer End Interrupt Flag) This flag indicates that the transfer end interrupt has been generated. [Setting conditions]  When the specified number of unit-transfers are completed in normal transfer mode (the value of DMCRAL becoming 0 on completion of transfer) ...
Page 449: Dmaca Module Activation Register (Dmast)
RX630 Group 18. DMA Controller (DMACA) 18.2.13 DMACA Module Activation Register (DMAST) Address(es): 0008 2200h — — — — — — — DMST Value after reset: Symbol Bit Name Description DMST DMAC Operation Enable 0: DMAC activation is disabled. 1: DMAC activation is enabled. b7 to b1 —...
Page 450: Operation
RX630 Group 18. DMA Controller (DMACA) 18.3 Operation 18.3.1 Transfer Mode (1) Normal Transfer Mode In normal transfer mode, one data is transferred by one transfer request. A maximum of 65535 can be set as the number of transfer operations using the DMCRAL of DMACm. When these bits are set to 0000h, no specific number of transfer operations is set;...
Page 451 RX630 Group 18. DMA Controller (DMACA) (2) Repeat Transfer Mode In repeat transfer mode, one data is transferred by one transfer request. A maximum of 1K data can be set as a total repeat transfer size using DMCRA of the DMACm. A maximum of 1K can be set as the number of repeat transfer operations using DMCRB of the DMACm;...
Page 452 RX630 Group 18. DMA Controller (DMACA) Transfer source data area Transfer destination data area (Specified as a repeat area) DMSAR DMDAR Data 1 Data 1 Data 2 Transfer Data 2 Data 3 Data 3 Data 4 Data 4 Data 1 Data 2 Data 3 Data 4...
Page 453 RX630 Group 18. DMA Controller (DMACA) (3) Block Transfer Mode In block transfer mode, a single block data is transferred by one transfer request. A maximum of 1K data can be set as a total block transfer size using DMCRA of the DMACm. A maximum of 1K can be set as the number of block transfer operations using DMCRB of the DMACm;...
Page 454: Extended Repeat Area Function
RX630 Group 18. DMA Controller (DMACA) 18.3.2 Extended Repeat Area Function The DMAC supports a function to specify the extended repeat areas on the transfer source and destination addresses. With the extended repeat areas set, the address registers repeatedly indicate the addresses of the specified extended repeat areas.
Page 455 RX630 Group 18. DMA Controller (DMACA) When an interrupt by an extended repeat area overflow is used in block transfer mode, the following should be taken into consideration. When a transfer is stopped by an interrupt by an extended repeat area overflow, the address register must be set so that the block size is a power of 2 or the block size boundary is aligned with the extended repeat area boundary.
Page 456: Address Update Function Using Offset
RX630 Group 18. DMA Controller (DMACA) 18.3.3 Address Update Function using Offset The source and destination addresses can be updated by fixing, increment, decrement, or offset addition. When the offset addition is selected, the offset specified by the DMA offset register (DMOFR of DMAC0) is added to the address every time the DMAC performs one data transfer.
Page 457 RX630 Group 18. DMA Controller (DMACA) (1) Basic Transfer Using Offset Addition Figure 18.7 shows an example of address updating using offset addition. Transfer Address B1 Data 1 Address A1 Data 1 Address B2 = address B1 + 4 Data 2 Data 3 Address B3 = address B2 + 4 Offset value...
Page 458 RX630 Group 18. DMA Controller (DMACA) First Data 1 Data 5 Data 9 Data 13 Data 1 Data 2 Data 3 Data 4 cycle Transfer Data 2 Data 6 Data 10 Data 14 Data 5 Data 6 Data 7 Data 8 Second cycle Data 3 Data 7...
Page 459 RX630 Group 18. DMA Controller (DMACA) Figure 18.9 shows a flowchart of the XY conversion. Start Set the address, repeat size, and number of repeat operations. Set repeat transfer mode. Enable repeat size end interrupts. Write 1 to the DTE bit in DMAC0.DMCNT. Receive a transfer request.
Page 460: Activation Sources
RX630 Group 18. DMA Controller (DMACA) 18.3.4 Activation Sources Software, the interrupt requests from the peripheral modules, and the external interrupt requests can be specified as the DMAC activation sources. Setting the DCTG[1:0] bits in DMTMD of DMACm selects the activation source. (1) DMAC Activation by Software Setting the DCTG[1:0] bits in DMTMD of DMACm to 00b enables the DMAC activation by software.
Page 461: Operation Timing
RX630 Group 18. DMA Controller (DMACA) 18.3.5 Operation Timing Figure 18.10 and Figure 18.11 show DMAC operation timing examples. System clock IRn in the ICU DMAC activation request DMAC access Data transfer Figure 18.10 DMAC Operation Timing Example (1) (DMA Activation by Interrupt from Peripheral Module/ External Interrupt Input Pin, Normal Transfer Mode, Repeat Transfer Mode) System clock IRn in the ICU...
Page 462: Dmac Execution Cycles
RX630 Group 18. DMA Controller (DMACA) 18.3.6 DMAC Execution Cycles Table 18.7 lists execution cycles in one DMAC data transfer operation. Table 18.7 DMAC Execution Cycles Transfer Mode Data Transfer (Read) Data Transfer (Write) Normal Cr+1 Repeat Cr+1 Block* P × Cr P ×...
Page 463: Activating The Dmac
RX630 Group 18. DMA Controller (DMACA) 18.3.7 Activating the DMAC Figure 18.12 shows the register setting procedure. <For activation other than by software> Start of initial settings Clear the interrupt enable bit (ICU.IERn.IENj) as an activation source to 0, then perform the settings below. <To use peripheral function Set the peripheral module as a DMACm request Set the control register for the peripheral function without...
Page 464: Starting Dma Transfer
RX630 Group 18. DMA Controller (DMACA) 18.3.8 Starting DMA Transfer Setting the DTE bit in DMCNT of DMACm to 1 (DMA transfer enabled) and setting the DMST bit in DMAST to 1 (DMAC start enabled) enable DMA transfer of channel m (m = 0 to 3). Another activation request cannot be accepted during the transfer of other DMAC channel or DTC.
Page 465: Channel Priority
RX630 Group 18. DMA Controller (DMACA) (6) DMA Active Flag (DMACm.DMSTS.ACT) The ACT bit in DMSTS of DMACm indicates whether the DMACm is in the idle or active state. This flag is set to 1 when the DMAC starts data transfer, and is cleared to 0 when data transfer in response to one transfer request is completed.
Page 466: Ending Dma Transfer
RX630 Group 18. DMA Controller (DMACA) 18.4 Ending DMA Transfer The operation for ending DMA transfer depends on the transfer end conditions. When DMA transfer ends, the DTE bit in DMCNT and the ACT flag in DMSTS of DMACm are changed from 1 to 0, indicating that DMA transfer has ended. 18.4.1 Transfer End by Completion of Specified Total Number of Transfer Operations (1) In Normal Transfer Mode (DMACm.DMTMD.MD[1:0] = 00b)
Page 467: Interrupts
RX630 Group 18. DMA Controller (DMACA) 18.5 Interrupts Each DMAC channel can output an interrupt request to the CPU or the DTC after transfer in response to one request is completed. When the transfer destination is the external bus or the on-chip peripheral bus, an interrupt request is generated upon completion of data write to the write buffer not to the actual transfer destination.
Page 468 RX630 Group 18. DMA Controller (DMACA) Specifically, the different procedures are used for canceling an interrupt to restart DMA transfer in the following two cases: (1) discontinuing or terminating DMA transfer and (2) continuing DMA transfer. (1) When Discontinuing or Terminating DMA Transfer Write 0 to the DTIF bit in DMSTS of DMACm to clear a transfer end interrupt, and to the ESIF bit in DMSTS of DMACm to clear a repeat size interrupt and an extended repeat area overflow interrupt.
Page 469: Low-Power Consumption Function
RX630 Group 18. DMA Controller (DMACA) 18.6 Low-Power Consumption Function Before transition to the module-stop state, all-module clock stop mode, software standby mode, or deep software standby mode, clear the DMST bit in DMAST to 0 (the DMAC suspended), and then perform the following. (1) Module-Stop Function Writing 1 to the MSTPA28 bit (transition to the module-stop state) in MSTPCRA enables the module-stop function of the DMAC.
Page 470: Usage Notes
RX630 Group 18. DMA Controller (DMACA) 18.7 Usage Notes 18.7.1 DMA Transfer to External Devices In DMA transfer to an external device, the ACT bit in DMSTS of DMACm may be cleared to 0 (DMAC transfer suspended) during the period from the beginning of the final data write to the end of the external bus access. 18.7.2 DMA Transfer to Peripheral Modules In DMA transfer to a peripheral module, the ACT bit in DMSTS of DMACm may be cleared to 0 (DMAC transfer...
Page 471: Data Transfer Controller (Dtca)
RX630 Group 19. Data Transfer Controller (DTCa) Data Transfer Controller (DTCa) The RX630 Group incorporates a data transfer controller (DTC). The DTC is activated by an interrupt request to control data transfer. 19.1 Overview Table 19.1 lists the specifications of the DTC, and Figure 19.1 shows a block diagram of the DTC. Table 19.1 DTC Specifications Item...
Page 472 RX630 Group 19. Data Transfer Controller (DTCa) Register Vector number control Interrupt controller Startup Start request control DTC response Bus interface DTCCR DTCVBR response DTCADMOD control DTCST DTCSTS Internal peripheral bus 1 Internal main bus 2 Internal peripheral bus 1 External bus Internal Memory bus 2...
Page 473: Register Descriptions
RX630 Group 19. Data Transfer Controller (DTCa) 19.2 Register Descriptions Registers MRA, MRB, SAR, DAR, CRA, and CRB are DTC internal registers, which cannot be directly accessed from the CPU. Values to be set in the DTC internal registers are placed in the RAM area as transfer information data. When an activation request is generated, the DTC reads the transfer information data from the RAM area and set them in the internal registers.
Page 474: Dtc Mode Register B (Mrb)
RX630 Group 19. Data Transfer Controller (DTCa) 19.2.2 DTC Mode Register B (MRB) Address(es): (inaccessible directly from the CPU) CHNE CHNS DISEL DM[1:0] — — Value after reset: x: Undefined Symbol Bit Name Description b1, b0 — Reserved These bits are read as undefined. The write value should be 0. —...
Page 475: Dtc Transfer Source Register (Sar)
RX630 Group 19. Data Transfer Controller (DTCa) 19.2.3 DTC Transfer Source Register (SAR) Address(es): (inaccessible directly from the CPU) Value after reset: Value after reset: x: Undefined In full-address mode, 32 bits are valid. In short-address mode, lower 24 bits are valid and upper 8 bits (b31 to b24) are ignored. The address of this register is extended by the value specified by b23.
Page 476: Dtc Transfer Count Register A (Cra)
RX630 Group 19. Data Transfer Controller (DTCa) 19.2.5 DTC Transfer Count Register A (CRA) Address(es): (inaccessible directly from the CPU)  Normal transfer mode Value after reset:  Repeat transfer mode/block transfer mode CRAH CRAL Value after reset: x: Undefined Note: •...
Page 477: Dtc Transfer Count Register B (Crb)
RX630 Group 19. Data Transfer Controller (DTCa) 19.2.6 DTC Transfer Count Register B (CRB) Address(es): (inaccessible directly from the CPU) Value after reset: x: Undefined CRB is used to set the block transfer count for block transfer mode. The transfer count is 1, 65535, and 65536 when the set value is 0001h, FFFFh, and 0000h, respectively. The CRB value is decremented (–1) when the final data of a single block size is transferred.
Page 478: Dtc Vector Base Register (Dtcvbr)
RX630 Group 19. Data Transfer Controller (DTCa) 19.2.8 DTC Vector Base Register (DTCVBR) Address(es): 0008 2404h Value after reset: Value after reset: Bit Name Description b11 to b0 DTC vector address (the lower 12 bits) These bits are read as 0. The write value should be 0. b31 to b12 DTC vector base address (the upper 20 bits) The upper 4 bits (b31 to b28) are ignored, and the address of...
Page 479: Dtc Module Start Register (Dtcst)
RX630 Group 19. Data Transfer Controller (DTCa) 19.2.10 DTC Module Start Register (DTCST) Address(es): 0008 240Ch — — — — — — — DTCST Value after reset: Symbol Bit Name Description DTCST DTC Module Start 0: DTC module-stop 1: DTC module-stop b7 to b1 —...
Page 480: Dtc Status Register (Dtcsts)
RX630 Group 19. Data Transfer Controller (DTCa) 19.2.11 DTC Status Register (DTCSTS) Address(es): 0008 240Eh — — — — — — — VECN[7:0] Value after reset: Symbol Bit Name Description b7 to b0 VECN[7:0] DTC-Activating Vector These bits indicate the vector number for the activating source Number Monitoring when DTC transfer is in progress.
Page 481: Sources Of Activation
RX630 Group 19. Data Transfer Controller (DTCa) 19.3 Sources of Activation The DTC is activated by an interrupt request. Setting the DTCERn.DTCE bit (where n is the interrupt vector number of the given interrupt) of the ICU to 1 selects the corresponding interrupt as an activation source for the DTC. For the correspondence between the DTC startup sources and the vector addresses, see Table 15.3, Interrupt Vector Table in section 15, Interrupt controller (ICUb) .
Page 482 RX630 Group 19. Data Transfer Controller (DTCa) Upper: DTCVBR DTC vector table Lower: Vector number  4 Transfer data (1) DTC vector address Transfer data (1) start address Transfer data (2) start address Transfer data (2) Transfer data (n) start address 4 bytes Transfer data (n) 4 bytes...
Page 483: Operation
RX630 Group 19. Data Transfer Controller (DTCa) 19.4 Operation The DTC transfers data in accordance with the transfer data. Storage of the transfer data in the RAM area is required before DTC operation. When the DTC is activated, it reads the DTC vector corresponding to the vector number. Then the DTC reads transfer data from the transfer data store address pointed by the DTC vector, transfers data, and then writes back the transfer data after the data transfer.
Page 484 RX630 Group 19. Data Transfer Controller (DTCa) START Match and RRS bit = 1 Compare vector numbers. Match? Mismatch RRS bit = 0 Read DTC vector Next transfer Read data to be transferred Update transfer data start address CHNE bit = 1? CHNS = 0 MD[1:0] = 01b? (Repeat transfer?)
Page 485: Transfer Data Read Skip Function
RX630 Group 19. Data Transfer Controller (DTCa) Table 19.3 Chain Transfer Conditions First Transfer Second Transfer* CHNE CHNS DISEL Transfer CHNE CHNS DISEL Transfer Counter* Counter* DTC Transfer Other than (1 → 0) — — — — — Ends after the first transfer (1 →...
Page 486: Transfer Data Write-Back Skip Function
RX630 Group 19. Data Transfer Controller (DTCa) 19.4.2 Transfer Data Write-Back Skip Function When the SM[1:0] bits in MRA or the DM[1:0] bits in MRB are set to “address fixed”, a part of transfer data is not written back. This function is performed independently of the setting of short-address mode or full-address mode. Table 19.4 lists transfer data write-back skip conditions and applicable registers.
Page 487: Repeat Transfer Mode
RX630 Group 19. Data Transfer Controller (DTCa) Transfer source data area Transfer destination data area Data 1 Data 1 Transfer Data 2 Data 2 Data 3 Data 3 Data 4 Data 4 Data 5 Data 5 Data 6 Data 6 Figure 19.5 Memory Map of Normal Transfer Mode 19.4.4...
Page 488 RX630 Group 19. Data Transfer Controller (DTCa) Transfer source data area Transfer destination data area (set to repeat area) Data 1 Data 1 Data 2 Transfer Data 2 Data 3 Data 3 Data 4 Data 4 Data 1 Data 2 Data 3 Data 4 Figure 19.6...
Page 489: Block Transfer Mode
RX630 Group 19. Data Transfer Controller (DTCa) 19.4.5 Block Transfer Mode This mode allows single-block data transfer on a single startup source. Specify either transfer source or transfer destination for the block area by the DTS bit in MRB. The block size can be set to 1 to 256 bytes (or 1 to 256 words or 1 to 256 longwords).
Page 490: Chain Transfer
RX630 Group 19. Data Transfer Controller (DTCa) 19.4.6 Chain Transfer Setting the CHNE bit in MRB to 1 allows chain transfer to be performed continuously on a single startup source. If the CHNE bit in MRB is set to 1, and the CHNS bit in MRB is set to 0, an interrupt request to the CPU is not generated by completion of specified number of rounds of transfer or by setting the DISEL bit in MRB to 1 (an interrupt request to the CPU is generated each time DTC data transfer is performed), and data transfer has no effect on the interrupt status flag that has started up the transfer.
Page 491: Operation Timing
RX630 Group 19. Data Transfer Controller (DTCa) 19.4.7 Operation Timing Figure 19.9 to Figure 19.13 show examples of DTC operation timing. System clock IRn in the ICU DTC startup request DTC access Transfer Data Vector read Transfer data read transfer data write Figure 19.9 Example (1) of DTC Operation Timing...
Page 492 RX630 Group 19. Data Transfer Controller (DTCa) System clock IRn in the ICU DTC startup request DTC access Vector read Data Transfer data Data Transfer data Transfer data Transfer data transfer transfer read write read write Figure 19.11 Example (3) of DTC Operation Timing (Short-Address Mode, Chain Transfer) System clock IRn in the ICU DTC startup request...
Page 493 RX630 Group 19. Data Transfer Controller (DTCa) System clock IRn in the ICU DTC startup request Read skip enable DTC access Data Transfer Vector read Transfer Transfer Data transfer data write data read transfer data write n = DTC vector number (interrupt vector number) Note: •...
Page 494: Execution Cycles Of The Dtc
RX630 Group 19. Data Transfer Controller (DTCa) 19.4.8 Execution Cycles of the DTC Table 19.8 lists the execution cycles of single data transfer of the DTC. For the order of the execution states, refer to section 19.4.7, Operation Timing . Table 19.8 Execution Cycles of the DTC Data Transfer...
Page 495: Dtc Setting Procedure
RX630 Group 19. Data Transfer Controller (DTCa) 19.5 DTC Setting Procedure Before using the DTC, set the DTC vector base register (DTCVBR). Figure 19.14 shows the procedure to set the DTC. Set the ICU.IERm.IENj bit corresponding to the activation source START interrupt to 0 and provide the following settings.
Page 496: Examples Of Dtc Usage
RX630 Group 19. Data Transfer Controller (DTCa) 19.6 Examples of DTC Usage 19.6.1 Normal Transfer As an example of DTC usage, its employment in the transfer of 128 bytes of data by an SCI is described below. (1) Transfer Data Set In the MRA register, select a fixed source address (MRA.SM[1:0] = 00b), normal transfer mode (MRA.MD[1:0] = 00b), and byte-sized transfer (MRA.SZ[1:0] = 00b).
Page 497 RX630 Group 19. Data Transfer Controller (DTCa) (1) First Transfer Data Set Settings are made for transfer to the PPGm.NDRH and PPGm.NDRL registers. In the MRA register, make the settings to select incrementation of the source address (MRA.SM[1:0] = 10b), transfer in repeated-transfer mode (MRA.MD[1:0] = 01b), and word-sized transfer (MRA.SZ[1:0] = 01b).
Page 498: Chain Transfer When Counter = 0
RX630 Group 19. Data Transfer Controller (DTCa) 19.6.3 Chain Transfer when Counter = 0 The second data transfer is performed only when the counter = 0. Repeat transfer of a transfer count of 256 or more is enabled by the re-setting for the first data transfer. The following shows an example of configuring a 128-Kbyte input buffer, where the input buffer is set so that its lower address starts with 0000h.
Page 499: Interrupt Source
RX630 Group 19. Data Transfer Controller (DTCa) Input circuit Transfer data allocated in the on-chip memory space Input buffer First data transfer Transfer data Chain transfer (counter = 0) Second data transfer Transfer data Upper 8 bits of DAR Figure 19.15 Chain Transfer when Counter = 0 19.7 Interrupt Source...
Page 500: Low-Power Consumption Function
RX630 Group 19. Data Transfer Controller (DTCa) 19.8 Low-Power Consumption Function Before transition to the module-stop state, all-module clock stop mode, software standby mode, or deep software standby mode, clear the DTCST bit in DTCST to 0 (the DTC suspended), and then perform the following. (1) Module-Stop Function Writing 1 to the MSTPA28 bit (transition to the module-stop state) in MSTPCRA enables the module-stop function of the DTC.
Page 501: Setting The Dtc Activation Enable Register (Icu.dtcern) Of The Interrupt Controller
RX630 Group 19. Data Transfer Controller (DTCa) Allocation of transfer data to Allocation of transfer data to little-endian area big-endian area (Short-address mode) (Short-address mode) Lower address Lower address Address Address 4(n+1) 4(n+1) 4(n+2) 4(n+2) 4 bytes 4 bytes Allocation of transfer data to Allocation of transfer data to little-endian area big-endian area...
Page 502: I/O Ports
RX630 Group 20. I/O Ports I/O Ports 20.1 Overview The I/O ports of the RX630 Group function as a programmable I/O port, an I/O pin of a peripheral module, an input pin for an interrupt, or a bus control pin. Each pin is also configurable as an I/O pin of a peripheral module or an input pin for an interrupt.
Page 503 RX630 Group 20. I/O Ports Table 20.2 Port Functions Open Drain Driving Abilify Port Input Pull-up Output Switching 5-V Tolerant ○ ○ ○ PORT0 P00 to P02 — ○ ○ P03, P05 Fixed to high driving — ability output ○ ○...
Page 504 RX630 Group 20. I/O Ports Table 20.2 Port Functions Open Drain Driving Abilify Port Input Pull-up Output Switching 5-V Tolerant ○ ○ PORTJ PJ3, PJ5 Fixed to high driving — ability output ○ ○ PORTK PK0 to PK7 Fixed to high driving —...
Page 505: I/O Port Configuration
RX630 Group 20. I/O Ports 20.2 I/O Port Configuration Port 0: P00 to P02* Port 4: P40 to P47 1: ON 0: OFF Enable peripheral module output Peripheral module output signal Input signal of peripheral module/interrupt Reading the port ISEL bit ASEL bit Analog input Port 0: P03*...
Page 506 RX630 Group 20. I/O Ports Port 0: P07 1 to 1 to Port 1: P10* , P11* , P12 to P17 Port 2: P20, P21, P22* , P23* Port 3: P30 to P32, P33* , P34, P36, P37 Port 7: P70* 1 to 1 to Port 8: P80 to P83*...
Page 507 RX630 Group 20. I/O Ports Port 5: P53* 1:ON 0: OFF Enable external bus output BCLK signal Enable external bus pin Reading the port Port 2: P24* , P25* , P26, P27 1 to Port 5: P50 to P52* , P54, P55, P56* , P57* Port 6: P60 to P67* Port 7: P71 to P77*...
Page 508 RX630 Group 20. I/O Ports Port 9: P90 to P93* Port D: PD0 to PD2, PD3 to PD7* Port E: PE0 to PE5, PF6* , PE7* 1: ON 0: OFF Enable external bus output Peripheral module output enable External bus output data Peripheral module output signal Enable external bus pin Input signal of peripheral module/interrupt/external bus...
Page 509: Register Descriptions
RX630 Group 20. I/O Ports 20.3 Register Descriptions 20.3.1 Port Direction Register (PDR) Address(es): PORT0.PDR 0008 C000h, PORT1.PDR 0008 C001h, PORT2.PDR 0008 C002h, PORT3.PDR 0008 C003h, PORT4.PDR 0008 C004h, PORT5.PDR 0008 C005h, PORT6.PDR 0008 C006h, PORT7.PDR 0008 C007h, PORT8.PDR 0008 C008h, PORT9.PDR 0008 C009h, PORTA.PDR 0008 C00Ah, PORTB.PDR 0008 C00Bh, PORTC.PDR 0008 C00Ch, PORTD.PDR 0008 C00Dh, PORTE.PDR 0008 C00Eh, PORTF.PDR 0008 C00Fh, PORTG.PDR 0008 C010h, PORTH.PDR 0008 C011h, PORTJ.PDR 0008 C012h, PORTK.PDR 0008 C013h, PORTL.PDR 0008 C014h...
Page 510: Port Output Data Register (Podr)
RX630 Group 20. I/O Ports 20.3.2 Port Output Data Register (PODR) Address(es): PORT0.PODR 0008 C020h, PORT1.PODR 0008 C021h, PORT2.PODR 0008 C022h, PORT3.PODR 0008 C023h, PORT4.PODR 0008 C024h, PORT5.PODR 0008 C025h, PORT6.PODR 0008 C026h, PORT7.PODR 0008 C027h, PORT8.PODR 0008 C028h, PORT9.PODR 0008 C029h, PORTA.PODR 0008 C02Ah, PORTB.PODR 0008 C02Bh, PORTC.PODR 0008 C02Ch, PORTD.PODR 0008 C02Dh, PORTE.PODR 0008 C02Eh, PORTF.PODR 0008 C02Fh, PORTG.PODR 0008 C030h, PORTH.PODR 0008 C031h, PORTJ.PODR 0008 C032h, PORTK.PODR 0008 C033h, PORTL.PODR 0008 C034h...
Page 511: Port Input Data Register (Pidr)
RX630 Group 20. I/O Ports 20.3.3 Port Input Data Register (PIDR) Address(es): PORT0.PIDR 0008 C040h, PORT1.PIDR 0008 C041h, PORT2.PIDR 0008 C042h, PORT3.PIDR 0008 C043h, PORT4.PIDR 0008 C044h, PORT5.PIDR 0008 C045h, PORT6.PIDR 0008 C046h, PORT7.PIDR 0008 C047h, PORT8.PIDR 0008 C048h, PORT9.PIDR 0008 C049h, PORTA.PIDR 0008 C04Ah, PORTB.PIDR 0008 C04Bh, PORTC.PIDR 0008 C04Ch, PORTD.PIDR 0008 C04Dh, PORTE.PIDR 0008 C04Eh, PORTF.PIDR 0008 C04Fh, PORTG.PIDR 0008 C050h, PORTH.PIDR 0008 C051h, PORTJ.PIDR 0008 C052h, PORTK.PIDR 0008 C053h, PORTL.PIDR 0008 C054h...
Page 512: Port Mode Register (Pmr)
RX630 Group 20. I/O Ports 20.3.4 Port Mode Register (PMR) Address(es): PORT0.PMR 0008 C060h, PORT1.PMR 0008 C061h, PORT2.PMR 0008 C062h, PORT3.PMR 0008 C063h, PORT4.PMR 0008 C064h, PORT5.PMR 0008 C065h, PORT6.PMR 0008 C066h, PORT7.PMR 0008 C067h, PORT8.PMR 0008 C068h, PORT9.PMR 0008 C069h, PORTA.PMR 0008 C06Ah, PORTB.PMR 0008 C06Bh, PORTC.PMR 0008 C06Ch, PORTD.PMR 0008 C06Dh, PORTE.PMR 0008 C06Eh, PORTF.PMR 0008 C06Fh, PORTG.PMR 0008 C070h, PORTH.PMR 0008 C071h, PORTJ.PMR 0008 C072h, PORTK.PMR 0008 C073h, PORTL.PMR 0008 C074h...
Page 513: Open Drain Control Register 0 (Odr0)
RX630 Group 20. I/O Ports 20.3.5 Open Drain Control Register 0 (ODR0) Address(es): PORT0.ODR0 0008 C080h, PORT1.ODR0 0008 C082h, PORT2.ODR0 0008 C084h, PORT3.ODR0 0008 C086h, PORT4.ODR0 0008 C088h, PORT5.ODR0 0008 C08Ah, PORT6.ODR0 0008 C08Ch, PORT7.ODR0 0008 C08Eh, PORT8.ODR0 0008 C090h, PORT9.ODR0 0008 C092h, PORTA.ODR0 0008 C094h, PORTB.ODR0 0008 C096h, PORTC.ODR0 0008 C098h, PORTD.ODR0 0008 C09Ah, PORTE.ODR0 0008 C09Ch, PORTF.ODR0 0008 C09Eh, PORTG.ODR0 0008 C0A0h, PORTJ.ODR0 0008 C0A4h, PORTK.ODR0 0008 C0A6h, PORTL.ODR0 0008 C0A8h...
Page 514: Open Drain Control Register 1 (Odr1)
RX630 Group 20. I/O Ports 20.3.6 Open Drain Control Register 1 (ODR1) Address(es): PORT0.ODR1 0008 C081h, PORT1.ODR1 0008 C083h, PORT2.ODR1 0008 C085h, PORT3.ODR1 0008 C087h, PORT4.ODR1 0008 C089h, PORT5.ODR1 0008 C08Bh, PORT6.ODR1 0008 C08Dh, PORT7.ODR1 0008 C08Fh, PORT8.ODR1 0008 C091h, PORT9.ODR1 0008 C093h, PORTA.ODR1 0008 C095h, PORTB.ODR1 0008 C097h, PORTC.ODR1 0008 C099h, PORTD.ODR1 0008 C09Bh, PORTE.ODR1 0008 C09Dh, PORTF.ODR1 0008 C09Fh, PORTG.ODR1 0008 C0A1h, PORTH.ODR1 0008 C0A3h, PORTJ.ODR1 0008 C0A5h, PORTK.ODR1 0008 C0A7h, PORTL.ODR1 0008 C0A9h...
Page 515: Pull-Up Control Register (Pcr)
RX630 Group 20. I/O Ports 20.3.7 Pull-Up Control Register (PCR) Address(es): PORT0.PCR 0008 C0C0h, PORT1.PCR 0008 C0C1h, PORT2.PCR 0008 C0C2h, PORT3.PCR 0008 C0C3h, PORT4.PCR 0008 C0C4h, PORT5.PCR 0008 C0C5h, PORT6.PCR 0008 C0C6h, PORT7.PCR 0008 C0C7h, PORT8.PCR 0008 C0C8h, PORT9.PCR 0008 C0C9h, PORTA.PCR 0008 C0CAh, PORTB.PCR 0008 C0CBh, PORTC.PCR 0008 C0CCh, PORTD.PCR 0008 C0CDh, PORTE.PCR 0008 C0CEh, PORTF.PCR 0008 C0CFh, PORTG.PCR 0008 C0D0h, PORTH.PCR 0008 C0D1h, PORTJ.PCR 0008 C0D2h, PORTK.PCR 0008 C0D3h, PORTL.PCR 0008 C0D4h...
Page 516: Driving Ability Control Register (Dscr)
RX630 Group 20. I/O Ports 20.3.8 Driving Ability Control Register (DSCR) Address(es): PORT0.DSCR 0008 C0E0h, PORT2.DSCR 0008 C0E2h, PORT5.DSCR 0008 C0E5h, PORT6.DSCR 0008 C0E6h, PORT7.DSCR 0008 C0E7h, PORT9.DSCR 0008 C0E9h, PORTA.DSCR 0008 C0EAh, PORTB.DSCR 0008 C0EBh, PORTC.DSCR 0008 C0ECh, PORTD.DSCR 0008 C0EDh, PORTE.DSCR 0008 C0EEh, PORTG.DSCR 0008 C0F0h Value after reset: Symbol Bit Name...
Page 517: Handling Of Unused Pins
RX630 Group 20. I/O Ports 20.4 Handling of Unused Pins Table 20.3 lists handling of unused pins. Table 20.3 Handling of Unused Pins Handling Description EMLE Connect to VSS through resistor (pull-down) (Used as a mode pin) RES# Connect to VCC through resistor (pull-up) USB0_DP Keep the pin open USB0_DM...
Page 518: Multi-Function Pin Controller (Mpc)
RX630 Group 21. Multi-Function Pin Controller (MPC) Multi-Function Pin Controller (MPC) 21.1 Overview The multi-function pin controller (MPC) selects and assigns input/output of peripheral functions and interrupt input signals from multiple ports. The MPC also assigns the port of external bus related signals. Table 21.1 lists the functions assigned to each multiplexed pin.
Page 519 RX630 Group 21. Multi-Function Pin Controller (MPC) Table 21.1 Functions Assigned to Each Multiplexed Pin (1/14) Package 177-pin, 145-pin, Module/Function Channel Pin Functions Allocation Port 176-pin 144-pin 100-Pin 80-Pin ○ ○ ○ ○ Interrupt NMI (input) ○ ○ ○ ○ Interrupt IRQ0 IRQ0-DS (input)
Page 520 RX630 Group 21. Multi-Function Pin Controller (MPC) Table 21.1 Functions Assigned to Each Multiplexed Pin (2/14) Package 177-pin, 145-pin, Module/Function Channel Pin Functions Allocation Port 176-pin 144-pin 100-Pin 80-Pin ○ ○ ○ ○ Interrupt IRQ12 IRQ12-DS (input) ○ ○ ○ ○...
Page 521 RX630 Group 21. Multi-Function Pin Controller (MPC) Table 21.1 Functions Assigned to Each Multiplexed Pin (3/14) Package 177-pin, 145-pin, Module/Function Channel Pin Functions Allocation Port 176-pin 144-pin 100-Pin 80-Pin ○ ○ ○ ○ Multi-function timer MTU3 MTIOC3A (input/output) unit 2 ○...
Page 522 RX630 Group 21. Multi-Function Pin Controller (MPC) Table 21.1 Functions Assigned to Each Multiplexed Pin (4/14) Package 177-pin, 145-pin, Module/Function Channel Pin Functions Allocation Port 176-pin 144-pin 100-Pin 80-Pin ○ Multi-function timer MTU5 MTIC5U (input) × × × unit 2 ○...
Page 523 RX630 Group 21. Multi-Function Pin Controller (MPC) Table 21.1 Functions Assigned to Each Multiplexed Pin (5/14) Package 177-pin, 145-pin, Module/Function Channel Pin Functions Allocation Port 176-pin 144-pin 100-Pin 80-Pin ○ ○ 16-bit timer pulse TPU0 TIOCA0 (input/output) × × unit ○...
Page 524 RX630 Group 21. Multi-Function Pin Controller (MPC) Table 21.1 Functions Assigned to Each Multiplexed Pin (6/14) Package 177-pin, 145-pin, Module/Function Channel Pin Functions Allocation Port 176-pin 144-pin 100-Pin 80-Pin ○ ○ ○ ○ 16-bit timer pulse TCLKA (input) unit (unit 0) ○...
Page 525 RX630 Group 21. Multi-Function Pin Controller (MPC) Table 21.1 Functions Assigned to Each Multiplexed Pin (7/14) Package 177-pin, 145-pin, Module/Function Channel Pin Functions Allocation Port 176-pin 144-pin 100-Pin 80-Pin ○ ○ ○ ○ Programmable pulse PPG0 PO13 (output) generator ○ ○...
Page 526 RX630 Group 21. Multi-Function Pin Controller (MPC) Table 21.1 Functions Assigned to Each Multiplexed Pin (8/14) Package 177-pin, 145-pin, Module/Function Channel Pin Functions Allocation Port 176-pin 144-pin 100-Pin 80-Pin ○ ○ ○ 8-bit timer TMR0 TMO0 (output) × ○ ○ ○...
Page 527 RX630 Group 21. Multi-Function Pin Controller (MPC) Table 21.1 Functions Assigned to Each Multiplexed Pin (9/14) Package 177-pin, 145-pin, Module/Function Channel Pin Functions Allocation Port 176-pin 144-pin 100-Pin 80-Pin ○ ○ ○ ○ Serial SCI1 RXD1 (input)/ communications SMISO1 (input/output)/ ○...
Page 528 RX630 Group 21. Multi-Function Pin Controller (MPC) Table 21.1 Functions Assigned to Each Multiplexed Pin (10/14) Package 177-pin, 145-pin, Module/Function Channel Pin Functions Allocation Port 176-pin 144-pin 100-Pin 80-Pin ○ ○ ○ ○ Serial SCI5 RXD5 (input)/ communications SMISO5 (input/output)/ ○...
Page 529 RX630 Group 21. Multi-Function Pin Controller (MPC) Table 21.1 Functions Assigned to Each Multiplexed Pin (11/14) Package 177-pin, 145-pin, Module/Function Channel Pin Functions Allocation Port 176-pin 144-pin 100-Pin 80-Pin ○ ○ ○ ○ Serial SCI9 RXD9 (input)/ communications SMISO9 (input/output)/ ○...
Page 530 RX630 Group 21. Multi-Function Pin Controller (MPC) Table 21.1 Functions Assigned to Each Multiplexed Pin (12/14) Package 177-pin, 145-pin, Module/Function Channel Pin Functions Allocation Port 176-pin 144-pin 100-Pin 80-Pin ○ ○ ○ ○ USB 2.0 Function Module USB0_DPUPE (output) ○ ○...
Page 531 RX630 Group 21. Multi-Function Pin Controller (MPC) Table 21.1 Functions Assigned to Each Multiplexed Pin (13/14) Package 177-pin, 145-pin, Module/Function Channel Pin Functions Allocation Port 176-pin 144-pin 100-Pin 80-Pin ○ ○ ○ ○ Serial peripheral RSPI1 RSPCKB (input/output) interface ○ ○...
Page 532 RX630 Group 21. Multi-Function Pin Controller (MPC) Table 21.1 Functions Assigned to Each Multiplexed Pin (14/14) Package 177-pin, 145-pin, Module/Function Channel Pin Functions Allocation Port 176-pin 144-pin 100-Pin 80-Pin ○ ○ ○ 12-bit A/D converter AN011 (input)* × ○ ○ ○...
Page 533: Register Descriptions
RX630 Group 21. Multi-Function Pin Controller (MPC) 21.2 Register Descriptions The registers and bits of unsupported pins, depending on the package, are reserved. The write value to the reserved bits is the value after a reset. 21.2.1 Write-Protect Register (PWPR) Address(es): 0008 C11Fh B0WI PFSWE —...
Page 534: P0N Pin Function Control Register (P0Npfs) (N = 0 To 3, 5, 7)
RX630 Group 21. Multi-Function Pin Controller (MPC) 21.2.2 P0n Pin Function Control Register (P0nPFS) (n = 0 to 3, 5, 7) Address(es): P00PFS 0008 C140h, P01PFS 0008 C141h, P02PFS 0008 C142h, P03PFS 0008 C143h, P05PFS 0008 C145h, P07PFS 0008 C147h ASEL ISEL —...
Page 535: P1N Pin Function Control Registers (P1Npfs) (N = 0 To 7)
RX630 Group 21. Multi-Function Pin Controller (MPC) 21.2.3 P1n Pin Function Control Registers (P1nPFS) (n = 0 to 7) Address(es): P10PFS 0008 C148h, P11PFS 0008 C149h, P12PFS 0008 C14Ah, P13PFS 0008 C14Bh P14PFS 0008 C14Ch, P15PFS 0008 C14Dh, P16PFS 0008 C14Eh, P17PFS 0008 C14Fh —...
Page 536 RX630 Group 21. Multi-Function Pin Controller (MPC) Table 21.5 Register Settings for Input/Output Pin Function in 145-/100-Pin TFLGA, 144-/100-Pin LQFP PSEL[4:0] Settings 00000b Hi-Z (initial value) 00001b — MTIOC0B MTIOC3A MTIOC0B MTIOC3C MTIOC3A 00010b — — MTCLKA MTCLKB MTIOC3D MTIOC3B 00011b —...
Page 537: P2N Pin Function Control Registers (P2Npfs) (N = 0 To 7)
RX630 Group 21. Multi-Function Pin Controller (MPC) 21.2.4 P2n Pin Function Control Registers (P2nPFS) (n = 0 to 7) Address(es): P20PFS 0008 C150h, P21PFS 0008 C151h, P22PFS 0008 C152h, P23PFS 0008 C153h P24PFS 0008 C154h, P25PFS 0008 C155h, P26PFS 0008 C156h, P27PFS 0008 C157h —...
Page 538 RX630 Group 21. Multi-Function Pin Controller (MPC) Table 21.8 Register Settings for Input/Output Pin Function in 100-Pin TFLGA, 100-Pin LQFP PSEL[4:0] Settings 00000b Hi-Z (initial value) 00001b MTIOC1A MTIOC1B MTIOC3B MTIOC3D MTIOC4A MTIOC4C MTIOC2A MTIOC2B 00010b — — MTCLKC MTCLKD MTCLKA MTCLKB —...
Page 539: P3N Pin Function Control Registers (P3Npfs) (N = 0 To 4)
RX630 Group 21. Multi-Function Pin Controller (MPC) 21.2.5 P3n Pin Function Control Registers (P3nPFS) (n = 0 to 4) Address(es): P30PFS 0008 C158h, P31PFS 0008 C159h, P32PFS 0008 C15Ah, P33PFS 0008 C15Bh, P34PFS 0008 C15Ch — ISEL — PSEL[4:0] Value after reset: Symbol Bit Name Description...
Page 540: P4N Pin Function Control Registers (P4Npfs) (N = 0 To 7)
RX630 Group 21. Multi-Function Pin Controller (MPC) Table 21.11 Register Settings for Input/Output Pin Function in 80-Pin LQFP PSEL[4:0] Settings 00000b (initial value) Hi-Z 00001b MTIOC4B MTIOC4D MTIOC0C MTIOC0A 00011b — — TIOCC0 — 00101b TMRI3 TMCI2 TMO3 TMCI3 00110b PO10 PO12 00111b...
Page 541: P5N Pin Function Control Registers (P5Npfs) (N = 0 To 2, 4 To 6)
RX630 Group 21. Multi-Function Pin Controller (MPC) 21.2.7 P5n Pin Function Control Registers (P5nPFS) (n = 0 to 2, 4 to 6) Address(es): P50PFS 0008 C168h, P51PFS 0008 C169h, P52PFS 0008 C16Ah P54PFS 0008 C16Ch, P55PFS 0008 C16Dh, P56PFS 0008 C16Eh —...
Page 542: P6N Pin Function Control Registers (P6Npfs) (N = 0, 1, 6 Or 7)
RX630 Group 21. Multi-Function Pin Controller (MPC) Table 21.14 Register Settings for Input/Output Pin Function in 80-Pin LQFP PSEL[4:0] Settings 00000b Hi-Z (initial value) 00001b MTIOC4B MTIOC4D 00011b — — 00101b TMCI1 TMO3 01010b — — 01011b CTS2# — RTS2# SS2# 01101b —...
Page 543: P7N Pin Function Control Registers (P7Npfs) (N = 0, 3 To 7)
RX630 Group 21. Multi-Function Pin Controller (MPC) 21.2.9 P7n Pin Function Control Registers (P7nPFS) (n = 0, 3 to 7) Address(es): P70PFS 0008 C178h, P73PFS 0008 C17BhP, P74PFS 0008 C17Ch, P75PFS 0008 C17Dh, P76PFS 0008 C17Eh, P77PFS 0008 C17Fh — —...
Page 544: P8N Pin Function Control Registers (P8Npfs) (N = 0 To 3, 6, 7)
RX630 Group 21. Multi-Function Pin Controller (MPC) 21.2.10 P8n Pin Function Control Registers (P8nPFS) (n = 0 to 3, 6, 7) Address(es): P80PFS 0008 C180h, P81PFS 0008 C181h, P82PFS 0008 C182h, P83PFS 0008 C183h P86PFS 0008 C186h, P87PFS 0008 C187h —...
Page 545: P9N Pin Function Control Registers (P9Npfs) (N = 0 To 3)
RX630 Group 21. Multi-Function Pin Controller (MPC) 21.2.11 P9n Pin Function Control Registers (P9nPFS) (n = 0 to 3) Address(es): P90PFS 0008 C188h, P91PFS 0008 C189h, P92PFS 0008 C18Ah, P93PFS 0008 C18Bh ASEL — — PSEL[4:0] Value after reset: Symbol Bit Name Description b4 to b0...
Page 546: Pan Pin Function Select Registers (Panpfs) (N = 0 To 7)
RX630 Group 21. Multi-Function Pin Controller (MPC) 21.2.12 PAn Pin Function Select Registers (PAnPFS) (n = 0 to 7) Address(es): PA0PFS 0008 C190h, PA1PFS 0008 C191h, PA2PFS 0008 C192h, PA3PFS 0008 C193h PA4PFS 0008 C194h, PA5PFS 0008 C195h, PA6PFS 0008 C196h, PA7PFS 0008 C197h —...
Page 547 RX630 Group 21. Multi-Function Pin Controller (MPC) Table 21.20 Register Settings for Input/Output Pin Function in 80-Pin LQFP PSEL[4:0] Settings 00000b (initial value) Hi-Z 00001b MTIOC4A MTIOC0B — MTIOC0D MTIC5U — MTIC5V 00010b — MTCLKC — MTCLKD MTCLKA — MTCLKB 00011b TIOCA0 TIOCB0...
Page 548: Pbn Pin Function Control Registers (Pbnpfs) (N = 0 To 7)
RX630 Group 21. Multi-Function Pin Controller (MPC) 21.2.13 PBn Pin Function Control Registers (PBnPFS) (n = 0 to 7) Address(es): PB0PFS 0008 C198h, PB1PFS 0008 C199h, PB2PFS 0008 C19Ah, PB3PFS 0008 C19Bh PB4PFS 0008 C19Ch, PB5PFS 0008 C19Dh, PB6PFS 0008 C19Eh, PB7PFS 0008 C19Fh —...
Page 549 RX630 Group 21. Multi-Function Pin Controller (MPC) Table 21.22 Register Settings for Input/Output Pin Function in 100-Pin TFLGA, 100-/80-Pin LQFP PSEL[4:0] Settings 00000b (initial value) Hi-Z 00001b MTIC5W MTIOC0C — MTIOC0A — MTIOC2A MTIOC3D MTIOC3B 00010b — MTIOC4C — MTIOC4A —...
Page 550: Pcn Pin Function Control Register (Pcnpfs) (N = 0 To 7)
RX630 Group 21. Multi-Function Pin Controller (MPC) 21.2.14 PCn Pin Function Control Register (PCnPFS) (n = 0 to 7) Address(es): PC0PFS 0008 C1A0h, PC1PFS 0008 C1A1h, PC2PFS 0008 C1A2h, PC3PFS 0008 C1A3h PC4PFS 0008 C1A4h, PC5PFS 0008 C1A5h, PC6PFS 0008 C1A6h, PC7PFS 0008 C1A7h —...
Page 551 RX630 Group 21. Multi-Function Pin Controller (MPC) Table 21.24 Register Settings for Input/Output Pin Function in 100-Pin TFLGA, 100-Pin LQFP PSEL[4:0] Settings 00000b (initial value) Hi-Z 00001b MTIOC3C MTIOC3A MTIOC4B MTIOC4D MTIOC3D MTIOC3B MTIOC3C MTIOC3A 00010b — — — — MTCLKC MTCLKD MTCLKA...
Page 552: Pdn Pin Function Control Register (Pdnpfs) (N = 0 To 7)
RX630 Group 21. Multi-Function Pin Controller (MPC) 21.2.15 PDn Pin Function Control Register (PDnPFS) (n = 0 to 7) Address(es): PD0PFS 0008 C1A8h, PD1PFS 0008 C1A9h, PD2PFS 0008 C1AAh, PD3PFS 0008 C1ABh PD4PFS 0008 C1ACh, PD5PFS 0008 C1ADh, PD6PFS 0008 C1AEh, PD7PFS 0008 C1AFh ASEL ISEL —...
Page 553: Pen Pin Function Control Register (Penpfs) (N = 0 To 7)
RX630 Group 21. Multi-Function Pin Controller (MPC) 21.2.16 PEn Pin Function Control Register (PEnPFS) (n = 0 to 7) Address(es): PE0PFS 0008 C1B0h, PE1PFS 0008 C1B1h, PE2PFS 0008 C1B2h, PE3PFS 0008 C1B3h PE4PFS 0008 C1B4h, PE5PFS 0008 C1B5h, PE6PFS 0008 C1B6h, PE7PFS 0008 C1B7h ASEL ISEL —...
Page 554 RX630 Group 21. Multi-Function Pin Controller (MPC) Table 21.30 Register Settings for Input/Output Pin Function in 100-Pin TFLGA, 100-Pin LQFP PSEL[4:0] Settings 00000b (initial value) Hi-Z 00001b — MTIOC4C MTIOC4A MTIOC4B MTIOC4D MTIOC4C — — 00010b — — — — MTIOC1A MTIOC2B —...
Page 555: Pfn Pin Function Select Register (Pfnpfs) (N = 0 To 2, 5)
RX630 Group 21. Multi-Function Pin Controller (MPC) 21.2.17 PFn Pin Function Select Register (PFnPFS) (n = 0 to 2, 5) Address(es): PF0PFS 0008 C1B8h, PF1PFS 0008 C1B9h, PF2PFS 0008 C1BAh, PF5PFS 0008 C1BDh — ISEL — PSEL[4:0] Value after reset: Symbol Bit Name Description...
Page 556: Pj3 Pin Function Control Register (Pj3Pfs)
RX630 Group 21. Multi-Function Pin Controller (MPC) 21.2.18 PJ3 Pin Function Control Register (PJ3PFS) Address(es): PJ3PFS 0008 C1D3h — — — PSEL[4:0] Value after reset: Symbol Bit Name Description b4-b0 PSEL[4:0] Pin Function Select These bits select the peripheral function. For individual pin functions, see Table 21.33.
Page 557: Pkn Pin Function Control Register (Pknpfs) (N = 2 To 5)
RX630 Group 21. Multi-Function Pin Controller (MPC) 21.2.19 PKn Pin Function Control Register (PKnPFS) (n = 2 to 5) Address(es): PK2PFS 0008 C1DAh, PK3PFS 0008 C1DBh, PK4PFS 0008 C1DCh, PK5PFS 0008 C1DDh — — — PSEL[4:0] Value after reset: Symbol Bit Name Description b4-b0...
Page 558: Cs Output Pin Select Register 0 (Pfcss0)
RX630 Group 21. Multi-Function Pin Controller (MPC) 21.2.21 CS Output Pin Select Register 0 (PFCSS0) Address(es): 0008 C102h CS3S[1:0] CS2S[1:0] CS1S[1:0] — CS0S Value after reset: Symbol Bit Name Description CS0S CS0# Output Pin Select 0: Set P60 as CS0# output pin 1: Set PC7 as CS0# output pin —...
Page 559: Cs Output Pin Select Register 1 (Pfcss1)
RX630 Group 21. Multi-Function Pin Controller (MPC) 21.2.22 CS Output Pin Select Register 1 (PFCSS1) Address(es): 0008 C103h CS7S[1:0] CS6S[1:0] CS5S[1:0] CS4S[1:0] Value after reset: Symbol Bit Name Description b1, b0 CS4S[1:0] CS4# Output Pin Select b1 b0 0 0: Set P64 as CS4# output pin 0 1: Set P74 as CS4# output pin 1 x: Set P24 as CS4# output pin b3, b2...
Page 560: Address Output Enable Register 0 (Pfaoe0)
RX630 Group 21. Multi-Function Pin Controller (MPC) 21.2.23 Address Output Enable Register 0 (PFAOE0) Address(es): 0008 C104h A15E A14E A13E A12E A11E A10E Value after reset: Symbol Bit Name Description Address A8 Output Enable 0: Disables A8 output. 1: Enables A8 output. Address A9 Output Enable 0: Disables A9 output.
Page 561: External Bus Control Register 0 (Pfbcr0)
RX630 Group 21. Multi-Function Pin Controller (MPC) 21.2.25 External Bus Control Register 0 (PFBCR0) Address(es): 0008 C106h WR32B WR1B ADRH DH32E — — ADRLE C32E Value after reset: Symbol Bit Name Description ADRLE A0 to A7 Output Enable 0: Configures PA0 to PA7 as the I/O port pins. 1: Configures PA0 to PA7 as the external address bus A0 to A7.
Page 562: Usb0 Control Register (Pfusb0)
RX630 Group 21. Multi-Function Pin Controller (MPC) 21.2.27 USB0 Control Register (PFUSB0) Address(es): 0008 C114h PUPHZ — — — — — — — Value after reset: Symbol Bit Name Description b1-b0 — Reserved These bits are read as 0. The write value should be 0. PUPHZS PUPHZ Select 0: USB0_DPUPE pin: high-level output or low-level output...
Page 563: How To Set The External Bus Interface
RX630 Group 21. Multi-Function Pin Controller (MPC) 21.3 How to Set the External Bus Interface If the external bus interface is to be used, set the MPC registers according to Table 21.35 and then set the external bus enable bit (EXBE) in system control register 0 (SYSCR0) to 1. Table 21.35 list how to set up port pins to act as the external bus interface.
Page 564 RX630 Group 21. Multi-Function Pin Controller (MPC) Table 21.35 How to Set the External Bus Interface (2/3) Settings of MPC Registers Port Output Signal 177-Pin, 176-Pin 145-Pin, 144-Pin 100-Pin PFBCR0.DH32E = 1 (not provided) (not provided) PFAOE1.A20E = 1, (not provided) (not provided) PFBCR0.ADRHMS = 1 PFBCR0.DH32E = 1...
Page 565 RX630 Group 21. Multi-Function Pin Controller (MPC) Table 21.35 How to Set the External Bus Interface (3/3) Settings of MPC Registers Port Output Signal 177-Pin, 176-Pin 145-Pin, 144-Pin 100-Pin D5[A5/D5] — D6[A6/D6] — D7[A7/D7] — D8[A8/D8] PFBCR0.DHE = 1 D9[A9/D9] PFBCR0.DHE = 1 D10[A10/D10] PFBCR0.DHE = 1...
Page 566: Usage Notes
RX630 Group 21. Multi-Function Pin Controller (MPC) 21.4 Usage Notes 21.4.1 Procedure for Specifying Input/Output Pin Function Use the following procedure to specify the input/output pin functions. (1) Clear the port mode register (PMR) to 0 to select the general I/O port function. (2) Specify the assignments of input/output signals for peripheral functions to the desired pins.
Page 567: Notes On The Use Of Analog Functions
RX630 Group 21. Multi-Function Pin Controller (MPC) Table 21.36 Register Settings PmnPFS PMR. PDR. Item ASEL ISEL PSEL[4:0] Point to Note After a reset 00000b Pins function as general input port pins after release from the reset state. General input ports Set the PmnPFS.ISEL bit to 1 if these are multiplexed with interrupt inputs.
Page 568: Multi-Function Timer Pulse Unit 2 (Mtu2A)
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) Multi-Function Timer Pulse Unit 2 (MTU2a) 22.1 Overview The RX630 Group has an on-chip multi-function timer pulse unit 2 (MTU). Each unit comprises a 16-bit timer with six channels (MTU0 to MTU5). Table 22.1 lists the specifications of the MTU, and Table 22.2 lists the function list.
Page 569 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) Table 22.2 MTU Functions (1/2) Item MTU0 MTU1 MTU2 MTU3 MTU4 MTU5 Count clock PCLK/1 PCLK/1 PCLK/1 PCLK/1 PCLK/1 PCLK/1 PCLK/4 PCLK/4 PCLK/4 PCLK/4 PCLK/4 PCLK/4 PCLK/16 PCLK/16 PCLK/16 PCLK/16 PCLK/16 PCLK/16 PCLK/64 PCLK/64...
Page 570 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) Table 22.2 MTU Functions (2/2) Item MTU0 MTU1 MTU2 MTU3 MTU4 MTU5 A/D converter start TGRA compare TGRA compare TGRA compare TGRA compare TGRA compare — trigger match or input match or input match or input match or input match or input...
Page 571 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) Interrupt request signals MTU3: TGIA3 TGIB3 TGIC3 Input/output pins TGID3 MTU3: MTIOC3A TCIV3 MTIOC3B MTU4: TGIA4 MTIOC3C TGIB4 MTIOC3D TGIC4 MTU4: MTIOC4A TGID4 MTIOC4B TCIV4 MTIOC4C MTIOC4D Input pins MTU5: TGIU5 MTU5: MTIC5U TGIV5 MTIC5V...
Page 572 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) Table 22.3 lists the pin configuration of the MTU. Table 22.3 Pin Configuration of MTU Module Symbol Pin Name Function MTCLKA Input External clock A input pin (MTU1 phase counting mode A phase input) MTCLKB Input External clock B input pin (MTU1 phase counting mode B phase input)
Page 573: Register Descriptions
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.2 Register Descriptions 22.2.1 Timer Control Register (TCR) Address(es): MTU0.TCR 0008 8700h, MTU1.TCR 0008 8780h, MTU2.TCR 0008 8800h, MTU3.TCR 0008 8600h, MTU4.TCR 0008 8601h, MTU5.TCRU 0008 8884h, MTU5.TCRV 0008 8894h, MTU5.TCRW 0008 88A4h CCLR[2:0] CKEG[1:0] TPSC[2:0]...
Page 574 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) Table 22.4 CCLR[2:0] (MTU0, MTU3, and MTU4) Bit 7 Bit 6 Bit 5 Channel CCLR2 CCLR1 CCLR0 Description MTU0, MTU3, TCNT clearing disabled MTU4 TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing in another channel performing synchronous clearing/synchronous operation*...
Page 575 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) Table 22.7 TPSC[2:0] (MTU1) Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description MTU1 Internal clock: counts on PCLK/1 Internal clock: counts on PCLK/4 Internal clock: counts on PCLK/16 Internal clock: counts on PCLK/64 External clock: counts on MTCLKA pin input External clock: counts on MTCLKB pin input...
Page 576: Timer Mode Register (Tmdr)
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.2.2 Timer Mode Register (TMDR) Address(es): MTU0.TMDR 0008 8701h, MTU1.TMDR 0008 8781h, MTU2.TMDR 0008 8801h, MTU3.TMDR 0008 8602h, MTU4.TMDR 0008 8603h — MD[3:0] Value after reset: Symbol Bit Name Description b3 to b0 MD[3:0] Mode Select These bits specify the timer operating mode.
Page 577 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) BFA Bit (Buffer Operation A) This bit specifies normal operation for TGRA or buffered operation of the combination of TGRA and TGRC. When TGRC is used as a buffer register, TGRC input capture/output compare does not take place in modes other than complementary PWM mode, but compare match with TGRC occurs in complementary PWM mode.
Page 578: Timer I/O Control Register (Tior)
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.2.3 Timer I/O Control Register (TIOR)  MTU0.TIORH, MTU1.TIOR, MTU2.TIOR, MTU3.TIORH, MTU4.TIORH Address(es): MTU0.TIORH 0008 8702h, MTU1.TIOR 0008 8782h, MTU2.TIOR 0008 8802h, MTU3.TIORH 0008 8604h, MTU4.TIORH 0008 8606h IOB[3:0] IOA[3:0] Value after reset: Symbol Bit Name Description...
Page 579 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a)  MTU5.TIORU, MTU5.TIORV, MTU5.TIORW Address(es): MTU5.TIORU 0008 8886h, MTU5.TIORV 0008 8896h, MTU5.TIORW 0008 88A6h — — — IOC[4:0] Value after reset: Symbol Bit Name Description b4 to b0 IOC[4:0] I/O Control C See the following table.
Page 580 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) Table 22.13 TIORL (MTU0) Bit 7 Bit 6 Bit 5 Bit 4 Description IOD3 IOD2 IOD1 IOD0 MTU0.TGRD Function MTIOC0D Pin Function Output compare register* Output prohibited Initial output is 0. 0 output at compare match.
Page 581 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) Table 22.15 TIOR (MTU2) Bit 7 Bit 6 Bit 5 Bit 4 Description IOB3 IOB2 IOB1 IOB0 MTU2.TGRB Function MTIOC2B Pin Function MTU2.TGRB works as an Output prohibited output compare register Initial output is 0.
Page 582 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) Table 22.17 TIORL (MTU3) Bit 7 Bit 6 Bit 5 Bit 4 Description IOD3 IOD2 IOD1 IOD0 MTU3.TGRD Function MTIOC3D Pin Function Output compare Output prohibited register* Initial output is 0. 0 output at compare match.
Page 583 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) Table 22.19 TIORL (MTU4) Bit 7 Bit 6 Bit 5 Bit 4 Description IOD3 IOD2 IOD1 IOD0 MTU4.TGRD Function MTIOC4D Pin Function Output compare Output prohibited register* Initial output is 0. 0 output at compare match.
Page 584 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) Table 22.21 TIORL (MTU0) Bit 3 Bit 2 Bit 1 Bit 0 Description IOC3 IOC2 IOC1 IOC0 MTU0.TGRC Function MTIOC0C Pin Function Output compare Output prohibited register* Initial output is 0. 0 output at compare match.
Page 585 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) Table 22.23 TIOR (MTU2) Bit 3 Bit 2 Bit 1 Bit 0 Description IOA3 IOA2 IOA1 IOA0 MTU2.TGRA Function MTIOC2A Pin Function Output compare register Output prohibited Initial output is 0. 0 output at compare match.
Page 586 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) Table 22.25 TIORL (MTU3) Bit 3 Bit 2 Bit 1 Bit 0 Description IOC3 IOC2 IOC1 IOC0 MTU3.TGRC Function MTIOC3C Pin Function Output compare Output prohibited register* Initial output is 0. 0 output at compare match.
Page 587 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) Table 22.27 TIORL (MTU4) Bit 3 Bit 2 Bit 1 Bit 0 Description IOC3 IOC2 IOC1 IOC0 MTU4.TGRC Function MTIOC4C Pin Function Output compare Output prohibited register* Initial output is 0. 0 output at compare match.
Page 588 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) Table 22.28 TIORU, TIORV, and TIORW (MTU5) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Description MTU5.TGRU, MTU5.TGRV, IOC4 IOC3 IOC2 IOC1 IOC0 MTU5.TGRW Function MTIC5U, MTIC5V, MTIC5W Pin Function Compare match register Compare match Setting prohibited...
Page 589: Timer Compare Match Clear Register (Tcntcmpclr)
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.2.4 Timer Compare Match Clear Register (TCNTCMPCLR) Address(es): MTU5.TCNTCMPCLR 0008 88B6h CMPCL CMPCL CMPCL — — — — — Value after reset: Symbol Bit Name Description CMPCLR5W TCNT Compare Clear 0: Disables MTU5.TCNTW to be cleared to 0000h at MTU5.TCNTW and MTU5.TGRW compare match or input capture 1: Enables MTU5.TCNTW to be cleared to 0000h at MTU5.TCNTW and MTU5.TGRW compare match or input capture...
Page 590: Timer Interrupt Enable Register (Tier)
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.2.5 Timer Interrupt Enable Register (TIER)  TIER (MTU0 to MTU4) Address(es): MTU0.TIER 0008 8704h, MTU1.TIER 0008 8784h, MTU2.TIER 0008 8804h, MTU3.TIER 0008 8608h, MTU4.TIER 0008 8609h TTGE TTGE2 TCIEU TCIEV TGIED TGIEC TGIEB TGIEA Value after reset: Symbol Bit Name...
Page 591 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) TTGE2 Bit (A/D Converter Start Request Enable 2) This bit enables or disables generation of A/D converter start requests by MTU4.TCNT underflow (trough) in complementary PWM mode. In MTU0 to MTU3, this bit is reserved. It is read as 0. The write value should be 0. TTGE Bit (A/D Converter Start Request Enable) This bit enables or disables generation of A/D converter start requests by TGRA input capture/compare match.
Page 592: Timer Status Register (Tsr)
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.2.6 Timer Status Register (TSR)  TSR (MTU0 to MTU4) Address(es): MTU0.TSR 0008 8705h, MTU1.TSR 0008 8785h, MTU2.TSR 0008 8805h, MTU3.TSR 0008 862Ch, MTU4.TSR 0008 862Dh TCFD — — — — —...
Page 593: Timer Buffer Operation Transfer Mode Register (Tbtm)
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.2.7 Timer Buffer Operation Transfer Mode Register (TBTM) Address(es): MTU0.TBTM 0008 8726h, MTU3.TBTM 0008 8638h, MTU4.TBTM 0008 8639h — — — — — TTSE TTSB TTSA Value after reset: Symbol Bit Name Description TTSA Timing Select A...
Page 594: Timer Input Capture Control Register (Ticcr)
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.2.8 Timer Input Capture Control Register (TICCR) Address(es): MTU1.TICCR 0008 8790h — — — — I2BE I2AE I1BE I1AE Value after reset: x: Undefined Symbol Bit Name Description I1AE Input Capture Enable 0: Does not include the MTIOC1A pin in the MTU2.TGRA input capture conditions 1: Includes the MTIOC1A pin in the MTU2.TGRA input capture...
Page 595: Timer A/D Converter Start Request Control Register (Tadcr)
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.2.9 Timer A/D Converter Start Request Control Register (TADCR) Address(es): MTU4.TADCR 0008 8640h BF[1:0] — — — — — — UT4AE DT4AE UT4BE DT4BE ITA3AE ITA4VE ITB3AE ITB4VE Value after reset: Symbol Bit Name Description...
Page 596: Timer A/D Converter Start Request Cycle Set Registers A And B (Tadcora And Tadcorb)
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) Table 22.29 Setting of Transfer Timing by BF0[1:0] Bits Bit 15 Bit 14 Description Does not transfer data from the cycle set buffer register to the cycle set register. Transfers data from the cycle set buffer register to the cycle set register at the crest of the MTU4.TCNT count.* Transfers data from the cycle set buffer register to the cycle set register at the trough of the MTU4.TCNT count.*...
Page 597: Timer Counter (Tcnt)
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.2.12 Timer Counter (TCNT) Address(es): MTU0.TCNT 0008 8706h, MTU1.TCNT 0008 8786h, MTU2.TCNT 0008 8806h, MTU3.TCNT 0008 8610h, MTU4.TCNT 0008 8612h, MTU5.TCNTU 0008 8880h, MTU5.TCNTV 0008 8890h, MTU5.TCNTW 0008 88A0h Value after reset: Note 1.
Page 598: Timer Start Registers (Tstr)
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.2.14 Timer Start Registers (TSTR)  TSTR (MTU0 to MTU4) Address(es): MTU.TSTR 0008 8680h CST4 CST3 — — — CST2 CST1 CST0 Value after reset: Symbol Bit Name Description CST0 Counter Start 0 0: MTU0.TCNT performs count stop 1: MTU0.TCNT performs count operation CST1...
Page 599: Timer Synchronous Registers (Tsyr)
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.2.15 Timer Synchronous Registers (TSYR) Address(es): MTU.TSYR 0008 8681h SYNC4 SYNC3 — — — SYNC2 SYNC1 SYNC0 Value after reset: Symbol Bit Name Description SYNC0 Timer Synchronous Operation 0 0: MTU0.TCNT operates independently (TCNT presetting/clearing is not related to other channels).
Page 600: Timer Read/Write Enable Registers (Trwer)
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.2.16 Timer Read/Write Enable Registers (TRWER) Address(es): MTU.TRWER 0008 8684h — — — — — — — Value after reset: Symbol Bit Name Description Read/Write Enable 0: Read/write access to the registers is disabled 1: Read/write access to the registers is enabled b7 to b1 —...
Page 601: Timer Output Master Enable Registers (Toer)
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.2.17 Timer Output Master Enable Registers (TOER) Address(es): MTU.TOER 0008 860Ah — — OE4D OE4C OE3D OE4B OE4A OE3B Value after reset: Symbol Bit Name Description OE3B Master Enable MTIOC3B 0: MTU output is disabled (inactive level)* 1: MTU output is enabled OE4A Master Enable MTIOC4A...
Page 602: Timer Output Control Registers 1 (Tocr1)
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.2.18 Timer Output Control Registers 1 (TOCR1) Address(es): MTU.TOCR 0008 860Eh — PSYE — — TOCL TOCS OLSN OLSP Value after reset: Symbol Bit Name Description OLSP Output Level Select P* See Table 22.30.
Page 603 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) Table 22.30 Output Level Select Function Bit 0 Function Compare Match Output OLSP Initial Output Active Leve Up-Counting Down-Counting High level Low level Low level High level Low level High level High level Low level Table 22.31...
Page 604: Timer Output Control Registers 2 (Tocr2)
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.2.19 Timer Output Control Registers 2 (TOCR2) Address(es): MTU.TOCR2 0008 860Fh BF[1:0] OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P Value after reset: Symbol Bit Name Description OLS1P Output Level Select 1P* This bit selects the output level on MTIOC3B in reset-synchronized PWM mode and complementary PWM mode.
Page 605 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) Table 22.34 MTIOC4A Output Level Select Function Bit 2 Function Compare Match Output OLS2P Initial Output Active Level Up-Counting Down-Counting High level Low level Low level High level Low level High level High level Low level Table 22.35...
Page 606: Timer Output Level Buffer Registers (Tolbr)
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.2.20 Timer Output Level Buffer Registers (TOLBR) Address(es): MTU.TOLBR 0008 8636h — — OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P Value after reset: Symbol Bit Name Description OLS1P Output Level Select 1P Specify the buffer value to be transferred to the OLS1P bit in TOCR2.
Page 607: Timer Gate Control Registers (Tgcr)
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.2.21 Timer Gate Control Registers (TGCR) Address(es): MTU.TGCR 0008 860Dh — Value after reset: Symbol Bit Name Description Output Phase Switch These bits turn on or off the positive-phase/negative-phase output. The setting of these bits is valid only when the TGCR.FB bit s set to 1. In this case, the setting of b0 to b2 is used instead of the external input.
Page 608: Timer Subcounters (Tcnts)
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) Table 22.39 Output Level Select Function Bit 2 Bit 1 Bit 0 Function MTIOC3B MTIOC4A MTIOC4B MTIOC3D MTIOC4C MTIOC4D U Phase V Phase W Phase U Phase V Phase W Phase 22.2.22 Timer Subcounters (TCNTS) Address(es): MTU.TCNTS 0008 8620h...
Page 609: Timer Cycle Data Registers (Tcdr)
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.2.24 Timer Cycle Data Registers (TCDR) Address(es): MTU.TCDR 0008 8614h Value after reset: Note: • Accessing the TCDR in 8-bit units is prohibited. Always access in 16-bit units. TCDR is 16-bit registers used only in complementary PWM mode. Set half the PWM carrier cycle as the TCDR value. TCDR is constantly compared with the TCNTS counter in complementary PWM mode, and when a match occurs, the TCNTS counter switches direction (down-count to up-count).
Page 610 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) T4VCOR[2:0] Bits (TCIV4 Interrupt Skipping Count Setting) T3ACOR[2:0] Bits (TGIA3 Interrupt Skipping Count Setting) These bits specify the TCIV3 and TGIA4 interrupt skipping count within the range from 0 to 7. For details, see Table 22.40 and Table 22.41 .
Page 611: Timer Interrupt Skipping Counters (Titcnt)
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.2.27 Timer Interrupt Skipping Counters (TITCNT) Address(es): MTU.TITCNT 0008 8631h — T3ACNT[2:0] — T4VCNT[2:0] Value after reset: Symbol Bit Name Description b2 to b0 T4VCNT[2:0] TCIV4 Interrupt Counter While the T4VEN bit in TITCR is set to 1, the count in these bits is incremented every time a TCIV4 interrupt occurs.
Page 612: Timer Buffer Transfer Set Registers (Tbter)
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.2.28 Timer Buffer Transfer Set Registers (TBTER) Address(es): MTU.TBTER 0008 8632h — — — — — — BTE[1:0] Value after reset: Symbol Bit Name Description b1, b0 BTE[1:0] Buffer Transfer Disable and These bits enable or disable transfer from the buffer registers used Interrupt Skipping Link Setting in complementary PWM mode to the temporary registers and...
Page 613: Timer Dead Time Enable Registers (Tder)
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.2.29 Timer Dead Time Enable Registers (TDER) Address(es): MTU.TDER 0008 8634h — — — — — — — TDER Value after reset: Symbol Bit Name Description TDER Dead Time Enable 0: No dead time is generated R/(W) 1: Dead time is generated* b7 to b1...
Page 614: Timer Waveform Control Registers (Twcr)
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.2.30 Timer Waveform Control Registers (TWCR) Address(es): MTU.TWCR 0008 8660h — — — — — — Value after reset: Symbol Bit Name Description Initial Output Inhibition 0: Initial value specified in TOCR is output R/(W) Enable 1: Initial output is inhibited...
Page 615: Noise Filter Control Registers (Nfcr)
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.2.31 Noise Filter Control Registers (NFCR)  NFCR (MTU0 to MTU4) Address(es): MTU0.NFCR 0008 8690h, MTU1.NFCR 0008 8691h, MTU2.NFCR 0008 8692h, MTU3.NFCR 0008 8693h, MTU4.NFCR 0008 8694h — — NFCS[1:0] NFDEN NFCEN NFBEN NFAEN Value after reset: Symbol Bit Name...
Page 616 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) NFCS[1:0] Bits (Noise Filter Clock Select) These bits set the sampling interval for the noise filters. When setting the NFCS[1:0] bits, wait for two cycles of the selected sampling interval before setting the input-capture function. When the NFCS[1:0] bits are set to 11b, selecting the external clock as the source to drive counting, wait for two cycles of the external clock before setting the input- capture function.
Page 617: Bus Master Interface
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.2.32 Bus Master Interface The timer counters (TCNT), general registers (TGR), timer subcounter (TCNTS), timer cycle buffer register (TCBR), timer dead time data register (TDDR), timer cycle data register (TCDR), timer A/D converter start request control register (TADCR), timer A/D converter start request cycle set registers (TADCORA/B), and timer A/D converter start request cycle set buffer registers (TADCOBRA/B) are 16-bit registers.
Page 618 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (b) Free-Running Count Operation and Periodic Count Operation Immediately after a reset, the MTU’s TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1, the corresponding TCNT counter starts up-count operation as a free-running counter. When TCNT overflows (from FFFFh to 0000h), the MTU requests an interrupt if the corresponding TCIEV bit in TIER is 1.
Page 619 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (2) Waveform Output by Compare Match The MTU can be set to output 0, output 1, or toggle the level on the corresponding output pin in response to compare matches. (a) Example of Procedure for Setting Waveform Output by Compare Match Figure 22.7 shows an example of the procedure for setting waveform output by compare match Output selection [1] Select initial value low output or high output, and...
Page 620 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) TCNT value Counter cleared by TGRB compare match FFFFh TGRB TGRA Time 0000h Toggle output MTIOCB Toggle output MTIOCA Figure 22.9 Example of Toggle Output Operation (3) Input Capture Function The TCNT value can be transferred to TGR on detection of the MTIOC pin input edge. The rising edge, falling edge, or both edges can be selected as the detection edge.
Page 621 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (b) Example of Input Capture Operation Figure 22.11 shows an example of input capture operation. In this example, both rising and falling edges have been selected as the MTIOCnA pin input capture input edge, the falling edge has been selected as the MTIOCnB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT.
Page 622: Synchronous Operation
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.3.2 Synchronous Operation In synchronous operation, the values in multiple TCNT counters can be modified simultaneously (synchronous presetting). In addition, multiple TCNT counters can be cleared simultaneously (synchronous clearing) by making the appropriate setting in TCR.
Page 623 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (2) Example of Synchronous Operation Figure 22.13 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for MTU0 to MTU2, MTU0.TGRB compare match has been set as the counter clearing source in MTU0, and synchronous clearing has been set for the counter clearing source in MTU1 and MTU2.
Page 624: Buffer Operation
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.3.3 Buffer Operation Buffer operation, provided for MTU0, MTU3, and MTU4, enables TGRC and TGRD to be used as buffer registers. In MTU0, TGRF can also be used as a buffer register. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register.
Page 625 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (1) Example of Buffer Operation Setting Procedure Figure 22.16 shows an example of the buffer operation setting procedure. [1] Designate TGR as an input capture register or Buffer operation output compare register by means of TIOR. [2] Designate TGR for buffer operation with bits BFA Select TGR function and BFB in TMDR.
Page 626 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (b) When TGR is an Input Capture Register Figure 22.18 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the MTIOCnA pin input capture input edge.
Page 627: Cascaded Operation
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (3) Selecting Timing for Transfer from Buffer Registers to Timer General Registers in Buffer Operation The timing for transfer from buffer registers to timer general registers can be selected in PWM mode 1 or 2 for MTU0 or in PWM mode 1 for MTU3 and MTU4 by setting the buffer operation transfer mode registers (MTU0.TBTM, MTU3.TBTM, and MTU4.TBTM).
Page 628 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) Table 22.44 Cascaded Combinations Combination Upper 16 Bits Lower 16 Bits MTU1 and MTU2 MTU1.TCNT MTU2.TCNT For simultaneous input capture of MTU1.TCNT and MTU2.TCNT during cascaded operation, additional input capture input pins can be specified by the input capture control register (TICCR). The input-capture condition is of edges in the signal produced by taking the logical OR of the input level on the main input pin and the input level on the added input pin.
Page 629 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (2) Cascaded Operation Example (a) Figure 22.21 illustrates the operation when MTU2.TCNT overflow/underflow counting has been set for MTU1.TCNT and phase counting mode has been designated for MTU2. MTU1.TCNT is incremented by MTU2.TCNT overflow and decremented by MTU2.TCNT underflow. MTCLKC MTCLKD MTU2.TCNT...
Page 630 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (4) Cascaded Operation Example (c) Figure 22.23 illustrates the operation when MTU1.TCNT and MTU2.TCNT have been cascaded and the I2AE and I1AE bits in TICCR have been set to 1 to include the MTIOC2A and MTIOC1A pins in the MTU1.TGRA and MTU2.TGRA input capture conditions, respectively.
Page 631 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (5) Cascaded Operation Example (d) Figure 22.24 illustrates the operation when MTU1.TCNT and MTU2.TCNT have been cascaded and the I2AE bit in TICCR has been set to 1 to include the MTIOC2A pin in the MTU1.TGRA input capture conditions. In this example, the IOA3 to IOA0 bits in MTU1.TIOR have selected occurrence of MTU0.TGRA compare match or input capture for the input capture timing while the IOA3 to IOA0 bits in MTU2.TIOR have selected the MTIOC2A rising edge for the input capture timing.
Page 632: Pwm Modes
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.3.5 PWM Modes PWM modes are provided to output PWM waveforms from the external pins. The output of a 0, the output of a 1, or toggling of the output in response to a compare match with each TGR is selectable. PWM waveforms in the range of 0% to 100% duty cycle can be output according to the TGR settings.
Page 633 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (1) Example of PWM Mode Setting Procedure Figure 22.25 shows an example of the PWM mode setting procedure. [1] Set the TPSC[2:0] bits in TCR to select the counter clock. PWM mode At the same time, set the CKEG[1:0] bits in TCR to select the input clock edge.
Page 634 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) Figure 22.27 shows an example of operation in PWM mode 2. In this example, synchronous operation is designated for MTU0 and MTU1, MTU1.TGRB compare match is set as the TCNT clearing source, and 0 is set as the initial output value and 1 as the output value for the other TGR registers (MTU0.TGRA to MTU0.TGRD and MTU1.TGRA), outputting 5-phase PWM waveforms.
Page 635 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) Figure 22.28 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode. TCNT value TGRB modified TGRA TGRB TGRB modified TGRB modified 0000h Time 0% duty MTIOCA Output does not change when compare matches occur simultaneously in cycle register and duty register...
Page 636: Phase Counting Mode
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.3.6 Phase Counting Mode In phase counting mode, the phase difference between two external input clocks is detected and TCNT is incremented or decremented accordingly. This mode can be set for MTU1 and MTU2. When phase counting mode is specified, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC[2:0] and bits CKEG[1:0] in TCR.
Page 637 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (2) Examples of Phase Counting Mode Operation In phase counting mode, TCNT is incremented or decremented according to the phase difference between two external clocks. There are four modes according to the count conditions. (a) Phase Counting Mode 1 Figure 22.30 shows an example of operation in phase counting mode 1, and Table 22.48 summarizes the TCNT up/ down-count conditions.
Page 638 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (b) Phase Counting Mode 2 Figure 22.31 shows an example of operation in phase counting mode 2, and Table 22.49 summarizes the TCNT up/ down-count conditions. MTCLKA (MTU1) MTCLKC (MTU2) MTCLKB (MTU1) MTCLKD (MTU2) TCNT value Up-counting...
Page 639 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) Phase Counting Mode 3 Figure 22.32 shows an example of operation in phase counting mode 3, and Table 22.50 summarizes the TCNT up/ down-count conditions. MTCLKA (MTU1) MTCLKC (MTU2) MTCLKB (MTU1) MTCLKD (MTU2) TCNT value Down-counting...
Page 640 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (d) Phase Counting Mode 4 Figure 22.33 shows an example of operation in phase counting mode 4, and Table 22.51 summarizes the TCNT up/ down-count conditions. MTCLKA (MTU1) MTCLKC (MTU2) MTCLKB (MTU1) MTCLKD (MTU2) TCNT value Down-counting...
Page 641 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (3) Phase Counting Mode Application Example Figure 22.34 shows an example in which MTU1 is in phase counting mode, and MTU1 is coupled with MTU0 to input 2-phase encoder pulses of a servo motor in order to detect position or speed. MTU1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to MTCLKA and MTCLKB.
Page 642: Reset-Synchronized Pwm Mode
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.3.7 Reset-Synchronized PWM Mode In the reset-synchronized PWM mode, three phases of positive and negative PWM waveforms that share a common wave transition point can be output by combining MTU3 and MTU4. When set for reset-synchronized PWM mode, the MTIOC3B, MTIOC3D, MTIOC4A, MTIOC4C, MTIOC4B, and MTIOC4D pins function as PWM output pins and timer counter 3 (MTU3.TCNT) functions as an up-counter.
Page 643 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (1) Example of Procedure for Setting Reset-Synchronized PWM Mode Figure 22.35 shows an example of procedure for setting the reset-synchronized PWM mode. Clear the CST3 and CST4 bits in TSTR to 0 to stop the TCNT Reset-synchronized operation.
Page 644 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (2) Example of Reset-Synchronized PWM Mode Operation Figure 22.36 shows an example of operation in the reset-synchronized PWM mode. MTU3.TCNT and MTU4.TCNT operate as up-counters. The counters are cleared when a compare match occurs between MTU3.TCNT and MTU3.TGRA, and then begin incrementing from 0000h.
Page 645: Complementary Pwm Mode
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.3.8 Complementary PWM Mode In complementary PWM mode, three phases of non-overlapping positive and negative PWM waveforms can be output by combining MTU3 and MTU4. PWM waveforms without non-overlapping interval are also available. In complementary PWM mode, MTIOC3B, MTIOC3D, MTIOC4A, MTIOC4B, MTIOC4C, and MTIOC4D pins function as PWM output pins, and the MTIOC3A pin can be set for toggle output synchronized with the PWM cycle.
Page 646 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) TCBR MTU3.TGRC TDDR MTU3.TGRA TCDR PWM cycle Comparator Match output signal PWM output 1 PWM output 2 TCNTS MTU3.TCNT MTU4.TCNT PWM output 3 PWM output 4 PWM output 5 Comparator PWM output 6 Match External cutoff signal...
Page 647 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (1) Example of Complementary PWM Mode Setting Procedure Figure 22.38 shows an example of the complementary PWM mode setting procedure. Clear bits CST3 and CST4 in the timer start register (TSTR) to 0 to stop timer counter Complementary PWM mode (TCNT) operation.
Page 648 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (2) Outline of Complementary PWM Mode Operation In complementary PWM mode, six phases of PWM waveforms can be output. Figure 22.39 illustrates counter operation in complementary PWM mode, and Figure 22.40 shows an example of operation in complementary PWM mode. (a) Counter Operation In complementary PWM mode, three counters—MTU3.TCNT, MTU4.TCNT, and TCNTS—...
Page 649 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (b) Register Operation In complementary PWM mode, nine registers (compare registers, buffer registers, and temporary registers) are used. Figure 22.40 shows an example of operation in complementary PWM mode. MTU3.TGRB, MTU4.TGRA, and MTU4.TGRB are constantly compared with the counters to generate PWM waveforms.
Page 650 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) Transfer from temporary register Transfer from temporary register to compare register to compare register MTU3.TGRA TCNTS TCDR MTU3.TCNT MTU4.TGRA MTU4.TCNT MTU4.TGRC TDDR 0000h Buffer register 6400h 0080h MTU4.TGRC 0080h 6400h Temporary register 2 TEMP2 Compare register 6400h 0080h...
Page 651 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) Table 22.56 Registers and Counters Requiring Initial Setting Register and Counter Setting MTU3.TGRC 1/2 PWM carrier cycle + dead time Td (1/2 PWM carrier cycle + 1 when dead time generation is disabled by TDER) TDDR Dead time Td (1 when dead time generation is disabled by TDER)
Page 652 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) Transfer from temporary register to compare register MTU3.TGRA =TCDR+1 TCNTS TCDR MTU3.TCNT MTU4.TCNT MTU4.TGRA MTU4.TGRC TDDR=1 0000h Buffer register Data1 Data2 MTU4.TGRC Temporary register TEMP2 Data1 Data2 Compare register Data1 Data2 MTU4.TGRA Positive phase output Initial output Negative phase output...
Page 653 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) Counter value MTU3.TGRC MTU3.TGRA update update MTU3.TCNT MTU3.TGRA MTU4.TCNT Time Figure 22.42 Example of PWM Cycle Updating (h) Register Data Updating In complementary PWM mode, the buffer register is used to update the data in a compare register. The update data can be written to the buffer register at any time.
Page 654 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) Figure 22.43 Example of Data Updating in Complementary PWM Mode R01UH0040EJ0150 Rev.1.50 Page 654 of 1654 Sep 28, 2012...
Page 655 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) Initial Output in Complementary PWM Mode In complementary PWM mode, the initial output is determined by the setting of bits OLSN and OLSP in timer output control register 1 (TOCR1) or bits OLS1N to OLS3N and OLS1P to OLS3P in timer output control register 2 (TOCR2). This initial output is the non-active level of the PWM pulse and continues from when complementary PWM mode is set with the timer mode register (TMDR) until MTU4.TCNT exceeds the value set in the dead time register (TDDR).
Page 656 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) Timer output control register settings TOCR1.OLSN bit = 0 (initial output: high; active level: low) TOCR1.OLSP bit = 0 (initial output: high; active level: low) MTU3.TCNT values MTU3.TCNT MTU4.TCNT TDDR MTU4.TGRA Time Initial output Positive phase...
Page 657 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) As shown in Figure 22.47 , if compare match c follows compare match a before compare match b, compare match b is ignored and the negative phase is turned on by compare match d. This is because turning off the positive phase has higher priority due to the occurrence of compare match c (positive-phase off timing) before compare match b (positive-phase on timing) (consequently, the waveform does not change because the positive phase goes from off to off).
Page 658 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) T2 period T1 period T1 period MTU3.TGRA TCDR TDDR 0000h Positive phase output Negative phase output Figure 22.48 Example of Waveform Output in Complementary PWM Mode (3) 0% and 100% Duty Cycle Output in Complementary PWM Mode In complementary PWM mode, 0% and 100% duty cycle PWM waveforms can be output as required.
Page 659 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) T1 period T2 period T1 period MTU3.TGRA TCDR TDDR 0000h Positive phase output Negative phase output Figure 22.50 Example of 0% and 100% Waveform Output in Complementary PWM Mode (2) T1 period T2 period T1 period MTU3.TGRA...
Page 660 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) T1 period T2 period T1 period MTU3.TGRA TCDR TDDR 0000h c b' d a' Positive phase output Negative phase output Figure 22.52 Example of 0% and 100% Waveform Output in Complementary PWM Mode (4) T2 period T1 period T1 period...
Page 661 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) MTU3.TGRA MTU3.TCNT MTU4.TCNT 0000h Toggle output MTIOC3A pin Figure 22.54 Example of Toggle Output Waveform Synchronized with PWM Output (m) Counter Clearing by Another Channel In complementary PWM mode, MTU3.TCNT, MTU4.TCNT, and TCNTS can be cleared by another channel when a mode for synchronization with another channel is specified through the timer synchronous register (TSYR) and synchronous clearing is selected with bits CCLR[2:0] in the timer control register (TCR).
Page 662 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (n) Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode Setting the WRE bit in TWCR to 1 suppresses initial output when synchronous counter clearing occurs in the Tb interval at the trough in complementary PWM mode and controls abrupt change in duty cycle at synchronous counter clearing.
Page 663 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a)  Example of Procedure for Setting Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode. An example of the procedure for setting output waveform control at synchronous counter clearing in complementary PWM mode is shown in Figure 22.57 .
Page 664 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) Synchronous clearing Bit WRE = 1 MTU3.TGRA TCDR MTU3.TGRB MTU3.TCNT MTU4.TCNT TDDR 0000h Positive phase output Negative phase output Output waveform is active-low. Figure 22.59 Example of Synchronous Clearing in Interval Tb at Crest (Timing (6) in Figure 22.56;...
Page 665 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) Bit WRE = 1 Synchronous clearing MTU3.TGRA TCDR MTU3.TGRB MTU3.TCNT MTU4.TCNT TDDR 0000h Positive phase output Initial value output is suppressed. Negative phase output Output waveform is active-low. Figure 22.61 Example of Synchronous Clearing in Interval Tb at Trough (Timing (11) in Figure 22.56;...
Page 666 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (p) Example of Waveform Output for Driving AC Synchronous Motor (Brushless DC Motor) In complementary PWM mode, a brushless DC motor can easily be controlled using the timer gate control register (TGCR).
Page 667 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) TGCR UF bit VF bit WF bit 6-phase output MTIOC3B pin MTIOC3D pin MTIOC4A pin MTIOC4C pin MTIOC4B pin MTIOC4D pin When TGCR.BDC = 1, TGCR.N = 0, TGCR.P = 0, and TGCR.FB = 1, the high level is the active level for output.
Page 668 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) For the linkage with the A/D converter start request delaying function, refer to section 22.3.9, A/D Converter Start Request Delaying Function . The timer interrupt skipping setting register (TITCR) should be set while the TGIA3 and TCIV4 interrupt requests are disabled by the settings of MTU3.TIER and MTU4.TIER under the conditions in which compare match never occur and TGIA3 and TGIA4 interrupt requests by compare match are never generated.
Page 669 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (b) Example of Interrupt Skipping Operation Figure 22.69 shows an example of MTU3.TGIA interrupt skipping in which the interrupt skipping count is set to three by the T3ACOR bits and the T3AEN bit is set to 1 in the timer interrupt skipping set register (TITCR). Interrupt skipping period Interrupt skipping period MTU3.TGRA compare match...
Page 670 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) MTU3. TCNT MTU4. TCNT Data1 Bit BTE0 in TBTER Bit BTE1 in TBTER Data1 Data2 Buffer register Data Data2 Temporary register Data Data2 Compare register Buffer transfer is suppressed (1) No data is transferred from the buffer register to the temporary register in the buffer transfer -disabled period (setting TBTER, BTE[1:0] to 01b).
Page 671 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (1) When the buffer register is modified within one carrier cycle of the generation of a TGIA3 interrupt TGIA3 interrupt generated TGIA3 interrupt generated MTU3. TCNT MTU4. TCNT Timing for Timing for modification of the modification of the Buffer transfer-...
Page 672 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) Skipping counter T3ACNT Skipping counter T4VCNT Buffer transfer-enabled period (T3AEN is set to 1) Buffer transfer-enabled period (T4VEN is set to 1) Buffer transfer-enabled period (T3AEN and T4VEN are set to 1) •...
Page 673: A/D Converter Start Request Delaying Function
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.3.9 A/D Converter Start Request Delaying Function A/D converter start requests can be issued in MTU4 by making settings in the timer A/D converter start request control register (TADCR), timer A/D converter start request cycle set registers (MTU4.TADCORA and MTU4.TADCORB), and timer A/D converter start request cycle set buffer registers (MTU4.TADCOBRA and MTU4.TADCOBRB).
Page 674 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (2) Basic Example of A/D Converter Start Request Delaying Function Operation Figure 22.74 shows a basic example of A/D converter start request signal (TRG4AN) operation when the trough of MTU4.TCNT is specified for the buffer transfer timing and an A/D converter start request signal is output during MTU4.TCNT down-counting.
Page 675 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) MTU4.TCNT MTU4.TADCORA TGIA3 interrupt skipping counter TCIV4 interrupt skipping counter TGIA3 A/D request-enabled period TCIV4 A/D request-enabled period A/D converter start request (TRG4AN) When linked with TGIA3 and TCIV4 interrupt skipping When linked with TGIA3 interrupt skipping When linked with TCIV4...
Page 676: External Pulse Width Measurement
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.3.10 External Pulse Width Measurement Up to three external pulse widths can be measured in MTU5. (1) Example of External Pulse Width Measurement Setting Procedure External pulse width measurement [1] Set the TPSC[1:0] bits in TCR to select the counter clock. [2] In TIOR, select the high level or low level for the pulse Select counter clock width measuring condition.
Page 677: Dead Time Compensation
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.3.11 Dead Time Compensation By measuring the delay of the output waveform and reflecting it to duty, the external pulse width measurement function can be used as the dead time compensation function to PWM output waveform while the complementary PWM mode is in operation.
Page 678 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (1) Example of Dead Time Compensation Setting Procedure Figure 22.80 shows an example of dead time compensation setting procedure by using three counters in MTU5. Place MTU3 and MTU4 in complementary PWM mode. For details, refer to Complementary PWM mode section 22.3.8, Complementary PWM Mode.
Page 679: Noise Filter
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (2) TCNT Capture at Crest and/or Trough in Complementary PWM Mode Operation The MTU5.TCNT value is captured in MTU5.TGR at either the crest or trough or at both the crest and trough during complementary PWM mode operation.
Page 680: Interrupt Sources
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.4 Interrupt Sources 22.4.1 Interrupt Sources and Priorities There are three kinds of MTU interrupt source; TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own enable/disable bit, allowing the generation of interrupt request signals to be enabled or disabled individually.
Page 681: Dtc And Dmac Activation
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (1) Input Capture/Compare Match Interrupt An interrupt is requested if the TGIE bit in TIER is set to 1 when a TGR input capture/compare match occurs on a channel. The MTU has 21 input capture/compare match interrupts (six for MTU0, four each for MTU3 and MTU4, two each for MTU1 and MTU2, and three for MTU5).
Page 682 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (2) A/D Converter Activation by Compare Match between MTU0.TCNT and MTU0.TGRE A compare match between MTU0.TCNT and MTU0.TGRE activates the A/D converter. A/D converter start request signal TRG0EN is issued when a compare match occurs between MTU0.TCNT and MTU0.TGRE.
Page 683: Operation Timing
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.5 Operation Timing 22.5.1 Input/Output Timing (1) TCNT Count Timing Figure 22.84 and Figure 22.85 show the TCNT count timing for TGI interrupt in internal clock operation, Figure 22.86 shows the TCNT count timing in external clock operation (normal mode), and Figure 22.87 shows the TCNT count timing in external clock operation (phase counting mode).
Page 684 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (2) Output Compare Output Timing A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched is updated by TCNT). When a compare match signal is generated, the value set in TIOR is output to the output compare output pin (MTIOC pin).
Page 685 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (3) Input Capture Signal Timing Figure 22.90 shows the input capture signal timing. PCLK Input capture input Input capture signal TCNT Figure 22.90 Input Capture Input Signal Timing (4) Timing for Counter Clearing by Compare Match/Input Capture Figure 22.91 and Figure 22.92 show the timing when counter clearing on compare match is specified, and Figure 22.93 shows the timing when counter clearing on input capture is specified.
Page 686 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) PCLK Input capture signal Counter clear signal 0000h TCNT Figure 22.93 Counter Clear Timing (Input Capture) (MTU0 to MTU5) (5) Buffer Operation Timing Figure 22.94 to Figure 22.96 show the timing in buffer operation. PCLK TCNT Compare match signal...
Page 687 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) PCLK TCNT 0000h TCNT clear signal Buffer transfer signal TGRA, TGRB, TGRE TGRC, TGRD, TGRF Figure 22.96 Buffer Operation Timing (when TCNT Cleared) (6) Buffer Transfer Timing (Complementary PWM Mode) Figure 22.97 to Figure 22.99 show the buffer transfer timing in complementary PWM mode. PCLK TCNTS 0000h...
Page 688: Interrupt Signal Timing
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) PCLK 0000h TCNTS Buffer transfer signal Temporary register Compare register Figure 22.99 Transfer Timing from Temporary Register to Compare Register 22.5.2 Interrupt Signal Timing (1) Timing for TGI Interrupt by Compare Match Figure 22.100 and Figure 22.101 show the TGI interrupt request signal timing on compare match.
Page 689 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) PCLK TCNT input clock TCNT TG R Com pare m atch signal Interrupt signal N ote: The com pare m atch is generated even though TCNT is stopped . Figure 22.101 TGI Interrupt Timing (Compare Match) (MTU5) (2) Timing for TGI Interrupt by Input Capture Figure 22.102 and Figure 22.103 show TGI interrupt request signal timing on input capture.
Page 690 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (3) TCIV and TCIU Interrupt Timing Figure 22.104 shows the TCIV interrupt request signal timing on overflow. Figure 22.105 shows the TCIU interrupt request signal timing on underflow. PCLK TCNT input clock TCNT (overflow) FFFFh 0000h...
Page 691: Usage Notes
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.6 Usage Notes 22.6.1 Module Clock Stop Mode Setting MTU operation can be disabled or enabled using the module stop control register. MTU operation is stopped with the initial setting. Register access is enabled by clearing the module stop state. For details, refer to section 11, Low Power Consumption .
Page 692: Contention Between Tcnt Write And Clear Operations
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.6.4 Contention between TCNT Write and Clear Operations If the counter clear signal is generated in a TCNT write cycle, TCNT clearing takes precedence and TCNT write operation is not performed. Figure 22.107 shows the timing in this case.
Page 693: Contention Between Tgr Write Operation And Compare Match
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.6.6 Contention between TGR Write Operation and Compare Match If a compare match occurs in a TGR write cycle, TGR write operation is executed and the compare match signal is also generated.
Page 694: Contention Between Buffer Register Write And Tcnt Clear Operations
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.6.8 Contention between Buffer Register Write and TCNT Clear Operations When the buffer transfer timing is set at the TCNT clear timing by the buffer transfer mode register (TBTM), if TCNT clearing occurs in a TGR write cycle, the data before write operation is transferred to TGR by the buffer operation.
Page 695: Contention Between Tgr Write Operation And Input Capture
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.6.10 Contention between TGR Write Operation and Input Capture If an input capture signal is generated in a TGR write cycle, the input capture operation takes precedence and the TGR write operation is not performed in MTU0 to MTU4. In MTU5, the TGR write operation is performed and the input capture signal is generated.
Page 696: Contention Between Buffer Register Write Operation And Input Capture
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.6.11 Contention between Buffer Register Write Operation and Input Capture If an input capture signal is generated in a buffer register write cycle, the buffer operation takes precedence and the buffer register write operation is not performed.
Page 697: Counter Value When Stopped In Complementary Pwm Mode
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) TCNT written to by CPU PCLK MTU2.TCNT FFFEh FFFFh N + 1 MTU2.TCNT write data MTU2.TGRA, TGRB FFFFh MTU2 compare match signal A/B Disabled MTU1.TCNT input clock MTU1.TCNT MTU1.TGRA MTU1 compare match signal A MTU1.TGRB MTU1 input capture signal B MTU0.TCNT...
Page 698: Buffer Operation Setting In Complementary Pwm Mode
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) MTU3.TGRA TCDR MTU3.TCNT MTU4.TCNT TDDR 0000h Complementary PWM mode operation Complementary PWM mode operation Counter operation stop Complementary PMW restart Figure 22.117 Counter Value when Stopped in Complementary PWM Mode (MTU3 and MTU4 Operation) 22.6.14 Buffer Operation Setting in Complementary PWM Mode When modifying the PWM cycle set register (MTU3.TGRA), timer cycle data register (TCDR), and compare registers...
Page 699: Overflow Flags In Reset-Synchronized Pwm Mode
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) MTU3.TGRA Data are transferred from the buffer in response to compare matches MTU3.TCNT with MTU3.TGRA. Point a MTU3.TGRA MTU3.TGRC MTU3.TGRC MTU3.TGRB, MTU4.TGRA MTU4.TGRB Point b MTU3.TGRB, MTU3.TGRD MTU3.TGRD, MTU4.TGRC MTU4.TGRA, MTU4.TGRC MTU4.TGRD MTU4.TGRB, MTU4.TGRD 0000h...
Page 700: Contention Between Overflow/Underflow And Counter Clearing
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.6.17 Contention between Overflow/Underflow and Counter Clearing If an overflow/underflow and counter clearing occur simultaneously, TCNT clearing takes precedence and the corresponding TCIV interrupt is not generated. Figure 22.120 shows the operation timing when a TGR compare match is specified as the clearing source and TGR is set to FFFFh.
Page 701: Output Level In Complementary Pwm Mode Or Reset-Synchronized Pwm Mode
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) MTU3.TIORL, MTU4.TIORH, and MTU4.TIORL to initialize the output pin state to a low level, then set the registers to the initial value (00h) before making the mode transition. When making a transition from PWM mode 1 to reset-synchronized PWM mode, switch to normal mode, initialize the output pin state to a low level, and then set the registers to the initial value (00h) before making the transition to reset- synchronized PWM mode.
Page 702: Points For Caution To Prevent Malfunctions In Synchronous Clearing For Complementary Pwm Mode
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.6.25 Points for Caution to Prevent Malfunctions in Synchronous Clearing for Complementary PWM Mode If control of the output waveform is enabled (TWCR.WRE = 1) at the time of synchronous counter clearing in complementary PWM mode, satisfaction of either condition 1 or 2 below has the following effects.
Page 703 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) Synchronous clearing MTU3.TGRA MTU3. TCNT Tb interval Tb interval MTU4. TCNT TDDR Positive phase output Negative phase output Although there is no period for output of the active level over this Dead time is interval, synchronous clearing leads to output of the active level.
Page 704: Continuous Output Of Interrupt Signal In Response To A Compare Match
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.6.26 Continuous Output of Interrupt Signal in Response to a Compare Match When TGR is set to 0000h, PCLK/1 is set as the counter clock, and compare match is set as the trigger for clearing of the counter clock, the value of the counter (TCNT) counter remains 0000h, and the interrupt signal will be output continuously (i.e.
Page 705: Mtu Output Pin Initialization
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.7 MTU Output Pin Initialization 22.7.1 Operating Modes The MTU has the following six operating modes. Waveforms can be output in any of these modes.  Normal mode (MTU0 to MTU4) ...
Page 706: Overview Of Pin Initialization Procedures And Mode Transitions In Case Of Error During Operation
RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) 22.7.3 Overview of Pin Initialization Procedures and Mode Transitions in Case of Error during Operation  When making a transition to a mode (Normal, PWM1, PWM2, or PCM) in which the pin output level is selected by the timer I/O control register (TIOR) setting, initialize the pins by means of TIOR setting.
Page 707 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (1) Operation when Error Occurs in Normal Mode and Operation is Restarted in Normal Mode Figure 22.125 shows a case in which an error occurs in normal mode and operation is restarted in normal mode after re- setting.
Page 708 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (2) Operation when Error Occurs in Normal Mode and Operation is Restarted in PWM Mode 1 Figure 22.126 shows a case in which an error occurs in normal mode and operation is restarted in PWM mode 1 after re-setting.
Page 709 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (4) Operation when Error Occurs in Normal Mode and Operation is Restarted in Phase Counting Mode Figure 22.128 shows a case in which an error occurs in normal mode and operation is restarted in phase counting mode after re-setting.
Page 710 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (5) Operation when Error Occurs in Normal Mode and Operation is Restarted in Complementary PWM Mode Figure 22.129 shows a case in which an error occurs in normal mode and operation is restarted in complementary PWM mode after re-setting.
Page 711 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (6) Operation when Error Occurs in Normal Mode and Operation is Restarted in Reset- Synchronized PWM Mode Figure 22.130 shows a case in which an error occurs in normal mode and operation is restarted in reset-synchronized PWM mode after re-setting.
Page 712 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (7) Operation when Error Occurs in PWM Mode 1 and Operation is Restarted in Normal Mode Figure 22.131 shows a case in which an error occurs in PWM mode 1 and operation is restarted in normal mode after re-setting.
Page 713 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (8) Operation when Error Occurs in PWM Mode 1 and Operation is Restarted in PWM Mode 1 Figure 22.132 shows a case in which an error occurs in PWM mode 1 and operation is restarted in PWM mode 1 after re-setting.
Page 714 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (10) Operation when Error Occurs in PWM Mode 1 and Operation is Restarted in Phase Counting Mode Figure 22.134 shows a case in which an error occurs in PWM mode 1 and operation is restarted in phase counting mode after re-setting.
Page 715 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (11) Operation when Error Occurs in PWM Mode 1 and Operation is Restarted in Complementary PWM Mode Figure 22.135 shows a case in which an error occurs in PWM mode 1 and operation is restarted in complementary PWM mode after re-setting.
Page 716 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (12) Operation when Error Occurs in PWM Mode 1 and Operation is Restarted in Reset- Synchronized PWM Mode Figure 22.136 shows a case in which an error occurs in PWM mode 1 and operation is restarted in reset-synchronized PWM mode after re-setting.
Page 717 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (13) Operation when Error Occurs in PWM Mode 2 and Operation is Restarted in Normal Mode Figure 22.137 shows a case in which an error occurs in PWM mode 2 and operation is restarted in normal mode after re-setting.
Page 718 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (14) Operation when Error Occurs in PWM Mode 2 and Operation is Restarted in PWM Mode 1 Figure 22.138 shows a case in which an error occurs in PWM mode 2 and operation is restarted in PWM mode 1 after re-setting.
Page 719 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (16) Operation when Error Occurs in PWM Mode 2 and Operation is Restarted in Phase Counting Mode Figure 22.140 shows a case in which an error occurs in PWM mode 2 and operation is restarted in phase counting mode after re-setting.
Page 720 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (17) Operation when Error Occurs in Phase Counting Mode and Operation is Restarted in Normal Mode Figure 22.141 shows a case in which an error occurs in phase counting mode and operation is restarted in normal mode after re-setting.
Page 721 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (18) Operation when Error Occurs in Phase Counting Mode and Operation is Restarted in PWM Mode 1 Figure 22.142 shows a case in which an error occurs in phase counting mode and operation is restarted in PWM mode 1 after re-setting.
Page 722 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (19) Operation when Error Occurs in Phase Counting Mode and Operation is Restarted in PWM Mode 2 Figure 22.143 shows a case in which an error occurs in phase counting mode and operation is restarted in PWM mode 2 after re-setting.
Page 723 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (21) Operation when Error Occurs in Complementary PWM Mode and Operation is Restarted in Normal Mode Figure 22.145 shows a case in which an error occurs in complementary PWM mode and operation is restarted in normal mode after re-setting.
Page 724 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (22) Operation when Error Occurs in Complementary PWM Mode and Operation is Restarted in PWM Mode 1 Figure 22.146 shows a case in which an error occurs in complementary PWM mode and operation is restarted in PWM mode 1 after re-setting.
Page 725 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (23) Operation when Error Occurs in Complementary PWM Mode and Operation is Restarted in Complementary PWM Mode Figure 22.147 shows a case in which an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (when operation is restarted using the cycle and duty settings at the time of stopping the counter).
Page 726 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (24) Operation when Error Occurs in Complementary PWM Mode and Operation is Restarted in Complementary PWM Mode with New Settings Figure 22.148 shows a case in which an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (operation is restarted using new cycle and duty settings).
Page 727 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (25) Operation when Error Occurs in Complementary PWM Mode and Operation is Restarted in Reset-Synchronized PWM Mode Figure 22.149 shows a case in which an error occurs in complementary PWM mode and operation is restarted in reset- synchronized PWM mode after re-setting.
Page 728 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (26) Operation when Error Occurs in Reset-Synchronized PWM Mode and Operation is Restarted in Normal Mode Figure 22.150 shows a case in which an error occurs in reset-synchronized PWM mode and operation is restarted in normal mode after re-setting.
Page 729 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (27) Operation when Error Occurs in Reset-Synchronized PWM Mode and Operation is Restarted in PWM Mode 1 Figure 22.151 shows a case in which an error occurs in reset-synchronized PWM mode and operation is restarted in PWM mode 1 after re-setting.
Page 730 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (28) Operation when Error Occurs in Reset-Synchronized PWM Mode and Operation is Restarted in Complementary PWM Mode Figure 22.152 shows a case in which an error occurs in reset-synchronized PWM mode and operation is restarted in complementary PWM mode after re-setting.
Page 731 RX630 Group 22. Multi-Function Timer Pulse Unit 2 (MTU2a) (29) Operation when Error Occurs in Reset-Synchronized PWM Mode and Operation is Restarted in Reset-Synchronized PWM Mode Figure 22.153 shows a case in which an error occurs in reset-synchronized PWM mode and operation is restarted in reset-synchronized PWM mode after re-setting.
Page 732: Port Output Enable 2 (Poe2A)
RX630 Group 23. Port Output Enable 2 (POE2a) Port Output Enable 2 (POE2a) The port output enable 2 (POE) module can be used to place the states of the pins for complementary PWM output by the MTU (MTIOC3B, MTIOC3D, MTIOC4A, MTIOC4B, MTIOC4C, and MTIOC4D), and the states of pins for MTU0 (MTIOC0A, MTIOC0B, MTIOC0C, and MTIOC0D) in the high-impedance in response to changes in the input levels on the POE0# to POE3# and POE8# pins, in the output levels on pins for complementary PWM output by the MTU, oscillation stop detection by the clock generation circuit, and changes to register settings (SPOER).
Page 733 RX630 Group 23. Port Output Enable 2 (POE2a) POECR1 POECR2 OSTST Oscillation stop detection signal from the clock generation circuit MTIOC3B Output level comparison circuit MTIOC3D Output enable signal MTIOC4A Output level for MTU3 and MTU4 pins comparison circuit MTIOC4C Output enable signal MTIOC4B Output level...
Page 734 RX630 Group 23. Port Output Enable 2 (POE2a) Table 23.2 lists input/output pins to be used by the POE. Table 23.2 LSI Input/Output Pins to be Used by POE Pin Name Description POE0# to POE3# Input Request signals to place the pins for MTU complementary PWM output in high-impedance. POE8# Input Request signals to place the MTU0 pins in high-impedance.
Page 735: Register Descriptions
RX630 Group 23. Port Output Enable 2 (POE2a) 23.2 Register Descriptions 23.2.1 Input Level Control/Status Register 1 (ICSR1) Address(es): 0008 8900h POE3F POE2F POE1F POE0F — — — PIE1 POE3M[1:0] POE2M[1:0] POE1M[1:0] POE0M[1:0] Value after reset: Symbol Bit Name Description b1, b0 POE0M[1:0] POE0 Mode...
Page 736 RX630 Group 23. Port Output Enable 2 (POE2a) When low-level sampling has been set by the POE0M[1:0] to POE3M[1:0] bits, writing 0 to the POE0F to POE3F flags requires high level input on the POE0# to POE3# pins. For details, see section 23.3.5, Release from the High-Impedance . PIE1 Bit (Port Interrupt Enable 1) This bit enables or disables OEI1 interrupt requests when any one of the POE0F to POE3F flags is set to 1.
Page 737: Output Level Control/Status Register 1 (Ocsr1)
RX630 Group 23. Port Output Enable 2 (POE2a) 23.2.2 Output Level Control/Status Register 1 (OCSR1) Address(es): 0008 8902h OSF1 — — — — — OCE1 OIE1 — — — — — — — — Value after reset: Symbol Bit Name Description b7 to b0 —...
Page 738: Input Level Control/Status Register 2 (Icsr2)
RX630 Group 23. Port Output Enable 2 (POE2a) 23.2.3 Input Level Control/Status Register 2 (ICSR2) Address(es): 0008 8908h — — — POE8F — — POE8E PIE2 — — — — — — POE8M[1:0] Value after reset: Symbol Bit Name Description b1, b0 POE8M[1:0] POE8 Mode...
Page 739: Software Port Output Enable Register (Spoer)
RX630 Group 23. Port Output Enable 2 (POE2a) 23.2.4 Software Port Output Enable Register (SPOER) Address(es): 0008 890Ah CH0HI CH34HI — — — — — — Value after reset: Symbol Bit Name Description CH34HIZ MTU3 and MTU4 Output High- 0: Does not place the pins in high-impedance. Impedance Enable 1: Places the pins in high-impedance.
Page 740: Port Output Enable Control Register 1 (Poecr1)
RX630 Group 23. Port Output Enable 2 (POE2a) 23.2.5 Port Output Enable Control Register 1 (POECR1) Address(es): 0008 890Bh — — — — PE3ZE PE2ZE PE1ZE PE0ZE Value after reset: Symbol Bit Name Description PE0ZE MTIOC0A High-Impedance 0: Does not place the pin in high-impedance. R/W* Enable 1: Places the pin in high-impedance.
Page 741: Input Level Control/Status Register 3 (Icsr3)
RX630 Group 23. Port Output Enable 2 (POE2a) P2CZEA Bit (MTU Port 2 High-Impedance Enable) This bit gives permission regarding whether or not the MTIOC4A and MTIOC4C pins for complementary PWM output from the MTU are placed in the high-impedance. It also gives permission regarding whether or not the levels on the MTIOC4A and MTIOC4C pins are compared.
Page 742: Operation
RX630 Group 23. Port Output Enable 2 (POE2a) 23.3 Operation The target pins for high-impedance control and conditions to place the pins in high-impedance are described below. (1) MTU0 pin (MTIOC0A) When any of the following conditions is satisfied, the pin is placed to the high-impedance state. ...
Page 743 RX630 Group 23. Port Output Enable 2 (POE2a)  Detection of stopped oscillation When ICSR3.OSTSTF flag is set to 1 with POECR2.P1CZEA and ICSR3.OSTSTE set to 1. (6) MTU4 pins (MTIOC4A and MTIOC4C) When any of the following conditions is satisfied, the pins are placed to the high-impedance state. ...
Page 744: Input Level Detection Operation
RX630 Group 23. Port Output Enable 2 (POE2a) 23.3.1 Input Level Detection Operation If the input conditions set by ICSR1 and ICSR2 occur on the POE0# to POE3# and POE8# pins, the pins for the MTU complementary PWM output and MTU0 are placed in high-impedance. (1) Falling Edge Detection When a change from a high to low level is input to the POE0# to POE3# and POE8# pins, the pins for the MTU complementary PWM output and MTU0 are placed in high-impedance.
Page 745: Output-Level Compare Operation
RX630 Group 23. Port Output Enable 2 (POE2a) 23.3.2 Output-Level Compare Operation Figure 23.4 shows an example of the output-level compare operation for the combination of MTIOC3B and MTIOC3D (MTU complementary PWM output pins). The operation is the same for the other pin combinations. PCLK Low level overlapping detected* MTIOC3B...
Page 746: Interrupts
RX630 Group 23. Port Output Enable 2 (POE2a) 23.4 Interrupts The POE issues a request to generate an interrupt when the corresponding condition below is matched during input-level detection, output-level comparison, or oscillation stop by the clock generation circuit. Table 23.4 shows the interrupt sources and their request conditions.
Page 747: Overview
RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) 16-Bit Timer Pulse Unit (TPUa) The RX630 Group has two on-chip 16-bit timer pulse units (TPU), unit 0 and unit 1, each comprising six channels. Therefore, this LSI includes twelve channels (TPU0 to TPU11). 24.1 Overview Specifications of the TPU are listed in Table 24.1 .
Page 748 RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) Table 24.2 TPU (Unit 0) Functions Item TPU0 TPU1 TPU2 TPU3 TPU4 TPU5 Count clock PCLK/1 PCLK/1 PCLK/1 PCLK/1 PCLK/1 PCLK/1 PCLK/4 PCLK/4 PCLK/4 PCLK/4 PCLK/4 PCLK/4 PCLK/16 PCLK/16 PCLK/16 PCLK/16 PCLK/16 PCLK/16 PCLK/64 PCLK/64...
Page 749 RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) Table 24.3 TPU (Unit 1) Functions Item TPU6 TPU7 TPU8 TPU9 TPU10 TPU11 Count clock PCLK/1 PCLK/1 PCLK/1 PCLK/1 PCLK/1 PCLK/1 PCLK/4 PCLK/4 PCLK/4 PCLK/4 PCLK/4 PCLK/4 PCLK/16 PCLK/16 PCLK/16 PCLK/16 PCLK/16 PCLK/16 PCLK/64 PCLK/64...
Page 750 RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) [Interrupt request signals] [Input/output pins] TPU3: TGI3A TPU3: TIOCA3 TGI3B TIOCB3 TGI3C TIOCC3 TGI3D TIOCD3 TCI3V TPU4: TIOCA4 TPU4: TGI4A TIOCB4 TGI4B TPU5: TIOCA5 TCI4V TIOCB5 TCI4U TGI5A TPU5: TGI5B TCI5V TCI5U [Clock input] Internal clock: PCLK/1...
Page 751 RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) [Interrupt request signals] [Input/output pins] TPU9: TGI9A TPU9: TIOCA9 TGI9B TIOCB8 TGI9C TIOCC9 TGI9D TIOCD9 TCI9V TPU10: TIOCA10 TPU10: TGI10A TIOCB10 TGI10B TPU11: TIOCA11 TCI10V TIOCB11 TCI10U TPU11: TGI11A TGI11B TCI11V TCI11U [Clock input] Internal clock: PCLK/1...
Page 752 RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) Table 24.4 lists the input/output pins of the TPU. Table 24.4 Pin Configuration of TPU Unit Channel Pin Name I/O Description Unit 0 Common TCLKA Input External clock A input pin (TPU1 and TPU5 phase counting mode A phase input) to unit 0 TCLKB Input...
Page 753: Register Descriptions
RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) 24.2 Register Descriptions 24.2.1 Timer Control Register (TCR) Address(es): TPU0.TCR 0008 8110h, TPU1.TCR 0008 8120h, TPU2.TCR 0008 8130h, TPU3.TCR 0008 8140h, TPU4.TCR 0008 8150h, TPU5.TCR 0008 8160h, TPU6.TCR 0008 8180h, TPU7.TCR 0008 8190h, TPU8.TCR 0008 81A0h, TPU9.TCR 0008 81B0h, TPU10.TCR 0008 81C0h, TPU11.TCR 0008 81D0h CCLR[2:0] CKEG[1:0]...
Page 754 RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) Table 24.5 Bits TPSC[2:0] (TPU0, TPU6) Bits TPSC[2:0] Channel Description TPU0 (unit 0) Internal clock: counts on PCLK/1 TPU6 (unit 1) Internal clock: counts on PCLK/4 Internal clock: counts on PCLK/16 Internal clock: counts on PCLK/64 External clock ...
Page 755 RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) Table 24.7 Bits TPSC[2:0] (TPU2, TPU8) Bits TPSC[2:0] Channel Description TPU2 (unit 0) Internal clock: counts on PCLK/1 TPU8 (unit 1) Internal clock: counts on PCLK/4 Internal clock: counts on PCLK/16 Internal clock: counts on PCLK/64 External clock ...
Page 756 RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) Table 24.9 Bits TPSC[2:0] (TPU4, TPU10) Bits TPSC[2:0] Channel Description TPU4 (unit 0) Internal clock: counts on PCLK/1 TPU10 (unit 1) Internal clock: counts on PCLK/4 Internal clock: counts on PCLK/16 Internal clock: counts on PCLK/64 External clock ...
Page 757 RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) Table 24.11 Bits CKEG[1:0] Bits CKEG[1:0] Input Clock Internal Clock External clock Counted at falling edge Counted at rising edge Counted at rising edge Counted at falling edge Counted at both edges Counted at both edges Counted at both edges Counted at both edges...
Page 758: Timer Mode Register (Tmdr)
RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) 24.2.2 Timer Mode Register (TMDR) Address(es): TPU0.TMDR 0008 8111h, TPU1.TMDR 0008 8121h, TPU2.TMDR 0008 8131h, TPU3.TMDR 0008 8141h, TPU4.TMDR 0008 8151h, TPU5.TMDR 0008 8161h, TPU6.TMDR 0008 8181h, TPU7.TMDR 0008 8191h, TPU8.TMDR 0008 81A1h, TPU9.TMDR 0008 81B1h, TPU10.TMDR 0008 81C1h, TPU11.TMDR 0008 81D1h ICSELD ICSELB MD[3:0]...
Page 759: Timer I/O Control Register (Tiorh, Tiorl, Tior)
RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) ICSELD Bit (TGRD Input Capture Input Select) Selects the input capture input for TPUm.TGRD (m = 0, 3, 6, 9). This function allows measurement of high-level width and period of the input pulse on a TIOCCn input pin. 24.2.3 Timer I/O Control Register (TIORH, TIORL, TIOR) ...
Page 760 RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa)  Unit 0 (TPU0.TIORL, TPU3.TIORL) Unit 1 (TPU6.TIORL, TPU9.TIORL) Address(es): TPU0.TIORL 0008 8113h, TPU3.TIORL 0008 8143h, TPU6.TIORL 0008 8183h, TPU9.TIORL 0008 81B3h IOD[3:0] IOC[3:0] Value after reset: Symbol Bit Name Description b3 to b0 IOC[3:0] TGRC Control See Table 24.20 and Table 24.21.*...
Page 761 RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) Table 24.14 TPU0.TIORH, TPU6.TIORH Bits IOA[3:0] Description TPUm.TGRA (m = 0, 6) Function TIOCAn Pin (n = 0, 6) Function and Related Issue Output compare register Output disabled Initial output is low output; low output at compare match Initial output is low output;...
Page 762 RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) Table 24.15 TPU1.TIOR, TPU7.TIOR Bits IOA[3:0] Description TPUm.TGRA (m = 1, 7) Function TIOCAn Pin (n = 1, 7) Function and Related Issue Output compare register Output disabled Initial output is low output; low output at compare match Initial output is low output;...
Page 763 RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) Table 24.16 TPU2.TIOR, TPU8.TIOR Bits IOA[3:0] Description TPUm.TGRA (m = 2, 8) Function TIOCAn Pin (n = 2, 8) Function and Related Issue Output compare register Output disabled Initial output is low output; low output at compare match Initial output is low output;...
Page 764 RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) Table 24.17 TPU3.TIORH, TPU9.TIORH Bits IOA[3:0] Description TPUm.TGRA (m = 3, 9) Function TIOCAn Pin (n = 3, 9) Function and Related Issue Output compare register Output disabled Initial output is low output; low output at compare match Initial output is low output;...
Page 765 RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) Table 24.18 TPU4.TIOR, TPU10.TIOR Bits IOA[3:0] Description TPUm.TGRA (m = 4, 10) Function TIOCAn Pin (n = 4, 10) Function and Related Issue Output compare register Output disabled Initial output is low output; low output at compare match Initial output is low output;...
Page 766 RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) Table 24.19 TPU5.TIOR, TPU11.TIOR Bits IOA[3:0] Description TPUm.TGRA (m = 5, 11) Function TIOCAn Pin (n = 5, 11) Function and Related Issue Output compare register Output disabled Initial output is low output; low output at compare match Initial output is low output;...
Page 767 RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) Table 24.20 TPU0.TIORL, TPU6.TIORL Bits IOC[3:0] Description TPUm.TGRC (m = 0, 6) Function TIOCCn Pin (n = 0, 6) Function and Related Issue Output compare register* Output disabled Initial output is low output; low output at compare match Initial output is low output;...
Page 768 RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) Table 24.21 TPU3.TIORL, TPU9.TIORL Bits IOC[3:0] Description TPUm.TGRC (m = 3, 9) Function TIOCCn Pin (m = 3, 9) Function and Related Issue Output compare register* Output disabled Initial output is low output; low output at compare match Initial output is low output;...
Page 769: Timer Interrupt Enable Register (Tier)
RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) 24.2.4 Timer Interrupt Enable Register (TIER) Address(es): TPU0.TIER 0008 8114h, TPU1.TIER 0008 8124h, TPU2.TIER 0008 8134h, TPU3.TIER 0008 8144h, TPU4.TIER 0008 8154h, TPU5.TIER 0008 8164h, TPU6.TIER 0008 8184h, TPU7.TIER 0008 8194h, TPU8.TIER 0008 81A4h, TPU9.TIER 0008 81B4h, TPU10.TIER 0008 81C4h, TPU11.TIER 0008 81D4h TTGE —...
Page 770: Timer Status Register (Tsr)
RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) 24.2.5 Timer Status Register (TSR) Address(es): TPU0.TSR 0008 8115h, TPU1.TSR 0008 8125h, TPU2.TSR 0008 8135h, TPU3.TSR 0008 8145h, TPU4.TSR 0008 8155h, TPU5.TSR 0008 8165h, TPU6.TSR 0008 8185h, TPU7.TSR 0008 8195h, TPU8.TSR 0008 81A5h, TPU9.TSR 0008 81B5h, TPU10.TSR 0008 81C5h, TPU11.TSR 0008 81D5h TCFD —...
Page 771 RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa)  When TPUm.TGRA is serving as an input-capture register, the input-capture signal has caused transfer of the value in TPUm.TCNT to TPUm.TGRA. [Clearing conditions]  Activation of the DTC by the TGImA interrupt and clearing of the DTC.MRB.DISEL bit. ...
Page 772: Timer Counter (Tcnt)
RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) TCFV Flag (Overflow Flag) This status flag indicates an overflow of TPUm.TCNT (m = 0 to 11). [Setting condition]  Overflow of the value in TPUm.TCNT (TCNT counted from FFFFh to 0000h). [Clearing condition] ...
Page 773: Timer General Register A (Tgra) Timer General Register B (Tgrb) Timer General Register C (Tgrc) Timer General Register D (Tgrd)
RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) 24.2.7 Timer General Register A (TGRA) Timer General Register B (TGRB) Timer General Register C (TGRC) Timer General Register D (TGRD) Address(es): TPU0.TGRA 0008 8118h, TPU0.TGRB 0008 811Ah, TPU0.TGRC 0008 811Ch, TPU0.TGRD 0008 811Eh, TPU1.TGRA 0008 8128h, TPU1.TGRB 0008 812Ah, TPU2.TGRA 0008 8138h, TPU2.TGRB 0008 813Ah, TPU3.TGRA 0008 8148h, TPU3.TGRB 0008 814Ah, TPU3.TGRC 0008 814Ch, TPU3.TGRD 0008 814Eh,...
Page 774: Timer Start Register (Tstr)
RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) 24.2.8 Timer Start Register (TSTR)  Unit 0 (TPUA.TSTR) Address(es): TPUA.TSTR 0008 8100h CST5 CST4 CST3 CST2 CST1 CST0 — — Value after reset: Symbol Bit Name Description CST0 Counter Start 0 0: TCNT count operation is stopped 1: TCNT performs count operation CST1...
Page 775: Timer Synchronous Register (Tsyr)
RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) 24.2.9 Timer Synchronous Register (TSYR)  Unit 0 (TPUA.TSYR) Address(es): TPUA.TSYR 0008 8101h — — SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 Value after reset: Symbol Bit Name Description SYNC0 Timer Synchronization 0 0: TCNT operates independently (TCNT presetting/clearing is unrelated to other channels) SYNC1...
Page 776: Noise Filter Control Register (Nfcr)
RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) 24.2.10 Noise Filter Control Register (NFCR) Address(es): TPU0.NFCR 0008 8108h, TPU1.NFCR 0008 8109h, TPU2.NFCR 0008 810Ah, TPU3.NFCR 0008 810Bh, TPU4.NFCR 0008 810Ch, TPU5.NFCR 0008 810Dh, TPU6.NFCR 0008 8178h, TPU7.NFCR 0008 8179h, TPU8.NFCR 0008 817Ah, TPU9.NFCR 0008 817Bh, TPU10.NFCR 0008 817Ch, TPU11.NFCR 0008 817Dh —...
Page 777 RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) NFDEN Bit (Noise Filter Enable D) This bit disables or enables the noise filter for the TIOCDm pin (m = 0, 3, 6, 9). Since unexpected edges may be internally generated when the value of NFDEN is changed, select the output compare function in the timer I/O control register before changing the NFDEN value.
Page 778: Operation
RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) 24.3 Operation 24.3.1 Basic Functions Each channel has a TPUm.TCNT counter and a TPUm.TGRy register (y = A to D). TCNT is a 16-bit up-counter, which can function as a free-running counter, periodic counter, or event counter. TGRy can be used as an input capture register or output compare register.
Page 779 RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) (b) Free-running count operation and periodic count operation Immediately after a reset, the TPUm.TCNT counters are all set as free-running counters. When the relevant bit in TPUA.TSTR or TPUB.TSTR is set to 1, the corresponding TCNT counter starts up-count operation as a free-running counter.
Page 780 RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) (2) Waveform Output by Compare Match The TPU can perform low, high, or toggle output from the corresponding output pin using a compare match. (a) Example of setting procedure for waveform output by compare match Figure 24.6 shows an example of the setting procedure for waveform output by a compare match.
Page 781 RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) Figure 24.8 shows an example of toggle output. In this example, TPUm.TCNT has been set as a periodic counter (with counter clearing performed by compare match B), and settings have been made so that output is toggled by both compare match A and compare match B. TCNT value Counter cleared by TGRB compare match FFFFn...
Page 782 RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) (b) Example of input capture operation Figure 24.10 shows an example of input capture operation when the noise filter is stopped. In this example, both rising and falling edges have been selected as the TIOCAn pin input capture input edge, the falling edge has been selected as the TIOCBn pin input capture input edge, and counter clearing by TPUm.TGRB input capture has been set for TPUm.TCNT.
Page 783: Synchronous Operation
RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) 24.3.2 Synchronous Operation In synchronous operation, the values in multiple TPUm.TCNT counters can be rewritten simultaneously (synchronous presetting). Also, multiple TCNT counters can be cleared simultaneously (synchronous clearing) by making the appropriate setting in TPUm.TCR. Synchronous operation enables TPUm.TGRy to be incremented with respect to a single time base.
Page 784 RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) (2) Example of Synchronous Operation Figure 24.12 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been set for TPU0 to TPU2, TPU0.TGRB compare match has been set as the TPU0 counter clearing source, and synchronous clearing has been set for the TPU1 and TPU2 counter clearing source.
Page 785: Buffer Operation
RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) 24.3.3 Buffer Operation Buffer operation, provided for TPU0 and TPU3 (TPU6 and TPU9), enables TPUm.TGRC and TPUm.TGRD to be used as buffer registers. Buffer operation differs depending on whether TPUm.TGRy has been set as an input capture register or a compare match register.
Page 786 RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) (1) Example of Buffer Operation Setting Procedure Figure 24.15 shows an example of the buffer operation setting procedure. [1] Set TGRy as an input capture register or output Buffer operation compare register by TIOR (y = A to D). [2] Set TGRy for buffer operation with bits BFA and Select TGRy function BFB in TMDR.
Page 787 RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) (b) When TPUm.TGRy is an input capture register Figure 24.17 shows an operation example in which TPUm.TGRA has been set as an input capture register, and buffer operation has been set for the TGRA register and TPUm.TGRC. Counter clearing by TGRA input capture has been set for TPUm.TCNT, and both rising and falling edges have been selected as the TIOCAn pin input capture input edge.
Page 788: Cascaded Operation
RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) 24.3.4 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. In the case of unit 0, this function works by counting the TPU1 (TPU4) counter clock at overflow/underflow of TPU2.TCNT (TPU5.TCNT) as set by the TPSC[2:0] bits in TPU1.TCR (TPSC[2:0] bits in TPU4.TCR).
Page 789 RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) (2) Examples of Cascaded Operation Figure 24.19 shows the operation when counting upon TPU2.TCNT overflow/underflow has been set for TPU1.TCNT, TPU1.TGRA and TPU2.TGRA have been set as input capture registers, and the rising edge of the TIOCA1 and TIOCA2 pins has been selected.
Page 790: Pwm Modes
RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) 24.3.5 PWM Modes In PWM mode, PWM waveforms are output from the output pins. low-, high-, or toggle-output can be selected as the output level in response to compare match of each TPUm.TGRy. Settings of TGRy registers can output a PWM waveform in the range of 0% to 100% duty cycle.
Page 791 RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) The correspondence between PWM output pins and registers is listed in Table 24.24 . Table 24.24 PWM Output Registers and Output Pins Output Pin Unit Channel Register PWM Mode 1 PWM Mode 2 TPU0 TPU0.TGRA TIOCA0...
Page 792 RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) (1) Example of PWM Mode Setting Procedure Figure 24.21 shows an example of the PWM mode setting procedure. [1] Select the counter clock with the TPSC[2:0] bits PWM mode in TCR. At the same time, select the input clock edge with the CKEG[1:0] bits in TCR.
Page 793 RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) Figure 24.23 shows an example of PWM mode 2 operation. In this example, synchronous operation is specified for TPU0 and TPU1, TPU1.TGRB compare match is set as the TPUm.TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TPUm.TGRy registers (TPU0.TGRA to TPU0.TGRD and TPU1.TGRA), to output a 5-phase PWM waveform.
Page 794 RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) Figure 24.24 shows examples of PWM waveform output with 0% duty cycle and 100% duty cycle in PWM mode. TCNT value TGRB changed TGRA TGRB changed TGRB TGRB changed 0000h Time 0% duty cycle TIOCA Output does not change when compare matches in cycle register and duty register occur simultaneously.
Page 795: Phase Counting Mode
RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) 24.3.6 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected by the settings for channels 1, 2, 4, and 5 (unit 0) and channels 7, 8, 10, and 11 (unit 1), and TPUm.TCNT is incremented/decremented accordingly. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up-/ down-counter regardless of the setting of the TPSC[2:0] bits and CKEG[1:0] bits in TPUm.TCR.
Page 796 RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) (2) Examples of Phase Counting Mode Operation In phase counting mode, TPUm.TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. (a) Phase counting mode 1 Figure 24.26 shows an example of phase counting mode 1 operation, and Table 24.26 lists the TPUm.TCNT up-/ down-count conditions.
Page 797 RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) (b) Phase counting mode 2 Figure 24.27 shows an example of phase counting mode 2 operation, and Table 24.27 lists the TPUm.TCNT up-/ down-count conditions. TCLKA (TPU1, TPU5) TCLKC (TPU2, TPU4) TCLKE (TPU7, TPU11) TCLKG (TPU8, TPU10) TCLKB (TPU1, TPU5) TCLKD (TPU2, TPU4)
Page 798 RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) Phase counting mode 3 Figure 24.28 shows an example of phase counting mode 3 operation, and Table 24.28 lists the TPUm.TCNT up-/ down-count conditions. TCLKA (TPU1, TPU5) TCLKC (TPU2, TPU4) TCLKE (TPU7, TPU11) TCLKG (TPU8, TPU10) TCLKB (TPU1, TPU5) TCLKD (TPU2, TPU4)
Page 799 RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) (d) Phase counting mode 4 Figure 24.29 shows an example of phase counting mode 4 operation, and Table 24.29 lists the TPUm.TCNT up-/ down-count conditions. TCLKA (TPU1, TPU5) TCLKC (TPU2, TPU4) TCLKE (TPU7, TPU11) TCLKG (TPU8, TPU10) TCLKB (TPU1, TPU5) TCLKD (TPU2, TPU4)
Page 800: Phase Counting Mode Application Example
RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) 24.3.6.1 Phase Counting Mode Application Example Figure 24.30 shows an example in which phase counting mode is set for TPU1, and TPU1 is coupled with TPU0 to input servo motor 2-phase encoder pulses in order to detect the position or speed. TPU1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to the TCLKA and TCLKB pins.
Page 801: Noise Filters
RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) 24.3.7 Noise Filters Each pin for use in input capture by TPU is equipped with a noise filter. The noise filter samples the level on the pin three times at the selected sampling interval, conveys the level to the internal circuits if the samples match, and continues to convey that level until the other level is sampled from the pins three times in a row.
Page 802: Interrupt Sources
RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) 24.4 Interrupt Sources There are three kinds of TPU interrupt sources: TPUm.TGRy input capture/compare match, TPUm.TCNT overflow, and TPUm.TCNT underflow. Relative channel priority levels can be changed by the interrupt controller, but the priority within a channel is fixed. For details, see section 15, Interrupt controller (ICUb) .
Page 803 RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) Table 24.30 TPU Interrupt Sources (2/2) DMAC Unit Channel Name Interrupt Source Activation Activation TPU6 TGI6A TPU6.TGRA input capture/compare match Possible Possible TGI6B TPU6.TGRB input capture/compare match Possible Not possible TGI6C TPU6.TGRC input capture/compare match Possible Not possible TGI6D...
Page 804: Dtc Activation
RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) (1) Input Capture/Compare Match Interrupt An interrupt is requested when the TGIEy bit (y = A, B, C, D) in TPUm.TIER is set to 1 by the occurrence of a TPUm.TGRy input capture/compare match on a channel. The TPU has 32 input capture/compare match interrupts, four each for TPU0, TPU3, TPU6 and TPU9, and two each for TPU1, TPU2, TPU4, TPU5, TPU7, TPU8, TPU10, and TPU11.
Page 805: Operation Timing
RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) 24.9 Operation Timing 24.9.1 Input/Output Timing (1) TPUm.TCNT Count Timing Figure 24.32 shows TPUm.TCNT count timing in internal clock operation, and Figure 24.33 shows TCNT count timing in external clock operation. PCLK Falling edge Rising edge Falling edge...
Page 806 RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) (2) Output Compare Output Timing A compare match signal is generated in the final state in which TPUm.TCNT and TPUm.TGRy match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TPUm.TIORH, TPUm.TIORL, or TPUm.TIOR is output to the output compare output pin TIOCyn (y = A to D, n = 0 to 11).
Page 807 RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) (4) Timing for Counter Clearing by Compare Match/Input Capture Figure 24.36 shows the timing when counter clearing by compare match occurrence is specified, and Figure 24.37 shows the timing when counter clearing by input capture occurrence is specified. PCLK Compare match signal Counter clear signal...
Page 808 RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) (5) Buffer Operation Timing Figure 24.38 and Figure 24.39 show the timings in buffer operation. PCLK N + 1 TCNT Compare match signal TGRA, TGRB TGRC, TGRD Figure 24.38 Buffer Operation Timing (Compare Match) PCLK Input capture signal TCNT...
Page 809: Interrupt Signal Timing
RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) 24.9.2 Interrupt Signal Timing (1) Timing of Interrupt Signal Setting on Compare Match Figure 24.40 shows the timing for setting the interrupt signal by compare match occurrence. PCLK TCNT input clock N + 1 TCNT TGRy Compare match signal...
Page 810 RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) (3) Timing of TCImV/TCImU Interrupt Signal Setting Figure 24.42 shows the timing for generating the TCImV interrupt signal by overflow occurrence. Figure 24.43 shows the timing for generating the TCImU interrupt signal by underflow occurrence. PCLK TCNT input clock TCNT (overflow)
Page 811: 24.10 Usage Notes
RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) 24.10 Usage Notes 24.10.1 Module-Stop Function Setting Operation of the TPU can be disabled or enabled using the module-stop control register. The TPU does not operate with the initial setting. Register access is enabled by clearing module-stop state. For details, see section 11, Low Power Consumption .
Page 812: Caution On Cycle Setting
RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) 24.10.3 Caution on Cycle Setting When counter clearing by compare match is set, TPUm.TCNT is cleared in the final state in which it matches the TPUm.TGRy value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: TCNT_CLK (N+1)
Page 813: Conflict Between Tpum.tgry Write And Compare Match
RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) 24.10.6 Conflict between TPUm.TGRy Write and Compare Match If a compare match occurs in a TGRy write cycle, the TGRy write takes precedence and the compare match signal is disabled. A compare match also does not occur when the same value as before is written. Figure 24.47 shows the timing in this case.
Page 814: Conflict Between Tpum.tgry Read And Input Capture
RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) 24.10.8 Conflict between TPUm.TGRy Read and Input Capture If the input capture signal is generated in a TGRy read cycle, the data that is read will be the data before input capture transfer.
Page 815: Conflict Between Buffer Register Write And Input Capture
RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) 24.10.10 Conflict between Buffer Register Write and Input Capture If the input capture signal is generated in a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 24.51 shows the timing in this case. Buffer register write by CPU PCLK Input capture signal...
Page 816: Conflict Between Tpum.tcnt Write And Overflow/Underflow
RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) 24.10.12 Conflict between TPUm.TCNT Write and Overflow/Underflow If an overflow/underflow occurs due to increment/decrement in a TCNT write cycle, the TCNT write takes precedence. Figure 24.53 shows the operation timing when there is conflict between TCNT write and overflow. TCNT write by CPU PCLK TCNT write data...
Page 817: Continuous Output Of Compare-Match Pulse Interrupt Signal
RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) 24.10.14 Continuous Output of Compare-Match Pulse Interrupt Signal When TGR is set to 0000h, PCLK/1 is set as the counter clock, and compare match is set as the counter clear source, the TCNT counter remains 0000h and is not updated, and a compare-match pulse interrupt signal is output continuously to form a flat signal level.
Page 818: Continuous Output Of Underflow Pulse Interrupt Signal
RX630 Group 24. 16-Bit Timer Pulse Unit (TPUa) 24.10.16 Continuous Output of Underflow Pulse Interrupt Signal If two external clock signals' same direction edges to be phase counted are generated within two PCLK cycles in phase counting mode 1, with TGR being 0000h, and compare match set as the counter clear source, the TCNT counter remains 0000h and is not updated, and a compare-match pulse interrupt signal and an underflow interrupt signal are output continuously to form a flat signal level.
Page 819: Programmable Pulse Generator (Ppg)
RX630 Group 25. Programmable Pulse Generator (PPG) Programmable Pulse Generator (PPG) The programmable pulse generator (PPG) generates pulse outputs by using the 16-bit timer pulse unit (TPU) and the multi-function timer pulse unit 2 (MTU) as a time base. The RX630 Group has two PPG units, each of which controls up to 16 pulse output pins. The pulse outputs from the PPGs are divided into 4-bit groups that can operate all simultaneously and independently.
Page 820 RX630 Group 25. Programmable Pulse Generator (PPG) Compare match signals NDERH NDERL Control logic PO15 PO14 Pulse output pins, PO13 group 3 PO12 PODRH NDRH PO11 Pulse output pins, PO10 group 2 Pulse output pins, group 1 NDRL PODRL Pulse output pins, group 0 PMR: PPG output mode register...
Page 821 RX630 Group 25. Programmable Pulse Generator (PPG) Table 25.3 lists the pin configuration of the PPG. Table 25.3 Pin Configuration of PPG Unit Pin Name Function PPG0 Output Group 0 pulse output Output Output Output Output Group 1 pulse output Output Output Output...
Page 822: Register Descriptions
RX630 Group 25. Programmable Pulse Generator (PPG) 25.2 Register Descriptions 25.2.1 PPG Trigger Select Register (PTRSLR) Address(es): 0008 81F0h — — — — — — — PTRSL Value after reset:  PPG1.PTRSLR Symbol Bit Name Description PTRSL PPG Trigger Select 0: Selects the set of MTU0 to MTU3 as the trigger channels for PPG1.
Page 823: Next Data Enable Registers H (Nderh) Next Data Enable Registers L (Nderl)
RX630 Group 25. Programmable Pulse Generator (PPG) 25.2.2 Next Data Enable Registers H (NDERH) Next Data Enable Registers L (NDERL) Address(es): 0008 81E8h NDER NDER NDER NDER NDER NDER PPG0.NDERH NDER9 NDER8 Value after reset: Address(es): 0008 81E9h NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 PPG0.NDERL Value after reset: ...
Page 824 RX630 Group 25. Programmable Pulse Generator (PPG) Address(es): 0008 81F8h NDER NDER NDER NDER NDER NDER NDER NDER PPG1.NDERH Value after reset: Address(es): 0008 81F9h NDER NDER NDER NDER NDER NDER NDER NDER PPG1.NDERL Value after reset:  PPG1.NDERH Symbol Bit Name Description NDER 24...
Page 825: Output Data Registers H (Podrh) Output Data Registers L (Podrl)
RX630 Group 25. Programmable Pulse Generator (PPG) 25.2.3 Output Data Registers H (PODRH) Output Data Registers L (PODRL) Address(es): 0008 81EAh POD15 POD14 POD13 POD12 POD11 POD10 POD9 POD8 PPG0.PODRH Value after reset: Address(es): 0008 81EBh PPG0.PODRL POD7 POD6 POD5 POD4 POD3 POD2...
Page 826 RX630 Group 25. Programmable Pulse Generator (PPG) PODi Bit (Output Data Register) (i = 7 to 0) When an output trigger is generated during PPG operation, the values of bits for which data transfer is enabled in the PPG0.NDERL register are transferred from the PPG0.NDRL register to this register. Writing from the CPU is impossible while any of the NDERi (i = 7 to 0) bits in PPG0.NDERL is 1.
Page 827 RX630 Group 25. Programmable Pulse Generator (PPG)  PPG1.PODRL Symbol Bit Name Description POD16 Output Data Register 0: The low level is output on the POi pin. 1: The high level is output on the POi pin. POD17 Output Data Register (i = 23 to 16) POD18 Output Data Register...
Page 828: Next Data Registers H (Ndrh) Next Data Registers L (Ndrl)
RX630 Group 25. Programmable Pulse Generator (PPG) 25.2.4 Next Data Registers H (NDRH) Next Data Registers L (NDRL) Address(es): 0008 81ECh, 0008 81EEh NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 PPG0.NDRH Value after reset: Address(es): 0008 81EDh, 0008 81EFh PPG0.NDRL NDR7 NDR6...
Page 829 RX630 Group 25. Programmable Pulse Generator (PPG) Pulse output group 2: 0008 81EEh Symbol Bit Name Description NDR8 Next Data Register The output trigger specified by PPG0.PCR transfers the values in this register to the corresponding bits in PPG0.PODRH. NDR9 Next Data Register NDR10 Next Data Register...
Page 830 RX630 Group 25. Programmable Pulse Generator (PPG) Address(es): 0008 81FCh, 0008 81FEh PPG1.NDRH NDR31 NDR30 NDR29 NDR28 NDR27 NDR26 NDR25 NDR24 Value after reset: Address(es): 0008 81FDh, 0008 81FFh NDR23 NDR22 NDR21 NDR20 NDR19 NDR18 NDR17 NDR16 PPG1.NDRL Value after reset: ...
Page 831 RX630 Group 25. Programmable Pulse Generator (PPG) Pulse output group 6: 0008 81FEh Symbol Bit Name Description NDR24 Next Data Register The output trigger specified by PPG1.PCR transfers the values in this register to the corresponding bits in PPG1.PODRH. NDR25 Next Data Register NDR26 Next Data Register...
Page 832: Ppg Output Control Register (Pcr)
RX630 Group 25. Programmable Pulse Generator (PPG) 25.2.5 PPG Output Control Register (PCR) Address(es): PPG0.PCR 0008 81E6h, PPG1.PCR 0008 81F6h G3CMS[1:0] G2CMS[1:0] G1CMS[1:0] G0CMS[1:0] Value after reset:  PPG0.PCR Symbol Bit Name Description b1, b0 G0CMS[1:0] Group 0 Compare Match Select b1 b0 0 0: Compare match in MTU0 0 1: Compare match in MTU1...
Page 833 RX630 Group 25. Programmable Pulse Generator (PPG) Symbol Bit Name Description  When the PTRSL bit in PPG1.PTRSLR is set to 0. b5, b4 G2CMS[1:0] Group 6 Compare Match Select b5 b4 0 0: Compare match in MTU0 0 1: Compare match in MTU1 1 0: Compare match in MTU2 1 1: Compare match in MTU3 ...
Page 834: Ppg Output Mode Register (Pmr)
RX630 Group 25. Programmable Pulse Generator (PPG) 25.2.6 PPG Output Mode Register (PMR) Address(es): PPG0.PMR 0008 81E7h, PPG1.PMR 0008 81F7h G3INV G2INV G1INV G0INV G3NOV G2NOV G1NOV G0NOV Value after reset:  PPG0.PMR Symbol Bit Name Description G0NOV Group 0 Non-Overlap 0: Normal operation (Output values updated on compare match A in the selected MTUn)
Page 835 RX630 Group 25. Programmable Pulse Generator (PPG)  PPG1.PMR Symbol Bit Name Description  When the PPG1.PTRSLR.PTRSL bit is 0 G0NOV Group 4 Non-Overlap 0: Normal operation (Output values updated on compare match A in the selected MTUn) 1: Non-overlapping operation (Output values updated on compare match A or B in the selected MTUn) (n = 0 to 3)
Page 836 RX630 Group 25. Programmable Pulse Generator (PPG) Symbol Bit Name Description G0INV Group 4 Output Polarity Change 0: Inverted output 1: Direct output G1INV Group 5 Output Polarity Change 0: Inverted output 1: Direct output G2INV Group 6 Output Polarity Change 0: Inverted output 1: Direct output G3INV...
Page 837: Operation
RX630 Group 25. Programmable Pulse Generator (PPG) 25.3 Operation Figure 25.4 shows a schematic diagram of the PPG. PPG pulse output is enabled when the corresponding bits in PPGn.NDERH and PPGn.NDERL (n = 0, 1) are set to 1 (data transfer is enabled). An initial output value is determined by the initial settings in the corresponding PPGn.PODRH and PPGn.PODRL.
Page 838: Output Timing
RX630 Group 25. Programmable Pulse Generator (PPG) 25.3.1 Output Timing When the selected compare match event occurs while pulse output is enabled, the values in PPGn.NDRH and PPGn.NDRL (n = 0, 1) are transferred to PPGn.PODRH and PPGn.PODRL, respectively, and then output on the corresponding pins.
Page 839: Sample Setup Procedure For Normal Pulse Output
RX630 Group 25. Programmable Pulse Generator (PPG) 25.3.2 Sample Setup Procedure for Normal Pulse Output Figure 25.6 and Figure 25.7 show sample procedures for setting normal pulse output. (1) PPG0 Setting Normal PPG output [1] Set TIOR of the MTU to make TGRA an output compare register Select TGR functions (toggle output).
Page 840 RX630 Group 25. Programmable Pulse Generator (PPG) (2) PPG1 Setting Normal PPG output In the case of MTU, set TIOR to make Select TGR functions TGRA an output compare register (toggle output). In the case of TPU (unit 0), set TIOR to make Set TGRA values TGRA an output compare register (toggle output).
Page 841: Example Of Normal Pulse Output (Example Of Five-Phase Pulse Output)
RX630 Group 25. Programmable Pulse Generator (PPG) 25.3.3 Example of Normal Pulse Output (Example of Five-Phase Pulse Output) Figure 25.8 shows an example in which pulse output from the PPG0 is used for cyclic five-phase pulse output. Compare match TCNT value TCNT TGRA 0000h...
Page 842: Non-Overlapping Pulse Output
RX630 Group 25. Programmable Pulse Generator (PPG) 25.3.4 Non-Overlapping Pulse Output During non-overlapping operation, data transfer from PPGn.NDRH and PPGn.NDRL (n = 0, 1) to PPGn.PODRH and PPGn. PODRL is performed as follows.  On compare match A, the values in PPGn.NDRH and PPGn.NDRL are always transferred to PPGn.PODRH and PPGn.
Page 843: Sample Setup Procedure For Non-Overlapping Pulse Output
RX630 Group 25. Programmable Pulse Generator (PPG) 25.3.5 Sample Setup Procedure for Non-Overlapping Pulse Output Figure 25.11 and Figure 25.12 show sample procedures for setting up non-overlapping pulse outputs. (1) PPG0 Setting Non-overlapping pulse output Select TGR functions Set TGR values MTU setup Set TIOR of the MTU to make TGRA and TGRB output compare Set counting operations...
Page 844 RX630 Group 25. Programmable Pulse Generator (PPG) (2) PPG1 Setting Non-overlapping pulse output Select TGR functions In the case of MTU, set TIOR to make TGRA and TGRB output compare registers (toggle output). In the case of TPU (unit 0), set TIOR to make TGRA and Set TGR values MTU and TGRB output compare registers (toggle output).
Page 845: Example Of Non-Overlapping Pulse Output (Example Of Four-Phase Complementary Non-Overlapping Output)
RX630 Group 25. Programmable Pulse Generator (PPG) 25.3.6 Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non-Overlapping Output) Figure 25.13 shows an example in which pulse output from the PPG0 is used for four-phase complementary non- overlapping pulse output. TCNT value TGRB TCNT...
Page 846 RX630 Group 25. Programmable Pulse Generator (PPG) 1. Set output compare registers of the MTUn.TGRA and MTUn.TGRB (n = 0 to 3) of MTU so that the corresponding compare match signals are the output triggers. Set the trigger period in TGRB and the non-overlap margin in TGRA, and set the counter to be cleared by compare match B.
Page 847: Inverted Pulse Output
RX630 Group 25. Programmable Pulse Generator (PPG) 25.3.7 Inverted Pulse Output When the G3INV, G2INV, G1INV, and G0INV bits in PPG0.PMR are cleared to 0, the values that are the inverse of the respective values in PPG0.PODRH and PPG0.PODRL can be output. Figure 25.14 shows the outputs when the G3INV and G2INV bits are cleared to 0 in addition to the settings in Figure 25.13 .
Page 848: Pulse Output Triggered By Input Capture
RX630 Group 25. Programmable Pulse Generator (PPG) 25.3.8 Pulse Output Triggered by Input Capture Pulse output from the PPG0 can be triggered by the MTU input capture as well as by compare match. When MTUn.TGRA (n = 0 to 3) functions as an input capture register in the MTU channel selected by PPG0.PCR, pulse output is triggered by the input capture signal.
Page 849: Bit Timer (Tmr)
RX630 Group 26. 8-Bit Timer (TMR) 8-Bit Timer (TMR) The RX630 Group has two units (unit 0, unit 1) of an on-chip 8-bit timer (TMR) module that comprise two 8-bit counter channels, totaling four channels. The 8-bit timer module can be used to count external events and also be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with a desired duty cycle using a compare-match signal with two registers.
Page 850 RX630 Group 26. 8-Bit Timer (TMR) Table 26.2 Pin Configuration of TMR Item Unit 0 Unit 1 Counter mode 8 Bits 16 Bits 8 Bits 16 Bits Channel TMR0 TMR1 TMR0 + TMR1 TMR2 TMR3 TMR2 + TMR3 Count clock PCLK/1 PCLK/1 PCLK/1...
Page 851 RX630 Group 26. 8-Bit Timer (TMR) Frequency dividing clock PCLK PCLK/2 PCLK/8 PCLK/32 PCLK/64 PCLK/1024 PCLK/8192 Counter clock 1 Counter clock 0 TMCI0 Clock select TMCI1 TCORA TCORA Compare match A1 Compare match A0 Comparator A0 Comparator A1 To SCI5, SCI12 Overflow 1 TMO0 Overflow 0...
Page 852 RX630 Group 26. 8-Bit Timer (TMR) Frequency dividing clock PCLK PCLK/2 PCLK/8 PCLK/32 PCLK/64 PCLK/1024 PCLK/8192 Counter clock 3 Counter clock 2 TMCI2 Clock select TMCI3 TCORA TCORA Compare match A3 Compare match A2 Comparator A2 Comparator A3 To SCI6 Overflow 3 TCNT TCNT...
Page 853: Register Descriptions
RX630 Group 26. 8-Bit Timer (TMR) Table 26.3 lists the input/output pins of the TMR. Table 26.3 Pin Configuration of TMR Unit Channel Pin Name Description TMR0 TMO0 Output Outputs compare match TMCI0 Input Inputs external clock for counter TMRI0 Input Inputs external reset to counter TMR1...
Page 854: Timer Counter (Tcnt)
RX630 Group 26. 8-Bit Timer (TMR) 26.2.1 Timer Counter (TCNT) Address(es): TMR0.TCNT 0008 8208h, TMR1.TCNT 0008 8209h TMR2.TCNT 0008 8218h, TMR3.TCNT 0008 8219h TMR0.TCNT(TMR2.TCNT) TMR1.TCNT(TMR3.TCNT) Value after reset: TCNT is an 8-bit readable/writable up-counter. TMR0.TCNT and TMR1.TCNT (TMR2.TCNT and TMR3.TCNT) comprise a single 16-bit counter so they can be accessed together by a word transfer instruction.
Page 855: Time Constant Register B (Tcorb)
RX630 Group 26. 8-Bit Timer (TMR) 26.2.3 Time Constant Register B (TCORB) Address(es): TMR0.TCORB 0008 8206h, TMR1.TCORB 0008 8207h TMR2.TCORB 0008 8216h, TMR3.TCORB 0008 8217h TMR0.TCORB(TMR2.TCORB) TMR1.TCORB(TMR3.TCORB) Value after reset: TCORB is an 8-bit readable/writable register. TMR0.TCORB and TMR1.TCORB (TMR2.TCORB and TMR3.TCORB) comprise a single 16-bit register so they can be accessed together by a word transfer instruction.
Page 856: Timer Counter Control Register (Tccr)
RX630 Group 26. 8-Bit Timer (TMR) 26.2.5 Timer Counter Control Register (TCCR) Address(es): TMR0.TCCR 0008 820Ah, TMR1.TCCR 0008 820Bh TMR2.TCCR 0008 821Ah, TMR3.TCCR 0008 821Bh TMRIS — — CSS[1:0] CKS[2:0] Value after reset: Symbol Bit Name Description b2 to b0 CKS[2:0] Clock Select* See Table 26.5.
Page 857 RX630 Group 26. 8-Bit Timer (TMR) Table 26.5 Clock Input to TCNT and Count Condition TCCR Register CSS[1:0] CKS[2:0] Channel Description TMR0 — Clock input prohibited (TMR2) Uses external clock. Counts at rising edge* Uses external clock. Counts at falling edge* Uses external clock.
Page 858: Timer Control/Status Register (Tcsr)
RX630 Group 26. 8-Bit Timer (TMR) 26.2.6 Timer Control/Status Register (TCSR)  TMR0.TCSR, TMR2.TCSR Address(es): TMR0.TCSR 0008 8202h, TMR2.TCSR 0008 8212h — — — ADTE OSB[1:0] OSA[1:0] Value after reset: Symbol Bit Name Description b1, b0 OSA[1:0] Output Select A* b1 b0 0 0: No change when compare match A occurs 0 1: Low is output when compare match A occurs...
Page 859 RX630 Group 26. 8-Bit Timer (TMR)  TMR1.TCSR, TMR3.TCSR Address(es): TMR1.TCSR 0008 8203h, TMR3.TCSR 0008 8213h — — — — OSB[1:0] OSA[1:0] Value after reset: Symbol Bit Name Description b1, b0 OSA[1:0] Output Select A* b1 b0 0 0: No change when compare match A occurs 0 1: Low is output when compare match A occurs 1 0: High is output when compare match A occurs 1 1: Output is inverted when compare match A occurs (toggle output)
Page 860: Operation
RX630 Group 26. 8-Bit Timer (TMR) 26.3 Operation 26.3.1 Pulse Output Figure 26.3 shows an example of the 8-bit timer being used to generate a pulse output with a desired duty cycle. 1. Set the TCR.CCLR[1:0] bits to 01b (cleared by compare match A) so that TCNT is cleared at a compare match of TCORA.
Page 861: Operation Timing
RX630 Group 26. 8-Bit Timer (TMR) TCORB TCORA TCNT TMRIn TMOn (n = 0 to 3) Figure 26.4 Example of Reset Input 26.4 Operation Timing 26.4.1 TCNT Count Timing Figure 26.5 shows the count timing of TCNT for frequency dividing clock input. Figure 26.6 shows the count timing of TCNT for external clock input.
Page 862: Timing Of Interrupt Flag Signal Output On A Compare Match
RX630 Group 26. 8-Bit Timer (TMR) PCLK External clock input pin TCNT input clock TCNT Figure 26.6 Count Timing for External Clock Input (at Both Edges) 26.4.2 Timing of Interrupt Flag Signal Output on a Compare Match A compare match refers to a match between the value of the TCORA or TCORB register and the TCNT, and a compare match interrupt signal is output at this time if the interrupt request is enabled.
Page 863: Timing Of Timer Output At Compare Match
RX630 Group 26. 8-Bit Timer (TMR) 26.4.3 Timing of Timer Output at Compare Match When a compare match signal is generated, the output value specified by the TCSR.OSA[1:0] and OSB[1:0] bits is output on the timer output pin (TMOn). Figure 26.8 shows the timing when the timer output is toggled by the compare match A signal. PCLK Compare match A signal TMOn (n = 0 to 3)
Page 864: Timing Of The External Reset For Tcnt
RX630 Group 26. 8-Bit Timer (TMR) 26.4.5 Timing of the External Reset for TCNT TCNT is cleared at the rising edge or high level of an external reset input, depending on the settings of the TCR.CCLR[1:0] bits. At least two or more PCLK cycles are required from an external reset input to clearing of TCNT. Figure 26.10 and Figure 26.11 show the timing of this operation.
Page 865: Timing Of Interrupt Signal Output On An Overflow
RX630 Group 26. 8-Bit Timer (TMR) 26.4.6 Timing of Interrupt Signal Output on an Overflow When TCNT overflows (changes from FFh to 00h), an overflow interrupt signal is output if this interrupt request is enabled. Figure 26.12 shows the timing of output of the interrupt signal. PCLK TCNT Internal overflow signal...
Page 866: Interrupt Sources
RX630 Group 26. 8-Bit Timer (TMR) 26.6 Interrupt Sources 26.6.1 Interrupt Sources and DTC Activation There are three interrupt sources for TMRn: CMIAn, CMIBn, and OVIn. Their interrupt sources and priorities are listed in Table 26.6 . It is also possible to activate the DTC by means of CMIAn and CMIBn interrupts. The DMAC cannot be activated by the interrupt sources for TMRn.
Page 867: Usage Notes
RX630 Group 26. 8-Bit Timer (TMR) 26.7 Usage Notes 26.7.1 Module-Stop State Setting Operation of the TMR can be disabled or enabled by using the module-stop control registers. The initial setting is for halting of TMR operation. Register access becomes possible after release from the module-stop state. For details, see section 11, Low Power Consumption .
Page 868: Conflict Between Tcnt Write And Increment
RX630 Group 26. 8-Bit Timer (TMR) 26.7.4 Conflict between TCNT Write and Increment Even if a counting-up signal is generated concurrently with CPU write to TCNT, the counting-up is not performed and the write takes priority as shown in Figure 26.14 . TCNT write by CPU PCLK TCNT input clock...
Page 869: Conflict Between Compare Matches A And B
RX630 Group 26. 8-Bit Timer (TMR) 26.7.6 Conflict between Compare Matches A and B If compare match events A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output statuses high for compare match A and compare match B, as listed in Table 26.8 . Table 26.8 Timer Output Priorities Output Setting...
Page 870 RX630 Group 26. 8-Bit Timer (TMR) Table 26.9 Switching of Frequency Dividing Clocks and TCNT Operation (2/2) Timing to Change the TCCR.CKS[2:0] Bits TCNT Clock Operation Switching from low to high* Clock before switching Clock after switching TCNT input clock TCNT TCCR.CKS[2:0] bits changed Switching from high to low*...
Page 871: Clock Source Setting With Cascaded Connection
RX630 Group 26. 8-Bit Timer (TMR) 26.7.8 Clock Source Setting with Cascaded Connection If 16-bit counter mode and compare match count mode are specified at the same time, input clocks for TMR0.TCNT and TMR1.TCNT (TMR2.TCNT and TMR3.TCNT) are not generated, and the counter stops. Do not specify 16-bit counter mode and compare match count mode simultaneously.
Page 872: Compare Match Timer (Cmt)
RX630 Group 27. Compare Match Timer (CMT) Compare Match Timer (CMT) The RX630 Group has two on-chip compare match timer (CMT) units (unit 0 and unit 1) each consisting of a two- channel 16-bit timer (i.e., a total of four channels). The CMT has a 16-bit counter, and can generate interrupts at set intervals.
Page 873: Register Descriptions
RX630 Group 27. Compare Match Timer (CMT) 27.2 Register Descriptions 27.2.1 Compare Match Timer Start Register 0 (CMSTR0) Address(es): 0008 8000h — — — — — — — — — — — — — — STR1 STR0 Value after reset: Symbol Bit Name Description...
Page 874: Compare Match Timer Control Register (Cmcr)
RX630 Group 27. Compare Match Timer (CMT) 27.2.3 Compare Match Timer Control Register (CMCR) Address(es): CMT0.CMCR 0008 8002h, CMT1.CMCR 0008 8008h, CMT2.CMCR 0008 8012h, CMT3.CMCR 0008 8018h — — — — — — — — — CMIE — — — —...
Page 875: Compare Match Timer Counter (Cmcnt)
RX630 Group 27. Compare Match Timer (CMT) 27.2.4 Compare Match Timer Counter (CMCNT) Address(es): CMT0.CMCNT 0008 8004h, CMT1.CMCNT 0008 800Ah, CMT2.CMCNT 0008 8014h, CMT3.CMCNT 0008 801Ah Value after reset: CMCNT is a readable/writable up-counter to generate interrupt requests. When an frequency dividing clock is selected by bits CKS[1:0] in CMCR and the STRn (n = 0 to 3) bit in CMSTRm (m = 0 or 1) is set to 1, CMCNT starts counting up using the selected clock.
Page 876: Operation
RX630 Group 27. Compare Match Timer (CMT) 27.3 Operation 27.3.1 Periodic Count Operation When an frequency dividing clock is selected by bits CKS[1:0] in CMCR and the STRn (n = 0 to 3) bit in CMSTRm (m = 0 or 1) is set to 1, CMCNT starts counting up using the selected clock. When the value in CMCNT and the value in CMCOR match, CMCNT is cleared to 0000h.
Page 877: Interrupts
RX630 Group 27. Compare Match Timer (CMT) 27.4 Interrupts 27.4.1 Interrupt Sources The CMT has channels and each of them to which a different vector address is allocated has a compare match interrupt (CMIn) (n = 0 to 3). When a compare match interrupt occurs, the corresponding interrupt request is output. When the interrupt is used to activate a CPU interrupt, the priority of channels can be changed by the interrupt controller settings.
Page 878: Usage Notes
RX630 Group 27. Compare Match Timer (CMT) 27.5 Usage Notes 27.5.1 Setting the Module-Stop Function The CMT can be enabled or disabled using the module-stop control register. The CMT is disabled by default. The registers can be accessed by canceling the module-stop state. For details, see section 11, Low Power Consumption . 27.5.2 Conflict between Write and Compare-Match Processes of CMCNT When the compare match signal is generated while writing to CMCNT, clearing CMCNT has priority over writing to it.
Page 879: Realtime Clock (Rtca)
RX630 Group 28. Realtime Clock (RTCa) Realtime Clock (RTCa) 28.1 Overview The RTC is capable of counting 100 years from year 00 to year 99. If we place 20 in the hundreds and thousands positions, counting is automatically adjusted for leap years. The source to drive counting of the time counters is selectable as the sub-clock or a main clock.
Page 880 RX630 Group 28. Realtime Clock (RTCa) Internal peripheral bus 2 Realtime clock (RTC) Bus interface To each RTCOUT RCR2 function Time counter 1-Hz output Alarm function Prescaler 128 Hz XCIN RSECAR RMINAR Sub-clock 32.768 kHz R64CNT RSECCNT 128-Hz generation for XCIN oscillator RHRAR RDAYAR...
Page 881: Register Descriptions
RX630 Group 28. Realtime Clock (RTCa) 28.2 Register Descriptions When writing to or reading from RTC registers, do so in accord with section 28.5.5, Points for Caution When Writing to and Reading from Registers . If the value in an RTC register after a reset is given as x (undefined bits) in the list, it is not initialized by a reset or in deep standby mode.
Page 882: Second Counter (Rseccnt)
RX630 Group 28. Realtime Clock (RTCa) 28.2.2 Second Counter (RSECCNT) Address(es): 0008 C402h — SEC10[2:0] SEC1[3:0] Value after reset: x: Undefined Symbol Bit Name Description b3 to b0 SEC1[3:0] Ones Place of Seconds Counts from 0 to 9 once per second. When a carry is generated, 1 is added to the tens place.
Page 883: Hour Counter (Rhrcnt)
RX630 Group 28. Realtime Clock (RTCa) 28.2.4 Hour Counter (RHRCNT) Address(es): 0008 C406h — HR10[1:0] HR1[3:0] Value after reset: x: Undefined Symbol Bit Name Description b3 to b0 HR1[3:0] Ones Place of Hours Counts from 0 to 9 once per hour. When a carry is generated, 1 is added to the tens place.
Page 884: Day-Of-Week Counter (Rwkcnt)
RX630 Group 28. Realtime Clock (RTCa) 28.2.5 Day-of-Week Counter (RWKCNT) Address(es): 0008 C408h — — — — — DAYW[2:0] Value after reset: x: Undefined Symbol Bit Name Description b2 to b0 DAYW[2:0] Day-of-Week Counting 0 0 0: Sunday 0 0 1: Monday 0 1 0: Tuesday 0 1 1: Wednesday 1 0 0: Thursday...
Page 885: Date Counter (Rdaycnt)
RX630 Group 28. Realtime Clock (RTCa) 28.2.6 Date Counter (RDAYCNT) Address(es): 0008 C40Ah — — DATE10[1:0] DATE1[3:0] Value after reset: x: Undefined Symbol Bit Name Description b3 to b0 DATE1[3:0] Ones Place of Days Counts from 0 to 9 once per day. When a carry is generated, 1 is added to the tens place.
Page 886: Year Counter (Ryrcnt)
RX630 Group 28. Realtime Clock (RTCa) 28.2.8 Year Counter (RYRCNT) Address(es): 0008 C40Eh — — — — — — — — YR10[3:0] YR1[3:0] Value after reset: x: Undefined Symbol Bit Name Description b3 to b0 YR1[3:0] Ones Place of Years Counts from 0 to 9 once per year.
Page 887: Minute Alarm Register (Rminar)
RX630 Group 28. Realtime Clock (RTCa) 28.2.10 Minute Alarm Register (RMINAR) Address(es): 0008 C412h MIN10[2:0] MIN1[3:0] Value after reset: x: Undefined Symbol Bit Name Description b3 to b0 MIN1[3:0] 1 Minute Value for the ones place of minutes b6 to b4 MIN10[2:0] 10 Minutes Value for the tens place of minutes...
Page 888: Hour Alarm Register (Rhrar)
RX630 Group 28. Realtime Clock (RTCa) 28.2.11 Hour Alarm Register (RHRAR) Address(es): 0008 C414h HR10[1:0] HR1[3:0] Value after reset: x: Undefined Symbol Bit Name Description b3 to b0 HR1[3:0] 1 Hour Value for the ones place of hours b5, b4 HR10[1:0] 10 Hours Value for the tens place of hours...
Page 889: Day-Of-Week Alarm Register (Rwkar)
RX630 Group 28. Realtime Clock (RTCa) 28.2.12 Day-of-Week Alarm Register (RWKAR) Address(es): 0008 C416h — — — — DAYW[2:0] Value after reset: x: Undefined Symbol Bit Name Description b2 to b0 DAYW[2:0] Day-of-Week Setting 0 0 0: Sunday 0 0 1: Monday 0 1 0: Tuesday 0 1 1: Wednesday 1 0 0: Thursday...
Page 890: Date Alarm Register (Rdayar)
RX630 Group 28. Realtime Clock (RTCa) 28.2.13 Date Alarm Register (RDAYAR) Address(es): 0008 C418h — DATE10[1:0] DATE1[3:0] Value after reset: x: Undefined Symbol Bit Name Description b3 to b0 DATE1[3:0] 1 Day Value for the ones place of days b5, b4 DATE10[1:0] 10 Days Value for the tens place of days...
Page 891: Month Alarm Register (Rmonar)
RX630 Group 28. Realtime Clock (RTCa) 28.2.14 Month Alarm Register (RMONAR) Address(es): 0008 C41Ah — — MON10 MON1[3:0] Value after reset: x: Undefined Symbol Bit Name Description b3 to b0 MON1[3:0] 1 Month Value for the ones place of months MON10 10 Months Value for the tens place of months...
Page 892: Year Alarm Register (Ryrar)
RX630 Group 28. Realtime Clock (RTCa) 28.2.15 Year Alarm Register (RYRAR) Address(es): 0008 C41Ch — — — — — — — — YR10[3:0] YR1[3:0] Value after reset: x: Undefined Symbol Bit Name Description b3 to b0 YR1[3:0] 1 Year Value for the ones place of years b7 to b4 YR10[3:0] 10 Years...
Page 893: Rtc Control Register 1 (Rcr1)
RX630 Group 28. Realtime Clock (RTCa) 28.2.17 RTC Control Register 1 (RCR1) Address(es): 0008 C422h PES[3:0] — Value after reset: x: Undefined Symbol Bit Name Description Alarm Interrupt 0: An alarm interrupt request is disabled Enable 1: An alarm interrupt request is enabled Carry Interrupt 0: A carry interrupt request is disabled.
Page 894: Rtc Control Register 2 (Rcr2)
RX630 Group 28. Realtime Clock (RTCa) 28.2.18 RTC Control Register 2 (RCR2) Address(es): 0008 C424h — HR24 AADJP AADJE RTCOE ADJ30 RESET START Value after reset: x: Undefined Symbol Bit Name Description START Start 0: Year, month, day-of-week, date, hour, minute, second, and 64-Hz counters, and prescaler are stopped.
Page 895 RX630 Group 28. Realtime Clock (RTCa) initialization is completed, the RESET bit is automatically cleared to 0. When 1 is written to the RESET bit, check that the bit is cleared to 0, and then make next settings. ADJ30 Bit (30-Second Adjustment) This bit is for 30-second adjustment.
Page 896: Rtc Control Register 3 (Rcr3)
RX630 Group 28. Realtime Clock (RTCa) 28.2.19 RTC Control Register 3 (RCR3) Address(es): 0008 C426h — — — — — — — RTCEN Value after reset: x: Undefined Symbol Bit Name Description RTCEN Sub-clock Control 0: Sub-clock oscillator is stopped. 1: Sub-clock oscillator is running.
Page 897: Rtc Control Register 4 (Rcr4)
RX630 Group 28. Realtime Clock (RTCa) 28.2.20 RTC Control Register 4 (RCR4) Address(es): 0008 C428h RCKSE — — — — — — — Value after reset: x: Undefined Symbol Bit Name Description RCKSEL Count Source Select 0: The sub-clock is selected. 1: The main clock is selected.
Page 898: Frequency Register H/L (Rfrh/L)
RX630 Group 28. Realtime Clock (RTCa) 28.2.21 Frequency Register H/L (RFRH/L)  RFRH register Address(es): 0008 C42Ah — — — — — — — — — — — — — — — RFC[16] Value after reset: x: Undefined  RFRL register Address(es): 0008 C42Ch RFC[15:0] Value after reset:...
Page 899: Time Error Adjustment Register (Radj)
RX630 Group 28. Realtime Clock (RTCa) Table 28.3 RFRH/L Register Settings by the Main Clock Frequency Main Clock Frequency RFRH/L Register Settings 4 MHz 0000 7A11h 8 MHz 0000 F423h 10 MHz 0001 312Ch 12 MHz 0001 6E35h 16 MHz 0001 E847h 28.2.22 Time Error Adjustment Register (RADJ)
Page 900: Time Capture Control Register Y (Rtccry) (Y = 0 To 2)
RX630 Group 28. Realtime Clock (RTCa) 28.2.23 Time Capture Control Register y (RTCCRy) (y = 0 to 2) Address(es): RTCCR0 0008 C440h, RTCCR1 0008 C442h, RTCCR2 0008 C444h TCEN — TCNF[1:0] — TCST TCCT[1:0] Value after reset: x: Undefined Symbol Bit Name Description b1, b0...
Page 901: Second Capture Register Y (Rseccpy) (Y = 0 To 2)
RX630 Group 28. Realtime Clock (RTCa) TCNF[1:0] Bits (Time Capture Noise Filter Control) These bits control the noise filter of the time capture event input pins (RTCIC0, RTCIC1, and RTCIC2). When the noise filter is on, the count source of 1- and 32-division is selectable. In this case, when the input level on the time capture event input pin matches three times at the set sampling period, the input level is determined.
Page 902: Minute Capture Register Y (Rmincpy) (Y = 0 To 2)
RX630 Group 28. Realtime Clock (RTCa) 28.2.25 Minute Capture Register y (RMINCPy) (y = 0 to 2) Address(es): RMINCP0 0008 C454h, RMINCP1 0008 C464h, RMINCP2 0008 C474h — MIN10[2:0] MIN1[3:0] Value after reset: x: Undefined Symbol Bit Name Description b3 to b0 MIN1[3:0] Ones Place of Minutes Captured Capture value for the ones place of minutes...
Page 903: Date Capture Register Y (Rdaycpy) (Y = 0 To 2)
RX630 Group 28. Realtime Clock (RTCa) 28.2.27 Date Capture Register y (RDAYCPy) (y = 0 to 2) Address(es): RDAYCP0 0008 C45Ah, RDAYCP1 0008 C46Ah, RDAYCP2 0008 C47Ah — — DATE10[1:0] DATE1[3:0] Value after reset: x: Undefined Symbol Bit Name Description b3 to b0 DATE1[3:0] Ones Place of Days Captured Capture value for the ones place of days...
Page 904: Operation
RX630 Group 28. Realtime Clock (RTCa) 28.3 Operation 28.3.1 Outline of Initial Settings of Registers after Power-On After the power is turned on, the initial settings for the clock setting, time-error adjustment, time setting, alarm, interrupt, and time capture control register should be performed. Power on Setting of clock signal distribution and reset by RTC software.
Page 905: Clock Setting Procedure
RX630 Group 28. Realtime Clock (RTCa) 28.3.2 Clock Setting Procedure Figure 28.3 shows how to set the clock. Select the count source Set the RCR4.RCKSEL bit No (main clock) RCKSEL = 0 Yes (sub-clock) Set the RCR3 (sub-clock oscillator) Supply 6 clocks which are selected by the Supply 6 clocks of the count source RCR4.RCKSEL bit Clear the START bit to 0...
Page 906: Setting The Time
RX630 Group 28. Realtime Clock (RTCa) 28.3.3 Setting the Time Figure 28.4 shows how to set the time. Write 0 to the START bit in RCR2 Clear the START bit to 0 START = 0 Wait for the START bit in RCR2 to be cleared to 0 Reset the prescaler and 64CNT Write 1 to the RESET bit in RCR2* Set the RCR3 (sub-clock oscillator)
Page 907: 30-Second Adjustment
RX630 Group 28. Realtime Clock (RTCa) 28.3.4 30-Second Adjustment Figure 28.5 shows how to execute 30-second adjustment. Execute 30-second adjustment while the clock is in operation Clock is in operation (the START bit in RCR2 is 1) Set the ADJ30 bit to 1 Write 1 to the ADJ30 bit in RCR2 ADJ30 = 0 Wait for the ADJ30 bit in RCR2 to be cleared to 0...
Page 908: Reading 64-Hz Counter And Time
RX630 Group 28. Realtime Clock (RTCa) 28.3.5 Reading 64-Hz Counter and Time Figure 28.6 shows how to read the 64-Hz counter and time. (a) To read the time without using interrupt Disable the ICU carry interrupt request Write 0 to the IER07.IEN7 bit of the ICU Enable the RTC carry interrupt request Write 1 to the CIE bit in RCR1 Clear the carry flag...
Page 909: Alarm Function
RX630 Group 28. Realtime Clock (RTCa) 28.3.6 Alarm Function Figure 28.7 shows how to use the alarm function. Check that the count is in operation Clock running (the START bit in RCR2 is 1) Write 0 to the IER0B.IEN4 bit of the ICU to prevent Disable the ICU alarm interrupt request erroneous interrupts Set alarm time...
Page 910: Procedure For Disabling Alarm Interrupt
RX630 Group 28. Realtime Clock (RTCa) 28.3.7 Procedure for Disabling Alarm Interrupt Figure 28.8 shows the procedure for disabling the enabled alarm interrupt request. Enable the alarm interrupt The AIE bit in the RCR1 register has been set to 1 Disable the alarm interrupt request of Write 0 to the IER0B.IEN4 bit of the ICU the ICU...
Page 911: Adjustment By Software
RX630 Group 28. Realtime Clock (RTCa) [Example 2] Sub-clock running at 32.766 kHz Adjustment procedure: At 32.766 kHz, 1 second elapses on counting up by 2 from 32,768. Since adding 20 is suitable if we have 10 seconds, the time can be adjusted by adding 20 to the value counted by the prescaler once every 10 seconds. Register settings: ...
Page 912: Capturing The Time
RX630 Group 28. Realtime Clock (RTCa) 28.3.8.5 Capturing the Time The RTC is capable of storing the month, date, hour, minute and second by detecting an edge of a signal on a time- capture event-input pin. A noise filter can also be used on a time-capture event-input pin. When the level on the pin matches three times at the set sampling period, the noise filter conveys the level to the RTC’s internal circuits, and this level is retained within the RTC until the level on the target pin for sampling has again matched three times.
Page 913: Interrupt Sources
RX630 Group 28. Realtime Clock (RTCa) 28.4 Interrupt Sources There are three interrupt sources in the realtime clock. Table 28.4 lists interrupt sources for the RTC. Table 28.4 RTC Interrupt Sources Name Interrupt Sources Interrupt Status Flag* Alarm interrupt IPR092.IR Periodic interrupt IPR093.IR Carry interrupt...
Page 914: Usage Notes
RX630 Group 28. Realtime Clock (RTCa) (3) Carry interrupt (CUP) This interrupt is generated when a carry to the second counter occurs or a carry to the R64CNT counter occurs during read access to the 64-Hz counter. 64 Hz Interrupt generated by the simultaneous R64CNT occurrence of the selected edge of the signal...
Page 915: Rtcout (1-Hz) Output
RX630 Group 28. Realtime Clock (RTCa) Set the PES[3:0] bits in RCR1 and Set the period and enable interrupt requests write 1 to the PIE bit The period is not guaranteed. Confirm generation of the first periodic interrupt* The first interrupt is generated Interrupts The set period elapses generated...
Page 916: Initialization Procedure When The Realtime Clock Is Not To Be Used
RX630 Group 28. Realtime Clock (RTCa) 28.5.6 Initialization Procedure when the Realtime Clock is not to be Used Registers in the RTC are not initialized by a reset. Accordingly, depending on the initial state, the generation of an unintentional interrupt or operation of the counter may lead to increased power consumption. For products that do not require a realtime clock, initialize the registers by following the initialization procedure shown in Figure 28.14 .
Page 917: Watchdog Timer (Wdta)
RX630 Group 29. Watchdog Timer (WDTA) Watchdog Timer (WDTA) The WDT has a 14-bit down-counter, and can be set up so that the chip is reset by a reset output when counting down from the initial value causes an underflow of the counter. Alternatively, generation of an interrupt request is selectable when the counter underflows.
Page 918 RX630 Group 29. Watchdog Timer (WDTA) Table 29.1 Specifications of WDT (2/2) Item Specifications  Selecting the clock frequency division ratio after refreshing (WDTCR.CKS[3:0] bits) Register start mode  Selecting the time-out period of the watchdog timer (WDTCR.TOPS[1:0] bits) (controlled by the WDT registers) ...
Page 919: Register Descriptions
RX630 Group 29. Watchdog Timer (WDTA) 29.2 Register Descriptions 29.2.1 WDT Refresh Register (WDTRR) Address(es): 0008 8020h Value after reset: Description b7 to b0 The down-counter is refreshed by writing 00h and then writing FFh to this register WDTRR refreshes the down-counter of the WDT. The down-counter of the WDT is refreshed by writing 00h and then writing FFh to WDTRR (refresh operation) within the refresh-permitted period.
Page 920: Wdt Control Register (Wdtcr)
RX630 Group 29. Watchdog Timer (WDTA) 29.2.2 WDT Control Register (WDTCR) Address(es): 0008 8022h — — RPSS[1:0] — — RPES[1:0] CKS[3:0] — — TOPS[1:0] Value after reset: Symbol Bit Name Description b1, b0 TOPS[1:0] Time-Out Period Selection b1 b0 0 0: 1,024 cycles (03FFh) 0 1: 4,096 cycles (0FFFh) 1 0: 8,192 cycles (1FFFh) 1 1: 16,384 cycles (3FFFh)
Page 921 RX630 Group 29. Watchdog Timer (WDTA) Table 29.2 Time-Out Period Settings CKS[3:0] Bits TOPS[1:0] Bits Time-Out Period Clock Division Ratio (Number of Cycles) Cycles of PCLK Clock PCLK/4 1024 4096 4096 16384 8192 32768 16384 65536 PCLK/64 1024 65536 4096 262144 8192 524288...
Page 922 RX630 Group 29. Watchdog Timer (WDTA) Table 29.3 Correspondence between Time-Out Period and Window Start and End Counter Values Time-Out Period Window Start and End Counter Value TOPS[1:0] Bits Cycles Counter Value 100% 1024 03FFh 03FFh 02FFh 01FFh 00FFh 4096 0FFFh 0FFFh 0BFFh...
Page 923: Wdt Status Register (Wdtsr)
RX630 Group 29. Watchdog Timer (WDTA) 29.2.3 WDT Status Register (WDTSR) Address(es): 0008 8024h REFEF UNDFF CNTVAL[13:0] Value after reset: Symbol Bit Name Description b13 to b0 CNTVAL[13:0] Down-Counter Value Value counted by the down-counter UNDFF Underflow Flag 0: No underflow occurred R(/W) 1: Underflow occurred REFEF...
Page 924: Wdt Reset Control Register (Wdtrcr)
RX630 Group 29. Watchdog Timer (WDTA) 29.2.4 WDT Reset Control Register (WDTRCR) Address(es): 0008 8026h RSTIR — — — — — — — Value after reset: Symbol Bit Name Description b6 to b0 — Reserved These bits are read as 0 and cannot be modified. RSTIRQS Reset Interrupt Request Selection 0: Non-maskable interrupt request output is enabled...
Page 925: Operation
RX630 Group 29. Watchdog Timer (WDTA) 29.3 Operation 29.3.1 Count Operation in Each Start Mode Select the WDT start mode by setting the WDT start mode selection bit (OFS0.WDTSTRT) in the option function select register 0. When the OFS0.WDTSTRT bit is 1 (register start mode), the WDT control register (WDTCR) and WDT reset control register (WDTRCR) are enabled, and counting is started by refreshing (writing) the WDT refresh register (WDTRR).
Page 926: Auto-Start Mode
RX630 Group 29. Watchdog Timer (WDTA) Counter value 100% Refresh- prohibited period Refresh- permitted period Refresh- prohibited period RES# pin Control register (WDTCR) (1) Initial value Writing to the Writing to the Writing to the (2) Set value register is invalid. register is valid.
Page 927: Control Over Writing To The Wdtcr And Wdtrcr Registers
RX630 Group 29. Watchdog Timer (WDTA) Figure 29.4 shows an example of operation under the following conditions.  The WDT start mode select (OFS0.WDTSTRT) bit is 0 (auto-start mode)  The reset interrupt request select (OFS0.WDTRSTIRQS) bit is 0 (non-maskable interrupt request output is enabled) ...
Page 928: Refresh Operation
RX630 Group 29. Watchdog Timer (WDTA) RES# pin Peripheral clock (PCLK) Data written to WDTCR xxxxh 00F3h 3300h register WDTCR register write signal (internal signal) Writing disabled WDTCR register 33F3h (initial value) 00F3h 00F3h 33F3h (initial value) Register protection signal WDTCR register is protected (internal signal) (writing-disabled period)
Page 929: Status Flags
RX630 Group 29. Watchdog Timer (WDTA) [Sample refreshing timings]  When the window start position is set to 1FFFh, even if 00h is written to WDTRR before 1FFFh is reached (2002h, for example), refreshing is done if FFh is written to WDTRR after the value of the WDTSR.CNTVAL[13:0] bits has reached 1FFFh.
Page 930: Reset Output
RX630 Group 29. Watchdog Timer (WDTA) 29.3.5 Reset Output When the reset interrupt selection (WDTRCR.RSTIRQS) bit is set to 1 in register start mode or when the WDT reset interrupt request selection (OFS0.WDTRSTIRQS) bit in the option function select register 0 is set to 1 in auto-start mode, a reset signal is output for one-count cycle when an underflow in the down-counter or a refresh error occurs.
Page 931: Correspondence Between Option Function Select Register 0 (Ofs0) And Wdt Registers
RX630 Group 29. Watchdog Timer (WDTA) 29.3.8 Correspondence between Option Function Select Register 0 (OFS0) and WDT Registers Table 29.5 lists the correspondence between the option function select register 0 (OFS0) and the WDT registers (WDT control register (WDTCR) and WDT reset control register (WDTRCR)) regarding control of the down-counter and reset or interrupt request output.
Page 932: Independent Watchdog Timer (Iwdta)
RX630 Group 30. Independent Watchdog Timer (IWDTa) Independent Watchdog Timer (IWDTa) The independent watchdog timer (IWDT) is used independently of the conventional watchdog timer to detect programs entering runaway conditions. The IWDT has a 14-bit down-counter, and can be set up so that the chip is reset by a reset output when counting down from the initial value causes an underflow of the counter.
Page 933 RX630 Group 30. Independent Watchdog Timer (IWDTa) Table 30.1 Specifications of IWDT (2/2) Item Specifications Reading the counter value The down-counter value can be read by the IWDTSR register.  Reset output Output signal (internal signal)  Interrupt request output ...
Page 934: Register Descriptions
RX630 Group 30. Independent Watchdog Timer (IWDTa) 30.2 Register Descriptions 30.2.1 IWDT Refresh Register (IWDTRR) Address(es): 0008 8030h Value after reset: Description b7 to b0 The down-counter is refreshed by writing 00h and then writing FFh to this register IWDTRR refreshes the down-counter of the IWDT. The down-counter of the IWDT is refreshed by writing 00h and then writing FFh to IWDTRR (refresh operation) within the refresh-permitted period.
Page 935: Iwdt Control Register (Iwdtcr)
RX630 Group 30. Independent Watchdog Timer (IWDTa) 30.2.2 IWDT Control Register (IWDTCR) Address(es): 0008 8032h — — RPSS[1:0] — — RPES[1:0] CKS[3:0] — — TOPS[1:0] Value after reset: Symbol Bit Name Description b1, b0 TOPS[1:0] Time-Out Period Selection b1 b0 0 0: 1,024 cycles (03FFh) 0 1: 4,096 cycles (0FFFh) 1 0: 8,192 cycles (1FFFh)
Page 936 RX630 Group 30. Independent Watchdog Timer (IWDTa) Table 30.2 Settings and Time-Out Periods CKS[3:0] Bits TOPS[1:0] Bits Time-Out Period Clock Division Ratio (Number of Cycles) Cycles of IWDTCLK IWDTCLK 1024 1024 4096 4096 8192 8192 16384 16384 IWDTCLK/16 1024 16384 4096 65536 8192...
Page 937 RX630 Group 30. Independent Watchdog Timer (IWDTa) RPES[1:0] Bits (Window End Position Selection) These bits select 75%, 50%, 25% or 0% of the count period for the window end position of the down-counter. The window end position should be a value smaller than the window start position (window start position > window end position).
Page 938: Iwdt Status Register (Iwdtsr)
RX630 Group 30. Independent Watchdog Timer (IWDTa) 30.2.3 IWDT Status Register (IWDTSR) Address(es): 0008 8034h REFEF UNDFF CNTVAL[13:0] Value after reset: Symbol Bit Name Description b13 to b0 CNTVAL[13:0] Down-Counter Value Value counted by the down-counter UNDFF Underflow Flag 0: No underflow occurred R(/W) 1: Underflow occurred REFEF...
Page 939: Iwdt Reset Control Register (Iwdtrcr)
RX630 Group 30. Independent Watchdog Timer (IWDTa) 30.2.4 IWDT Reset Control Register (IWDTRCR) Address(es): 0008 8036h RSTIR — — — — — — — Value after reset: Symbol Bit Name Description b6 to b0 — Reserved These bits are read as 0 and cannot be modified. RSTIRQS Reset Interrupt Request Selection 0: Non-maskable interrupt request output is enabled...
Page 940: Option Function Select Register 0 (Ofs0)
RX630 Group 30. Independent Watchdog Timer (IWDTa) 30.2.6 Option Function Select Register 0 (OFS0) For the OFS0 register, refer to section 30.3.8, Correspondence between Option Function Select Register 0 (OFS0) and IWDT Registers . 30.3 Operation 30.3.1 Count Operation in Each Start Mode Select the IWDT start mode by setting the IWDT start mode selection bit (OFS0.IWDTSTRT) in the option function select register 0.
Page 941: Auto-Start Mode
RX630 Group 30. Independent Watchdog Timer (IWDTa) Counter value 100% Refresh- prohibited period Refresh- permitted period Refresh- prohibited period RES# pin Control register (IWDTCR) (1) Initial value Writing to the Writing to the Writing to the (2) Set value register is invalid. register is invalid.
Page 942: Control Over Writing To The Iwdtcr, Iwdtrcr, And Iwdtcstpr Registers
RX630 Group 30. Independent Watchdog Timer (IWDTa) Figure 30.4 shows an example of operation under the following conditions.  The IWDT start mode selection (OFS0.IWDTSTRT) bit is 0 (auto-start mode)  The reset interrupt request selection (OFS0.IWDTRSTIRQS) bit is 0 (non-maskable interrupt request output is enabled) ...
Page 943: Refresh Operation
RX630 Group 30. Independent Watchdog Timer (IWDTa) RES# pin Peripheral clock (PCLK) Data written to IWDTCR xxxxh 00F3h 3300h register IWDTCR register write signal (internal signal) Writing disabled IWDTCR register 33F3h (initial value) 00F3h 00F3h 33F3h (initial value) Register protection signal IWDTCR register is protected (internal signal) (writing-disabled period)
Page 944 RX630 Group 30. Independent Watchdog Timer (IWDTa) [Sample refreshing timings]  When the window start position is set to 1FFFh, even if 00h is written to IWDTRR before 1FFFh is reached (2002h, for example), refreshing is done if FFh is written to IWDTRR after the value of the IWDTSR.CNTVAL[13:0] bits has reached 1FFFh.
Page 945: Status Flags
RX630 Group 30. Independent Watchdog Timer (IWDTa) Peripheral clock (PCLK) IWDT-dedicated clock (IWDTCLK) Data written to IWDTRR register IWDTRR register write Valid signal (internal signal) IWDTRR register Refresh request signal Refresh signal (after synchronization Refresh request with IWDTCLK) (n)h (n-1)h (n-1)h 0FFFh Counter value...
Page 946: Interrupt Source
RX630 Group 30. Independent Watchdog Timer (IWDTa) 30.3.6 Interrupt Source When the reset interrupt selection (IWDTRCR.RSTIRQS) bit is set to 0 in register start mode or when the IWDT reset interrupt request selection (OFS0.IWDTRSTIRQS) bit in the option function select register 0 is set to 0 in auto-start mode, a non-maskable interrupt (WUNI) signal is output when an underflow in the down-counter or a refresh error occurs.
Page 947: Correspondence Between Option Function Select Register 0 (Ofs0) And Iwdt Registers
RX630 Group 30. Independent Watchdog Timer (IWDTa) Peripheral clock (PCLK) IWDT-dedicated clock (IWDTCLK) Refreshing (after synchronization with IWDTCLK) (n)h (n-1)h 3FFFh Counter value Bits IWDTSR.CNTVAL (n)h (n-1)h (n-1)h [13:0] IWDTSR.CNTVAL[13:0] read signal (internal signal) IWDTSR.CNTVAL xxxxh (n)h (n)h [13:0] read data Figure 30.9 Processing for Reading IWDT Down-Counter Value (IWDTCR.CKS[3:0] = 0010b, IWDTCR.TOPS[1:0] = 11b)
Page 948: Overview
RX630 Group 31. USB 2.0 Function Module (USBa) USB 2.0 Function Module (USBa) 31.1 Overview The RX630 Group provides one port of USB 2.0 function module (USB). The USB is a USB controller which provides capabilities as a USB function controller. The USB supports full-speed transfer when used as the function controller.
Page 949 RX630 Group 31. USB 2.0 Function Module (USBa) Figure 31.1 shows a block diagram of the USB module. LINK core registers registers transceiver USB device controller USB0_DP Interrupt USB0_DM controller FIFO buffer FIFO controller USB protocol controller engine Memory CPU clock controller control USB clock (48 MHz)
Page 950: Register Descriptions
RX630 Group 31. USB 2.0 Function Module (USBa) 31.2 Register Descriptions 31.2.1 System Configuration Control Register (SYSCFG) Address(es): USB0.SYSCFG 000A 0000h — — — — — SCKE — — — — — DPRPU — — — USBE Value after reset: Symbol Bit Name Description...
Page 951: System Configuration Status Register 0 (Syssts0)
RX630 Group 31. USB 2.0 Function Module (USBa) 31.2.2 System Configuration Status Register 0 (SYSSTS0) Address(es): USB0.SYSSTS0 000A 0004h — — — — — — — — — — — — — — LNST[1:0] Value after reset: Symbol Bit Name Description b1, b0 LNST[1:0]...
Page 952: Device State Control Register 0 (Dvstctr0)
RX630 Group 31. USB 2.0 Function Module (USBa) 31.2.3 Device State Control Register 0 (DVSTCTR0) Address(es): USB0.DVSTCTR0 000A 0008h — — — — — — — WKUP — — — — — RHST[2:0] Value after reset: Symbol Bit Name Description b2 to b0 RHST[2:0] USB Bus Reset Status...
Page 953: D0Fifo Port Register (D0Fifo D1Fifo Port Register (D1Fifo)
RX630 Group 31. USB 2.0 Function Module (USBa) 31.2.4 CFIFO Port Register (CFIFO) D0FIFO Port Register (D0FIFO) D1FIFO Port Register (D1FIFO) Address(es): USB0.CFIFO 000A 0014h, USB0.D0FIFO 000A 0018h, USB0.D1FIFO 000A 001Ch FIFOPORT[15:0] Value after reset: Symbol Bit Name Description b15 to b0 FIFOPORT[15:0] FIFO Port The valid bits in a FIFO port register depend on the settings of the...
Page 954 RX630 Group 31. USB 2.0 Function Module (USBa) Table 31.4 Endian Operation in 16-Bit Access CFIFOSEL.BIGEND Bit D0FIFOSEL.BIGEND Bit D1FIFOSEL.BIGEND Bit Bits 15 to 8 Bits 7 to 0 N + 1 data N + 0 data N + 0 data N + 1 data Table 31.5 Endian Operation in 8-Bit Access...
Page 955: D0Fifo Port Select Register (D0Fifosel D1Fifo Port Select Register (D1Fifosel)
RX630 Group 31. USB 2.0 Function Module (USBa) 31.2.5 CFIFO Port Select Register (CFIFOSEL) D0FIFO Port Select Register (D0FIFOSEL) D1FIFO Port Select Register (D1FIFOSEL)  CFIFOSEL Address(es): USB0.CFIFOSEL 000A 0020h BIGEN RCNT — — — — — — ISEL — CURPIPE[3:0] Value after reset: Symbol...
Page 956 RX630 Group 31. USB 2.0 Function Module (USBa) Do not set the same pipe number to the CURPIPE[3:0] bits in CFIFOSEL, D0FIFOSEL, and D1FIFOSEL. Even if an attempt is made to modify the setting of these bits during access to the FIFO buffer, the current access setting is retained until the access is completed.
Page 957 RX630 Group 31. USB 2.0 Function Module (USBa)  D0FIFOSEL, D1FIFOSEL Address(es): USB0.D0FIFOSEL 000A 0028h, USB0.D1FIFOSEL 000A 002Ch BIGEN RCNT REW DCLRM DREQE — — — — — — CURPIPE[3:0] Value after reset: Symbol Bit Name Description b3 to b0 CURPIPE[3:0] FIFO Port Access Pipe Specification b3 b2 b1 b0...
Page 958 RX630 Group 31. USB 2.0 Function Module (USBa) Do not set the same pipe number to the CURPIPE[3:0] bits in CFIFOSEL, D0FIFOSEL, and D1FIFOSEL. Even if an attempt is made to modify the setting of these bits during access to the FIFO buffer, the current access setting is retained until the access is completed.
Page 959: D0Fifo Port Control Register (D0Fifoctr D1Fifo Port Control Register (D1Fifoctr)
RX630 Group 31. USB 2.0 Function Module (USBa) 31.2.6 CFIFO Port Control Register (CFIFOCTR) D0FIFO Port Control Register (D0FIFOCTR) D1FIFO Port Control Register (D1FIFOCTR) Address(es): USB0.CFIFOCTR 000A 0022h, USB0.D0FIFOCTR 000A 002Ah, USB0.D1FIFOCTR 000A 002Eh BVAL BCLR FRDY — — — —...
Page 960 RX630 Group 31. USB 2.0 Function Module (USBa)  A short packet is received and the data is completely read while PIPECFG.BFRE = 1. BCLR Bit (CPU Buffer Clear) The BCLR bit should be set to 1 to clear the FIFO buffer on the CPU side for the selected pipe. When double buffer mode is set for the FIFO buffer assigned to the selected pipe, the USB module clears only one plane of the FIFO buffer even when both planes are read-enabled.
Page 961: Interrupt Enable Register 0 (Intenb0)
RX630 Group 31. USB 2.0 Function Module (USBa) 31.2.7 Interrupt Enable Register 0 (INTENB0) Address(es): USB0.INTENB0 000A 0030h VBSE RSME SOFE DVSE CTRE BEMPE NRDYE BRDYE — — — — — — — — Value after reset: Symbol Bit Name Description b7 to b0 —...
Page 962: Brdy Interrupt Enable Register (Brdyenb)
RX630 Group 31. USB 2.0 Function Module (USBa) 31.2.8 BRDY Interrupt Enable Register (BRDYENB) Address(es): USB0.BRDYENB 000A 0036h PIPE9 PIPE8 PIPE7 PIPE6 PIPE5 PIPE4 PIPE3 PIPE2 PIPE1 PIPE0 — — — — — — BRDYE BRDYE BRDYE BRDYE BRDYE BRDYE BRDYE BRDYE BRDYE...
Page 963: Nrdy Interrupt Enable Register (Nrdyenb)
RX630 Group 31. USB 2.0 Function Module (USBa) 31.2.9 NRDY Interrupt Enable Register (NRDYENB) Address(es): USB0.NRDYENB 000A 0038h PIPE9 PIPE8 PIPE7 PIPE6 PIPE5 PIPE4 PIPE3 PIPE2 PIPE1 PIPE0 — — — — — — NRDYE NRDYE NRDYE NRDYE NRDYE NRDYE NRDYE NRDYE NRDYE...
Page 964: Bemp Interrupt Enable Register (Bempenb)
RX630 Group 31. USB 2.0 Function Module (USBa) 31.2.10 BEMP Interrupt Enable Register (BEMPENB) Address(es): USB0.BEMPENB 000A 003Ah PIPE9 PIPE8 PIPE7 PIPE6 PIPE5 PIPE4 PIPE3 PIPE2 PIPE1 PIPE0 — — — — — — BEMPE BEMPE BEMPE BEMPE BEMPE BEMPE BEMPE BEMPE BEMPE...
Page 965: Sof Output Configuration Register (Sofcfg)
RX630 Group 31. USB 2.0 Function Module (USBa) 31.2.11 SOF Output Configuration Register (SOFCFG) Address(es): USB0.SOFCFG 000A 003Ch BRDY EDGES — — — — — — — — — — — — — — Value after reset: Symbol Bit Name Description b3 to b0 —...
Page 966 RX630 Group 31. USB 2.0 Function Module (USBa) Symbol Bit Name Description b6 to b4 DVSQ[2:0] Device State b6 b5 b4 0 0 0: Powered state 0 0 1: Default state 0 1 0: Address state 0 1 1: Configured state 1 x x: Suspended state x: Don’t care VBSTS...
Page 967 RX630 Group 31. USB 2.0 Function Module (USBa) PIPEnNRDYE bits to which 1 has been set. The NRDY bit cannot be cleared to 0 even if software writes 0 to this bit. BEMP Bit (Buffer Empty Interrupt Status) When the BEMPENB.PIPEnBEMPE bit (n = 0 to 9) for a pipe has been set to 1 and the corresponding BEMPSTS.PIPEnBEMP bit is set to 1, (i.e.
Page 968: Brdy Interrupt Status Register (Brdysts)
RX630 Group 31. USB 2.0 Function Module (USBa) 31.2.13 BRDY Interrupt Status Register (BRDYSTS) Address(es): USB0.BRDYSTS 000A 0046h PIPE9B PIPE8B PIPE7B PIPE6B PIPE5B PIPE4B PIPE3B PIPE2B PIPE1B PIPE0B — — — — — — Value after reset: Symbol Bit Name Description PIPE0BRDY BRDY Interrupt Status for PIPE0*...
Page 969: Nrdy Interrupt Status Register (Nrdysts)
RX630 Group 31. USB 2.0 Function Module (USBa) 31.2.14 NRDY Interrupt Status Register (NRDYSTS) Address(es): USB0.NRDYSTS 000A 0048h PIPE9N PIPE8N PIPE7N PIPE6N PIPE5N PIPE4N PIPE3N PIPE2N PIPE1N PIPE0N — — — — — — Value after reset: Symbol Bit Name Description PIPE0NRDY NRDY Interrupt Status for PIPE0...
Page 970: Bemp Interrupt Status Register (Bempsts)
RX630 Group 31. USB 2.0 Function Module (USBa) 31.2.15 BEMP Interrupt Status Register (BEMPSTS) Address(es): USB0.BEMPSTS 000A 004Ah PIPE9B PIPE8B PIPE7B PIPE6B PIPE5B PIPE4B PIPE3B PIPE2B PIPE1B PIPE0B — — — — — — Value after reset: Symbol Bit Name Description PIPE0BEMP BEMP Interrupt Status for PIPE0...
Page 971: Frame Number Register (Frmnum)
RX630 Group 31. USB 2.0 Function Module (USBa) 31.2.16 Frame Number Register (FRMNUM) Address(es): USB0.FRMNUM 000A 004Ch OVRN CRCE — — — FRNM[10:0] Value after reset: Symbol Bit Name Description b10 to b0 FRNM[10:0] Frame Number These bits indicate a frame number. b13 to b11 —...
Page 972: Device State Changing Register (Dvchgr)
RX630 Group 31. USB 2.0 Function Module (USBa) 31.2.17 Device State Changing Register (DVCHGR) Address(es): USB0.DVCHGR 000A 004Eh DVCH — — — — — — — — — — — — — — — Value after reset: Symbol Bit Name Description b14 to b0 —...
Page 973: Usb Request Type Register (Usbreq)
RX630 Group 31. USB 2.0 Function Module (USBa) STSRECOV[3:0] Bits (Status Recovery) These bits are used in recovery from interruptions to the USB power supply when recovery is to the pre-interruption state of the USB module's internal sequencer. For details, see section 31.3.1.2, Canceling Deep Software Standby Mode by a USB Suspend/Resume Interrupt .
Page 974: Usb Request Index Register (Usbindx)
RX630 Group 31. USB 2.0 Function Module (USBa) 31.2.21 USB Request Index Register (USBINDX) Address(es): USB0.USBINDX 000A 0058h WINDEX[15:0] Value after reset: Symbol Bit Name Description b15 to b0 WINDEX[15:0] Index The USB request wIndex value USBINDX stores setup requests for control transfers. USBINDX is initialized by a USB bus reset.
Page 975: Dcp Maximum Packet Size Register (Dcpmaxp)
RX630 Group 31. USB 2.0 Function Module (USBa) 31.2.23 DCP Maximum Packet Size Register (DCPMAXP) Address(es): USB0.DCPMAXP 000A 005Eh — — — — — — — — — MXPS[6:0] Value after reset: Symbol Bit Name Description b6 to b0 MXPS[6:0] Maximum Packet Size These bits specify the maximum data payload (maximum packet size) for the DCP.
Page 976: Dcp Control Register (Dcpctr)
RX630 Group 31. USB 2.0 Function Module (USBa) 31.2.24 DCP Control Register (DCPCTR) Address(es): USB0.DCPCTR 000A 0060h SQCLR SQSET SQMO BSTS — — — — — — PBUSY — — CCPL PID[1:0] Value after reset: Symbol Bit Name Description b1, b0 PID[1:0] Response PID b1 b0...
Page 977 RX630 Group 31. USB 2.0 Function Module (USBa) Specifically, during control read transfer, the USB module transmits the ACK handshake in response to the OUT transaction from the USB host, and transmits the zero-length packet in response to the IN transaction from the USB host during control write or no-data control transfer.
Page 978: Pipe Window Select Register (Pipesel)
RX630 Group 31. USB 2.0 Function Module (USBa) 31.2.25 Pipe Window Select Register (PIPESEL) Address(es): USB0.PIPESEL 000A 0064h — — — — — — — — — — — — PIPESEL[3:0] Value after reset: Symbol Bit Name Description b3 to b0 PIPESEL[3:0] Pipe Window Select b3 b2 b1 b0...
Page 979: Pipe Configuration Register (Pipecfg)
RX630 Group 31. USB 2.0 Function Module (USBa) 31.2.26 Pipe Configuration Register (PIPECFG) Address(es): USB0.PIPECFG 000A 0068h SHTNA TYPE[1:0] — — — BFRE DBLB — — — EPNUM[3:0] Value after reset: Symbol Bit Name Description b3 to b0 EPNUM[3:0] Endpoint Number* These bits specify the endpoint number for the selected pipe.
Page 980 RX630 Group 31. USB 2.0 Function Module (USBa) EPNUM[3:0] Bits (Endpoint Number) The EPNUM[3:0] bits specify the endpoint number for the selected pipe. Setting 0000b means unused pipe. Do not make the settings such that the combination of the settings of the DIR and EPNUM bits should be the same for two or more pipes (EPNUM[3:0] = 0000b can be set for all of the pipes).
Page 981: Pipe Maximum Packet Size Register (Pipemaxp)
RX630 Group 31. USB 2.0 Function Module (USBa) 31.2.27 Pipe Maximum Packet Size Register (PIPEMAXP) Address(es): USB0.PIPEMAXP 000A 006Ch — — — — — — — MXPS[8:0] Value after reset: 0/1* Note 1. The initial value of the MXPS[8:0] bits is 0000h when no pipe is selected with the PIPESEL bits in PIPESEL and 0040h when a pipe is selected.
Page 982: Pipe Cycle Control Register (Pipeperi)
RX630 Group 31. USB 2.0 Function Module (USBa) 31.2.28 Pipe Cycle Control Register (PIPEPERI) Address(es): USB0.PIPEPERI 000A 006Eh — — — IFIS — — — — — — — — — IITV[2:0] Value after reset: Symbol Bit Name Description b2 to b0 IITV[2:0] Interval Error Detection Interval Specifies the interval error detection timing for the...
Page 983: Pipen Control Registers (Pipenctr) (N = 1 To 9)
RX630 Group 31. USB 2.0 Function Module (USBa) 31.2.29 PIPEn Control Registers (PIPEnCTR) (n = 1 to 9)  PIPEnCTR (n = 1 to 5) Address(es): USB0.PIPE1CTR 000A 0070h, USB0.PIPE2CTR 000A 0072h, USB0.PIPE3CTR 000A 0074h, USB0.PIPE4CTR 000A 0076h, USB0.PIPE5CTR 000A 0078h BSTS INBUF ATREP ACLRM SQCLR SQSET SQMO...
Page 984 RX630 Group 31. USB 2.0 Function Module (USBa)  The USB module sets PID to NAK on recognizing the completion of the transfer when the relevant pipe is in the receiving direction and software has set the PIPECFG.SHTNAK bit for the selected pipe to 1. ...
Page 985 RX630 Group 31. USB 2.0 Function Module (USBa) When the ATREPM bit is set to 1, the USB module responds to the token from the USB host as described below. (1) When the relevant pipe is for bulk IN transfer (PIPECFG.TYPE[1:0] = 01b and PIPECFG.DIR = 1) When ATREPM = 1 and PID = BUF, the USB module transmits a zero-length packet in response to the IN token.
Page 986 RX630 Group 31. USB 2.0 Function Module (USBa) Table 31.6 USB Module Operation as Determined by the Setting of the PID[1:0] Bits (2/2) Transfer Direction Bits PID[1:0] Transfer Type (DIR Bit) Operation of USB Module 10b (STALL) or Bulk or interrupt Operation does not Returns STALL in response to the token from the USB host.
Page 987 RX630 Group 31. USB 2.0 Function Module (USBa)  PIPEnCTR (n = 6 to 9) Address(es): USB0.PIPE6CTR 000A 007Ah, USB0.PIPE7CTR 000A 007Ch, USB0.PIPE8CTR 000A 007Eh, USB0.PIPE9CTR 000A 0080h ACLRM SQCLR SQSET SQMO BSTS — — — — — PBUSY — —...
Page 988 RX630 Group 31. USB 2.0 Function Module (USBa) To specify each response type, set the PID[1:0] bits as follows.  To make a transition from NAK (00b) to STALL, set 10.  To make a transition from BUF (01b) to STALL, set 11. ...
Page 989: Pipen Transaction Counter Enable Registers (Pipentre) (N = 1 To 5)
RX630 Group 31. USB 2.0 Function Module (USBa) 31.2.30 PIPEn Transaction Counter Enable Registers (PIPEnTRE) (n = 1 to 5) Address(es): USB0.PIPE1TRE 000A 0090h, USB0.PIPE2TRE 000A 0094h, USB0.PIPE3TRE 000A 0098h, USB0.PIPE4TRE 000A 009Ch, USB0.PIPE5TRE 000A 00A0h — — — — —...
Page 990: Pipen Transaction Counter Registers (Pipentrn) (N = 1 To 5)
RX630 Group 31. USB 2.0 Function Module (USBa) 31.2.31 PIPEn Transaction Counter Registers (PIPEnTRN) (n = 1 to 5) Address(es): USB0.PIPE1TRN 000A 0092h, USB0.PIPE2TRN 000A 0096h, USB0.PIPE3TRN 000A 009Ah, USB0.PIPE4TRN 000A 009Eh, USB0.PIPE5TRN 000A 00A2h TRNCNT[15:0] Value after reset: Symbol Bit Name Description ...
Page 991: Deep Standby Usb Transceiver Control/Pin Monitor Register (Dpusr0R)
RX630 Group 31. USB 2.0 Function Module (USBa) 31.2.32 Deep Standby USB Transceiver Control/Pin Monitor Register (DPUSR0R) Address(es): 000A 0400h DVBST — — — — — — — — — — — — — Value after reset: FIXPH — — —...
Page 992: Deep Standby Usb Suspend/Resume Interrupt Register (Dpusr1R)
RX630 Group 31. USB 2.0 Function Module (USBa) 31.2.33 Deep Standby USB Suspend/Resume Interrupt Register (DPUSR1R) Address(es): 000A 0404h DVBIN — — — — — — — — — — — — — — DPINT0 Value after reset: DVBSE DPINT —...
Page 993: Operation
RX630 Group 31. USB 2.0 Function Module (USBa) 31.3 Operation 31.3.1 System Control This section describes the register settings that are necessary for initialization of this module and power consumption control. 31.3.1.1 Starting Operation Setting the SYSCFG.USBE bit to 1 after starting the clock supply to the USB module (SYSCFG.SCKE = 1) enables and starts USB module operation.
Page 994 RX630 Group 31. USB 2.0 Function Module (USBa) Figure 31.3 shows an example of peripheral connection of the USB connector (USB0) in the bus-powered state. External Connection RX630 (LSI) System power Each system power B connector supply (3.3 V) supply (3.3 V) Regulator VBUS USB0_VBUS...
Page 995: Canceling Deep Software Standby Mode By A Usb Suspend/Resume Interrupt
RX630 Group 31. USB 2.0 Function Module (USBa) 31.3.1.2 Canceling Deep Software Standby Mode by a USB Suspend/Resume Interrupt Deep software standby mode can be canceled by a USB suspend/resume interrupt. A USB suspend/resume interrupt is detected at the USB resume detecting unit. The USB resume detecting unit controls and monitors the I/O pins for USB0 to detect USB suspend/resume interrupts.
Page 996 RX630 Group 31. USB 2.0 Function Module (USBa) When canceling deep software standby mode using a USB suspend/resume interrupt, set the DPSBYCR.IOKEEP bit to have the outputs of the I/O ports retained. Figure 31.5 shows a flowchart for setting the USB when entering deep software standby mode. Figure 31.6 shows a flowchart for setting the USB when canceling deep software standby mode.
Page 997 RX630 Group 31. USB 2.0 Function Module (USBa) USB suspend/resume interrupt detection Check recovery source and status DPUSR1R Suspended state: USB state is J-state. Suspended state: VBUS state is 1. Wait state for connection: VBUS state is 0. Noise Noise or recovery Re-set interrupts to be detected at Recovery USB resume detecting unit...
Page 998: Interrupt Sources
RX630 Group 31. USB 2.0 Function Module (USBa) 31.3.2 Interrupt Sources Table 31.11 lists the interrupt sources in the USB module. When an interrupt generation condition is satisfied and the interrupt output is enabled using the corresponding interrupt enable register, the USB issues a USB interrupt request to the interrupt controller (ICU) and an USB interrupt will be generated.
Page 999 RX630 Group 31. USB 2.0 Function Module (USBa) Figure 31.7 shows the circuits related to the interrupts in the USB0. USBR USB bus reset detected INTENB0 INTSTS0 VBSE Set_Address detected VBINT RSME Set_Configuration detected USBI RESM SOFE Suspended state detected SOFR Control Write Data Stage DVSE...
Page 1000: Interrupt Descriptions
RX630 Group 31. USB 2.0 Function Module (USBa) Table 31.12 lists the interrupts generated in the USB0. Table 31.12 USB0 Interrupts DMAC Interrupt Name Interrupt Flag Activation Activation Priority D0FIFO DMA transfer request 0 Possible Possible High D1FIFO DMA transfer request 1 Possible Possible USBI...

This manual is also suitable for:

R5f56307ddla R5f56307ddfn R5f56308cdfn R5f56308ddfn R5f56308cdfp R5f56308ddfp ... Show all