Renesas R5F5110JADLF Microcontrollers Manuals

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Renesas R5F5110JADLF User Manual

Renesas R5F5110JADLF User Manual (968 pages)

RX110 Group

Brand: Renesas | Category: Microcontrollers | Size: 12 MB

Table of Contents

Table of Contents
9
Features
32
Overview
33
Outline of Specifications
33
List of Products
37
Block Diagram
40
Pin Functions
41
Pin Assignments
44
Cpu
57
Features
57
Register Set of the CPU
58
General-Purpose Registers (R0 to R15)
59
Control Registers
59
Interrupt Stack Pointer (Isp)/User Stack Pointer (USP)
60
Interrupt Table Register (INTB)
60
Program Counter (PC)
60
Processor Status Word (PSW)
61
Backup PC (BPC)
62
Backup PSW (BPSW)
63
Fast Interrupt Vector Register (FINTV)
63
Register Associated with DSP Instructions
63
Accumulator (ACC)
63
Processor Mode
64
Supervisor Mode
64
User Mode
64
Privileged Instruction
64
Switching between Processor Modes
64
Data Types
65
Endian
65
Switching the Endian
65
Access to I/O Registers
69
Notes on Access to I/O Registers
69
Data Arrangement
69
Data Arrangement in Registers
69
Data Arrangement in Memory
70
Notes on the Allocation of Instruction Codes
70
Vector Table
71
Fixed Vector Table
71
Relocatable Vector Table
72
Operation of Instructions
73
Data Prefetching by the RMPA Instruction and the String-Manipulation Instructions
73
Pipeline
73
Overview
73
Instructions and Pipeline Processing
75
Instructions Converted into Single Micro-Operation and Pipeline Processing
75
Instructions Converted into Multiple Micro-Operations and Pipeline Processing
77
Pipeline Basic Operation
80
Calculation of the Instruction Processing Time
82
Numbers of Cycles for Response to Interrupts
83
Operating Modes
84
Operating Mode Types and Selection
84
Register Descriptions
85
Mode Monitor Register (MDMONR)
85
System Control Register 1 (SYSCR1)
86
Details of Operating Modes
87
Single-Chip Mode
87
Boot Mode
87
Boot Mode (SCI)
87
Transitions of Operating Modes
87
MD Pin Levels and Operating Mode Transitions
87
Address Space
88
I/O Registers
90
I/O Register Addresses (Address Order)
92
Resets
105
Overview
105
Register Descriptions
107
Reset Status Register 0 (RSTSR0)
107
Reset Status Register 1 (RSTSR1)
108
Reset Status Register 2 (RSTSR2)
109
Software Reset Register (SWRR)
110
Operation
111
RES# Pin Reset
111
Power-On Reset
111
Voltage Monitoring 1 Reset and Voltage Monitoring 2 Reset
113
Independent Watchdog Timer Reset
114
Software Reset
115
Determination of Cold/Warm Start
115
Determination of Reset Generation Source
116
Option-Setting Memory
117
Overview
117
Register Descriptions
118
Option Function Select Register 0 (OFS0)
118
Option Function Select Register 1 (OFS1)
120
Endian Select Register (MDE)
122
Usage Note
123
Setting Example of Option-Setting Memory
123
Note on Parallel Use of the Voltage Monitoring 1 Reset and IWDT Reset
123
Voltage Detection Circuit (Lvdaa)
124
Overview
124
Register Descriptions
127
Voltage Monitoring 1 Circuit Control Register 1 (LVD1CR1)
127
Voltage Monitoring 1 Circuit Status Register (LVD1SR)
128
Voltage Monitoring 2 Circuit Control Register 1 (LVD2CR1)
129
Voltage Monitoring 2 Circuit Status Register (LVD2SR)
130
Voltage Monitoring Circuit Control Register (LVCMPCR)
131
Voltage Detection Level Select Register (LVDLVLR)
132
Voltage Monitoring 1 Circuit Control Register 0 (LVD1CR0)
133
Voltage Monitoring 2 Circuit Control Register 0 (LVD2CR0)
134
VCC Input Voltage Monitor
135
Monitoring Vdet1
135
Monitoring Vdet2
135
Interrupt and Reset from Voltage Monitoring 1
136
Interrupt and Reset from Voltage Monitoring 2
138
Clock Generation Circuit
140
Overview
140
Register Descriptions
142
System Clock Control Register (SCKCR)
142
System Clock Control Register 3 (SCKCR3)
144
Main Clock Oscillator Control Register (MOSCCR)
145
Sub-Clock Oscillator Control Register (SOSCCR)
146
Low-Speed On-Chip Oscillator Control Register (LOCOCR)
147
IWDT-Dedicated On-Chip Oscillator Control Register (ILOCOCR)
148
High-Speed On-Chip Oscillator Control Register (HOCOCR)
149
Oscillation Stabilization Flag Register (OSCOVFSR)
150
Oscillation Stop Detection Control Register (OSTDCR)
151
Oscillation Stop Detection Status Register (OSTDSR)
152
Main Clock Oscillator Wait Control Register (MOSCWTCR)
153
High-Speed On-Chip Oscillator Wait Control Register (HOCOWTCR)
154
CLKOUT Output Control Register (CKOCR)
155
Main Clock Oscillator Forced Oscillation Control Register (MOFCR)
156
Main Clock Oscillator
157
Connecting a Crystal
157
External Clock Input
158
Handling of Pins When the Main Clock Is Not Used
158
Notes on the External Clock Input
158
Sub-Clock Oscillator
159
Connecting 32.768-Khz Crystal
159
Handling of Pins When Sub-Clock Is Not Used
159
Oscillation Stop Detection Function
160
Oscillation Stop Detection and Operation after Detection
160
Oscillation Stop Detection Interrupts
161
Internal Clock
162
System Clock
162
Peripheral Module Clock
162
Flashif Clock
162
CAC Clock
162
RTC-Dedicated Clock
162
IWDT-Dedicated Clock
162
Usage Notes
163
Notes on Clock Generation Circuit
163
Notes on Resonator
163
Notes on Board Design
163
Notes on Sub-Clock
164
Clock Frequency Accuracy Measurement Circuit (CAC)
168
Overview
168
Register Descriptions
170
CAC Control Register 0 (CACR0)
170
CAC Control Register 1 (CACR1)
171
CAC Control Register 2 (CACR2)
172
CAC Interrupt Request Enable Register (CAICR)
173
CAC Status Register (CASTR)
174
CAC Upper-Limit Value Setting Register (CAULVR)
175
CAC Lower-Limit Value Setting Register (CALLVR)
175
CAC Counter Buffer Register (CACNTBR)
175
Operation
176
Measuring Clock Frequency
176
Digital Filtering of Signals on the CACREF Pin
177
Interrupt Requests
177
Usage Notes
178
Module Stop Function Setting
178
Low Power Consumption
179
Overview
179
Register Descriptions
183
Standby Control Register (SBYCR)
183
Module Stop Control Register a (MSTPCRA)
184
Module Stop Control Register B (MSTPCRB)
185
Module Stop Control Register C (MSTPCRC)
186
Operating Power Control Register (OPCCR)
187
Sub Operating Power Control Register (SOPCCR)
188
Sleep Mode Return Clock Source Switching Register (RSTCKCR)
193
Reducing Power Consumption by Switching Clock Signals
195
Module Stop Function
195
Function for Lower Operating Power Consumption
195
Setting Operating Power Control Mode
195
Low Power Consumption Modes
197
Sleep Mode
197
Entry to Sleep Mode
197
Exit from Sleep Mode
198
Sleep Mode Return Clock Source Switching Function
198
Deep Sleep Mode
199
Entry to Deep Sleep Mode
199
Exit from Deep Sleep Mode
200
Software Standby Mode
201
Entry to Software Standby Mode
201
Exit from Software Standby Mode
202
Example of Software Standby Mode Application
203
Usage Notes
204
I/O Port States
204
Module Stop State of DTC
204
On-Chip Peripheral Module Interrupts
204
Write Access to MSTPCRA, MSTPCRB, and MSTPCRC
204
Timing of WAIT Instructions
204
Rewrite the Register by DTC in Sleep Mode
204
Register Write Protection Function
205
Register Descriptions
206
Protect Register (PRCR)
206
Exception Handling
207
Exception Events
207
Undefined Instruction Exception
208
Privileged Instruction Exception
208
Reset
208
Non-Maskable Interrupt
208
Interrupts
208
Unconditional Trap
208
Exception Handling Procedure
209
Acceptance of Exception Events
211
Acceptance Timing and Saved PC Value
211
Vector and Site for Saving the Values in the PC and PSW
211
Hardware Processing for Accepting and Returning from Exceptions
212
Hardware Pre-Processing
213
Undefined Instruction Exception
213
Privileged Instruction Exception
213
Reset
213
Non-Maskable Interrupt
213
Interrupt
214
Unconditional Trap
214
Return from Exception Handling Routine
215
Priority of Exception Events
215
Interrupt Controller (Icub)
216
Overview
216
Register Descriptions
218
Interrupt Request Register N (Irn) (N = Interrupt Vector Number)
218
Interrupt Request Enable Register M (Ierm) (M = 02H to 1Fh)
219
Interrupt Source Priority Register N (Iprn) (N = 000 to 249)
220
Fast Interrupt Set Register (FIR)
221
Software Interrupt Activation Register (SWINTR)
222
DTC Activation Enable Register N (Dtcern) (N = Interrupt Vector Number)
223
IRQ Control Register I (Irqcri) (I = 0 to 7)
224
IRQ Pin Digital Filter Enable Register 0 (IRQFLTE0)
225
IRQ Pin Digital Filter Setting Register 0 (IRQFLTC0)
226
Non-Maskable Interrupt Status Register (NMISR)
227
Non-Maskable Interrupt Enable Register (NMIER)
229
Non-Maskable Interrupt Status Clear Register (NMICLR)
230
NMI Pin Interrupt Control Register (NMICR)
231
NMI Pin Digital Filter Enable Register (NMIFLTE)
231
NMI Pin Digital Filter Setting Register (NMIFLTC)
232
Vector Table
233
Interrupt Vector Table
233
Fast Interrupt Vector Table
241
Non-Maskable Interrupt Vector Table
241
Interrupt Operation
241
Detecting Interrupts
241
Operation of Status Flags for Edge-Detected Interrupts
241
Operation of Status Flags for Level-Detected Interrupts
243
Enabling and Disabling Interrupt Sources
244
Selecting Interrupt Request Destinations
244
Determining Priority
245
Multiple Interrupts
245
Fast Interrupt
246
Digital Filter
246
External Pin Interrupts
247
Non-Maskable Interrupt Operation
248
Return from Power-Down States
249
Return from Sleep Mode or Deep Sleep Mode
249
Return from Software Standby Mode
249
Usage Note
249
Note on WAIT Instruction Used with Non-Maskable Interrupt
249
Buses
250
Overview
250
Description of Buses
252
CPU Buses
252
Memory Buses
252
Internal Main Buses
252
Internal Peripheral Buses
253
Write Buffer Function (Internal Peripheral Bus)
254
Parallel Operation
255
Restrictions
255
Register Descriptions
256
Bus Error Status Clear Register (BERCLR)
256
Bus Error Monitoring Enable Register (BEREN)
256
Bus Error Status Register 1 (BERSR1)
257
Bus Error Status Register 2 (BERSR2)
257
Bus Priority Control Register (BUSPRI)
258
Bus Error Monitoring Section
260
Type of Bus Error
260
Illegal Address Access
260
Timeout
260
Operations When a Bus Error Occurs
260
Conditions Leading to Bus Errors
261
Data Transfer Controller (Dtca)
262
Overview
262
Register Descriptions
264
DTC Mode Register a (MRA)
264
DTC Mode Register B (MRB)
265
DTC Transfer Source Register (SAR)
266
DTC Transfer Destination Register (DAR)
266
DTC Transfer Count Register a (CRA)
267
DTC Transfer Count Register B (CRB)
268
DTC Control Register (DTCCR)
268
DTC Vector Base Register (DTCVBR)
269
DTC Address Mode Register (DTCADMOD)
269
DTC Module Start Register (DTCST)
270
DTC Status Register (DTCSTS)
271
Activation Sources
272
Allocating Transfer Information and DTC Vector Table
272
Operation
274
Transfer Information Read Skip Function
276
Transfer Information Write-Back Skip Function
277
Normal Transfer Mode
278
Repeat Transfer Mode
279
Block Transfer Mode
280
Chain Transfer
281
Operation Timing
282
Execution Cycles of the DTC
285
DTC Bus Mastership Release Timing
285
DTC Setting Procedure
286
Examples of DTC Usage
287
Normal Transfer
287
Chain Transfer When the Counter = 0
288
Interrupt Source
289
Low Power Consumption Function
290
Usage Notes
291
Transfer Information Start Address
291
Allocating Transfer Information
291
I/O Ports
292
Overview
292
I/O Port Configuration
294
Register Descriptions
298
Port Direction Register (PDR)
298
Port Output Data Register (PODR)
299
Port Input Data Register (PIDR)
300
Port Mode Register (PMR)
301
Open Drain Control Register 0 (ODR0)
302
Open Drain Control Register 1 (ODR1)
303
Pull-Up Control Register (PCR)
304
Port Switching Register a (PSRA)
305
Port Switching Register B (PSRB)
306
Initialization of the Port Direction Register (PDR)
307
Handling of Unused Pins
309
Multi-Function Pin Controller (MPC)
310
Overview
310
Register Descriptions
315
Write-Protect Register (PWPR)
315
P1N Pin Function Control Register (P1Npfs) (N = 4 to 7)
316
P2N Pin Function Control Register (P2Npfs) (N = 6 to 7)
318
P3N Pin Function Control Register (P3Npfs) (N = 0 to 2)
319
P4N Pin Function Control Register (P4Npfs) (N = 0 to 4, 6)
320
Pan Pin Function Control Register (Panpfs) (N = 0, 1, 3, 4, 6)
321
Pbn Pin Function Control Register (Pbnpfs) (N = 0, 1, 3, 5 to 7)
324
Pcn Pin Function Control Register (Pcnpfs) (N = 2 to 7)
326
Pen Pin Function Control Register (Penpfs) (N = 0 to 7)
328
Phn Pin Function Control Register (Phnpfs) (N = 0 to 3)
330
Pjn Pin Function Control Register (Pjnpfs) (N = 6, 7)
331
Usage Notes
332
Procedure for Specifying I/O Pin Functions
332
Notes on MPC Register Setting
332
Note on Using Analog Functions
333
Multi-Function Timer Pulse Unit 2 (Mtu2B)
334
Overview
334
Register Descriptions
338
Timer Control Register (TCR)
338
Timer Mode Register (TMDR)
341
Timer I/O Control Register (TIOR)
343
Timer Compare Match Clear Register (TCNTCMPCLR)
349
Timer Interrupt Enable Register (TIER)
350
Timer Status Register (TSR)
352
Timer Buffer Operation Transfer Mode Register (TBTM)
353
Timer Input Capture Control Register (TICCR)
354
Timer Counter (TCNT)
354
Timer General Register (TGR)
355
Timer Start Registers (TSTR)
356
Timer Synchronous Registers (TSYR)
357
Noise Filter Control Registers (NFCR)
358
Bus Master Interface
360
Operation
361
Basic Functions
361
Synchronous Operation
367
Buffer Operation
369
Cascaded Operation
373
PWM Modes
378
Phase Counting Mode
382
External Pulse Width Measurement
388
Noise Filter
389
Interrupt Sources
390
Interrupt Sources and Priorities
390
DTC Activation
391
A/D Converter Activation
391
Operation Timing
392
Input/Output Timing
392
Interrupt Signal Timing
396
Usage Notes
399
Module Clock Stop Mode Setting
399
Count Clock Restrictions
399
Notes on Cycle Setting
399
Contention between TCNT Write and Clear Operations
400
Contention between TCNT Write and Increment Operations
400
Contention between TGR Write Operation and Compare Match
401
Contention between Buffer Register Write Operation and Compare Match
401
Contention between Buffer Register Write and TCNT Clear Operations
402
Contention between TGR Read Operation and Input Capture
402
Contention between TGR Write Operation and Input Capture
403
Contention between Buffer Register Write Operation and Input Capture
404
Contention between MTU2.TCNT Write Operation and Overflow/Underflow in Cascaded Operation
405
Contention between Overflow/Underflow and Counter Clearing
406
Contention between TCNT Write Operation and Overflow/Underflow
406
Interrupts During Periods in the Module Stop State
407
Simultaneous Input Capture in MTU1.TCNT and MTU2.TCNT in Cascade Connection
407
Point for Caution Regarding MTU5.TCNT and MTU5.TGR Registers
407
Continuous Output of Interrupt Signal in Response to a Compare Match
408
MTU Output Pin Initialization
409
Operating Modes
409
Operation in Case of Re-Setting Due to Error During Operation
409
Overview of Pin Initialization Procedures and Mode Transitions in Case of Error During Operation
410
Compare Match Timer (CMT)
423
Overview
423
Register Descriptions
424
Compare Match Timer Start Register 0 (CMSTR0)
424
Compare Match Timer Control Register (CMCR)
424
Compare Match Counter (CMCNT)
425
Compare Match Constant Register (CMCOR)
425
Operation
426
Periodic Count Operation
426
CMCNT Count Timing
426
Interrupts
427
Interrupt Sources
427
Timing of Compare Match Interrupt Generation
427
Usage Notes
428
Setting the Module Stop Function
428
Conflict between CMCNT Counter Writing and Compare Match
428
Conflict between CMCNT Counter Writing and Incrementing
428
Realtime Clock (RTCA)
429
Overview
429
Register Descriptions
431
64-Hz Counter (R64CNT)
431
Second Counter (Rseccnt)/Binary Counter 0 (BCNT0)
432
Minute Counter (Rmincnt)/Binary Counter 1 (BCNT1)
433
Hour Counter (Rhrcnt)/Binary Counter 2 (BCNT2)
434
Day-Of-Week Counter (Rwkcnt)/Binary Counter 3 (BCNT3)
435
Date Counter (RDAYCNT)
436
Month Counter (RMONCNT)
437
Year Counter (RYRCNT)
437
Second Alarm Register (Rsecar)/Binary Counter 0 Alarm Register (BCNT0AR)
438
Minute Alarm Register (Rminar)/Binary Counter 1 Alarm Register (BCNT1AR)
439
Hour Alarm Register (Rhrar)/Binary Counter 2 Alarm Register (BCNT2AR)
440
Day-Of-Week Alarm Register (Rwkar)/Binary Counter 3 Alarm Register (BCNT3AR)
441
Date Alarm Register (Rdayar)/Binary Counter 0 Alarm Enable Register (BCNT0AER)
442
Month Alarm Register (Rmonar)/Binary Counter 1 Alarm Enable Register (BCNT1AER)
443
Year Alarm Register (Ryrar)/Binary Counter 2 Alarm Enable Register (BCNT2AER)
444
Year Alarm Enable Register (Ryraren)/Binary Counter 3 Alarm Enable Register (BCNT3AER)
445
RTC Control Register 1 (RCR1)
446
RTC Control Register 2 (RCR2)
447
RTC Control Register 3 (RCR3)
451
Time Error Adjustment Register (RADJ)
452
Operation
453
Outline of Initial Settings of Registers after Power on
453
Clock and Count Mode Setting Procedure
454
Setting the Time
455
30-Second Adjustment
455
Reading 64-Hz Counter and Time
456
Alarm Function
457
Procedure for Disabling Alarm Interrupt
458
Time Error Adjustment Function
458
Automatic Adjustment
458
Adjustment by Software
459
Procedure for Changing the Mode of Adjustment
460
Procedure for Stopping Adjustment
460
Interrupt Sources
461
Usage Notes
463
Register Writing During Counting
463
Use of Periodic Interrupts
463
RTCOUT (1-Hz/64-Hz) Clock Output
463
Transitions to Low Power Consumption Modes after Setting Registers
464
Notes When Writing to and Reading from Registers
464
Changing the Count Mode
464
Initialization Procedure When the Realtime Clock Is Not to be Used
465
Independent Watchdog Timer (Iwdta)
466
Overview
466
Register Descriptions
468
IWDT Refresh Register (IWDTRR)
468
IWDT Control Register (IWDTCR)
469
IWDT Status Register (IWDTSR)
472
IWDT Reset Control Register (IWDTRCR)
473
IWDT Count Stop Control Register (IWDTCSTPR)
474
Option Function Select Register 0 (OFS0)
474
Operation
475
Count Operation in each Start Mode
475
Register Start Mode
475
Auto-Start Mode
477
Control over Writing to the IWDTCR, IWDTRCR, and IWDTCSTPR Registers
479
Refresh Operation
480
Status Flags
482
Reset Output
482
Interrupt Sources
482
Reading the Counter Value
483
Correspondence between Option Function Select Register 0 (OFS0) and IWDT Registers
484
Usage Notes
484
Refresh Operations
484
Clock Divide Ratio Setting
484
Note on Parallel Use of the Voltage Monitoring 1 Reset and IWDT Reset
484
Serial Communications Interface (Scie, Scif)
485
Overview
485
Register Descriptions
491
Receive Shift Register (RSR)
491
Receive Data Register (RDR)
491
Transmit Data Register (TDR)
491
Transmit Shift Register (TSR)
491
Serial Mode Register (SMR)
492
Serial Control Register (SCR)
496
Serial Status Register (SSR)
500
Smart Card Mode Register (SCMR)
505
Bit Rate Register (BRR)
507
Serial Extended Mode Register (SEMR)
514
Noise Filter Setting Register (SNFR)
516
I C Mode Register 1 (SIMR1)
517
I 2 C Mode Register 2 (SIMR2)
518
I 2 C Mode Register 3 (SIMR3)
519
I C Status Register (SISR)
521
SPI Mode Register (SPMR)
522
Extended Serial Module Enable Register (ESMER)
523
Control Register 0 (CR0)
524
Control Register 1 (CR1)
524
Control Register 2 (CR2)
525
Control Register 3 (CR3)
526
Port Control Register (PCR)
526
Interrupt Control Register (ICR)
527
Status Register (STR)
528
Status Clear Register (STCR)
529
Control Field 0 Data Register (CF0DR)
529
Control Field 0 Compare Enable Register (CF0CR)
530
Control Field 0 Receive Data Register (CF0RR)
530
Primary Control Field 1 Data Register (PCF1DR)
530
Secondary Control Field 1 Data Register (SCF1DR)
531
Control Field 1 Compare Enable Register (CF1CR)
531
Control Field 1 Receive Data Register (CF1RR)
531
Timer Control Register (TCR)
532
Timer Mode Register (TMR)
532
Timer Prescaler Register (TPRE)
533
Timer Count Register (TCNT)
533
Operation in Asynchronous Mode
534
Serial Data Transfer Format
535
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
536
Clock
537
CTS and RTS Functions
537
SCI Initialization (Asynchronous Mode)
538
Serial Data Transmission (Asynchronous Mode)
539
Serial Data Reception (Asynchronous Mode)
542
Multi-Processor Communications Function
546
Multi-Processor Serial Data Transmission
547
Multi-Processor Serial Data Reception
548
Operation in Clock Synchronous Mode
551
Clock
551
CTS and RTS Functions
552
SCI Initialization (Clock Synchronous Mode)
553
Serial Data Transmission (Clock Synchronous Mode)
554
Serial Data Reception (Clock Synchronous Mode)
558
Simultaneous Serial Data Transmission and Reception (Clock Synchronous Mode)
561
Operation in Smart Card Interface Mode
562
Sample Connection
562
Data Format (Except in Block Transfer Mode)
563
Block Transfer Mode
564
Receive Data Sampling Timing and Reception Margin
565
SCI Initialization (Smart Card Interface Mode)
566
Serial Data Transmission (Except in Block Transfer Mode)
567
Serial Data Reception (Except in Block Transfer Mode)
570
Clock Output Control
572
Operation in Simple I C Mode
573
Generation of Start, Restart, and Stop Conditions
574
Clock Synchronization
576
SSDA Output Delay
577
SCI Initialization (Simple I 2 C Mode)
578
Operation in Master Transmission (Simple I 2 C Mode)
579
Master Reception (Simple I 2 C Mode)
581
Operation in Simple SPI Mode
583
States of Pins in Master and Slave Modes
584
SS Function in Master Mode
584
SS Function in Slave Mode
584
Relationship between Clock and Transmit/Receive Data
585
SCI Initialization (Simple SPI Mode)
586
Transmission and Reception of Serial Data (Simple SPI Mode)
586
Extended Serial Mode Control Section: Description of Operation
587
Serial Transfer Protocol
587
Transmitting a Start Frame
588
Receiving a Start Frame
591
Priority Interrupt Bit
596
Detection of Bus Collisions
597
Digital Filter for Input on the RXDX12 Pin
598
Bit Rate Measurement
599
Selectable Timing for Sampling Data Received through RXDX12
600
Timer
601
23.10 Noise Cancellation Function
603
23.11 Interrupt Sources
604
Buffer Operations for TXI and RXI Interrupts
604
Interrupts in Asynchronous Mode, Clock Synchronous Mode, and Simple SPI Mode
604
Interrupts in Smart Card Interface Mode
605
Interrupts in Simple I C Mode
606
Interrupt Requests from the Extended Serial Mode Control Section
607
23.12 Usage Notes
608
Setting the Module Stop Function
608
Break Detection and Processing
608
Mark State and Generating Breaks
608
Receive Error Flags and Transmit Operations (Clock Synchronous Mode and Simple SPI Mode)
608
Writing Data to the TDR Register
608
Restrictions on Clock Synchronous Transmission (Clock Synchronous Mode and Simple SPI Mode)
609
Restrictions on Using DTC
610
Notes on Starting Transfer
610
SCI Operations During Low Power Consumption State
610
External Clock Input in Clock Synchronous Mode and Simple SPI Mode
613
Limitations on Simple SPI Mode
614
Limitation 1 on Usage of the Extended Serial Mode Control Section
614
Limitation 2 on Usage of the Extended Serial Mode Control Section
615
Note on Transmit Enable Bit (te Bit)
615
Note on Stopping Reception When the RTS Function Is in Use
616
I C-Bus Interface (RIIC)
617
Overview
617
Register Descriptions
620
I 2 C-Bus Control Register 1 (ICCR1)
620
I 2 C-Bus Control Register 2 (ICCR2)
622
I 2 C-Bus Mode Register 1 (ICMR1)
626
I 2 C-Bus Mode Register 2 (ICMR2)
627
I 2 C-Bus Mode Register 3 (ICMR3)
629
I 2 C-Bus Function Enable Register (ICFER)
631
I 2 C-Bus Status Enable Register (ICSER)
633
I 2 C-Bus Interrupt Enable Register (ICIER)
635
I 2 C-Bus Status Register 1 (ICSR1)
637
I 2 C-Bus Status Register 2 (ICSR2)
640
Slave Address Register Ly (Sarly) (y = 0 to 2)
643
Slave Address Register Uy (Saruy) (y = 0 to 2)
644
I 2 C-Bus Bit Rate Low-Level Register (ICBRL)
645
I 2 C-Bus Bit Rate High-Level Register (ICBRH)
646
I 2 C-Bus Transmit Data Register (ICDRT)
648
I 2 C-Bus Receive Data Register (ICDRR)
648
I 2 C-Bus Shift Register (ICDRS)
648
Timeout Internal Counter (TMOCNTL/TMOCNTU)
649
Operation
650
Communication Data Format
650
Initial Settings
651
Master Transmit Operation
652
Master Receive Operation
655
Slave Transmit Operation
661
Slave Receive Operation
664
SCL Synchronization Circuit
667
SDA Output Delay Function
668
Digital Noise Filter Circuit
669
Address Match Detection
670
Slave-Address Match Detection
670
Detection of the General Call Address
672
Device-ID Address Detection
673
Host Address Detection
675
Automatic Low-Hold Function for SCL
676
Function to Prevent Wrong Transmission of Transmit Data
676
NACK Reception Transfer Suspension Function
677
Function to Prevent Failure to Receive Data
677
Arbitration-Lost Detection Functions
679
Master Arbitration-Lost Detection (MALE Bit)
679
Function to Detect Loss of Arbitration During NACK Transmission (NALE Bit)
681
Slave Arbitration-Lost Detection (SALE Bit)
682
24.10 Start Condition/Restart Condition/Stop Condition Issuing Function
683
Issuing a Start Condition
683
Issuing a Restart Condition
683
Issuing a Stop Condition
684
24.11 Bus Hanging
685
Timeout Function
685
Extra SCL Clock Cycle Output Function
687
RIIC Reset and Internal Reset
688
24.12 Smbus Operation
689
Smbus Timeout Measurement
689
Packet Error Code (PEC)
690
Smbus Host Notification Protocol (Notify ARP Master Command)
690
24.13 Interrupt Sources
691
Buffer Operation for TXI and RXI Interrupts
691
24.14 Resets and Register and Function States When Issuing each Condition
692
24.15 Usage Notes
693
Setting Module Stop Function
693
Notes on Starting Transfer
693
Serial Peripheral Interface (RSPI)
694
Overview
694
Register Descriptions
698
RSPI Control Register (SPCR)
698
RSPI Slave Select Polarity Register (SSLP)
700
RSPI Pin Control Register (SPPCR)
701
RSPI Status Register (SPSR)
702
RSPI Data Register (SPDR)
704
RSPI Sequence Control Register (SPSCR)
707
RSPI Sequence Status Register (SPSSR)
708
RSPI Bit Rate Register (SPBR)
709
RSPI Data Control Register (SPDCR)
710
RSPI Clock Delay Register (SPCKD)
712
RSPI Slave Select Negation Delay Register (SSLND)
713
RSPI Next-Access Delay Register (SPND)
714
RSPI Control Register 2 (SPCR2)
715
RSPI Command Registers 0 to 7 (SPCMD0 to SPCMD7)
716
Operation
719
Overview of RSPI Operations
719
Controlling RSPI Pins
720
RSPI System Configuration Examples
721
Single Master/Single Slave (with this MCU Acting as Master)
721
Single Master/Single Slave (with this MCU Acting as Slave)
722
Single Master/Multi-Slave (with this MCU Acting as Master)
723
Single Master/Multi-Slave (with this MCU Acting as Slave)
724
Multi-Master/Multi-Slave (with this MCU Acting as Master)
725
Master (Clock Synchronous Operation)/Slave (Clock Synchronous Operation) (with this MCU Acting as Master)
726
Master (Clock Synchronous Operation)/Slave (Clock Synchronous Operation) (with this MCU Acting as Slave)
726
Data Format
727
When Parity Is Disabled (SPCR2.SPPE = 0)
728
When Parity Is Enabled (SPCR2.SPPE = 1)
732
Transfer Format
736
Cpha = 0
736
Cpha = 1
737
Communications Operating Mode
738
Full-Duplex Synchronous Serial Communications (SPCR.TXMD = 0)
738
Transmit Operations Only (SPCR.TXMD = 1)
739
Transmit Buffer Empty/Receive Buffer Full Interrupts
740
Error Detection
742
Overrun Error
743
Parity Error
744
Mode Fault Error
745
Initializing RSPI
746
Initialization by Clearing the SPE Bit
746
System Reset
746
SPI Operation
747
Master Mode Operation
747
Slave Mode Operation
757
Clock Synchronous Operation
761
Master Mode Operation
761
Slave Mode Operation
765
Loopback Mode
767
Self-Diagnosis of Parity Bit Function
768
Interrupt Sources
769
Usage Notes
770
Setting Module Stop Function
770
Note on Low Power Consumption Functions
770
Notes on Starting Transfer
770
Notes on the SPRF and SPTEF Flags
770
CRC Calculator (CRC)
771
Overview
771
Register Descriptions
772
CRC Control Register (CRCCR)
772
CRC Data Input Register (CRCDIR)
772
CRC Data Output Register (CRCDOR)
773
Operation
774
Usage Notes
777
Module Stop Function Setting
777
Note on Transmission
777
Overview
778
Register Descriptions
782
A/D Data Registers y (Addry) (y = 0 to 4, 6, 8 to 15)
782
A/D Data Duplication Register (ADDBLDR)
784
A/D Temperature Sensor Data Register (ADTSDR)
785
A/D Internal Reference Voltage Data Register (ADOCDR)
786
A/D Control Register (ADCSR)
787
A/D Channel Select Register a (ADANSA)
790
A/D Channel Select Register B (ADANSB)
791
A/D-Converted Value Addition Mode Select Register (ADADS)
792
A/D-Converted Value Addition Count Select Register (ADADC)
793
A/D Control Extended Register (ADCER)
794
A/D Start Trigger Select Register (ADSTRGR)
795
A/D Converted Extended Input Control Register (ADEXICR)
797
A/D Sampling State Register N (Adsstrn) (N = 0 to 4, 6, L, T, O)
798
Operation
799
Scanning Operation
799
Single Scan Mode
800
Basic Operation
800
A/D Conversion When Temperature Sensor Output Is Selected
801
A/D Conversion When Internal Reference Voltage Is Selected
802
A/D Conversion in Double Trigger Mode
803
Continuous Scan Mode
804
Basic Operation
804
Group Scan Mode
805
Basic Operation
805
A/D Conversion in Double Trigger Mode
806
Notes on Using Software Trigger
807
Analog Input Sampling and Scan Conversion Time
808
Usage Example of Automatic Register Clearing Function
809
A/D-Converted Value Addition Function
809
Starting A/D Conversion with an Asynchronous Trigger
810
Starting A/D Conversion with Synchronous Trigger from Peripheral Modules
810
Interrupt Sources
810
Interrupt Request on Completion of each Scanning Conversion
810
A/D Conversion Accuracy Definitions
811
Usage Notes
812
Notes on Reading Data Registers
812
Notes on Stopping A/D Conversion
812
A/D Conversion Restarting Timing and Termination Timing
812
Notes on Scan End Interrupt Handling
812
Module Stop Function Setting
812
Notes on Entering Low Power Consumption States
812
Notes on Releasing Software Standby Mode
812
Allowable Impedance of Signal Source
813
Influence on Absolute Accuracy
815
Voltage Range of Analog Power Supply Pins
815
Notes on Board Design
815
Notes on Noise Prevention
816
Port Setting When 12-Bit A/D Converter Inputs Are Used
816
Sequence of Powering on AVCC0 and VCC
816
Temperature Sensor (TEMPSA)
817
Overview
817
Register Descriptions
818
Temperature Sensor Calibration Data Register (TSCDRH, TSCDRL)
818
Using the Temperature Sensor
819
Before Using the Temperature Sensor
819
Setting the 12-Bit A/D Converter
821
A/D Conversion Result of Temperature Sensor Output
821
Data Operation Circuit (DOC)
822
Overview
822
Register Descriptions
823
DOC Control Register (DOCR)
823
DOC Data Input Register (DODIR)
824
DOC Data Setting Register (DODSR)
824
Operation
825
Data Comparison Mode
825
Data Addition Mode
826
Data Subtraction Mode
827
Interrupt Requests
827
Usage Note
827
Module Stop Function Setting
827
Ram
828
Overview
828
Operation
828
Low Power Consumption Function
828
Flash Memory
829
Overview
829
ROM Area and Block Configuration
830
Register Descriptions
832
Flash P/E Mode Entry Register (FENTRYR)
832
Protection Unlock Register (FPR)
833
Protection Unlock Status Register (FPSR)
833
Flash P/E Mode Control Register (FPMCR)
834
Flash Initial Setting Register (FISR)
835
Flash Reset Register (FRESETR)
837
Flash Area Select Register (FASR)
837
Flash Control Register (FCR)
838
Flash Extra Area Control Register (FEXCR)
839
Flash Processing Start Address Register H (FSARH)
841
Flash Processing Start Address Register L (FSARL)
841
Flash Processing End Address Register H (FEARH)
842
Flash Processing End Address Register L (FEARL)
842
Flash Read Buffer Register H (FRBH)
842
Flash Read Buffer Register L (FRBL)
843
Flash Write Buffer Register H (FWBH)
843
Flash Write Buffer Register L (FWBL)
843
Flash Status Register 0 (FSTATR0)
844
Flash Status Register 1 (FSTATR1)
846
Flash Error Address Monitor Register H (FEAMH)
847
Flash Error Address Monitor Register L (FEAML)
847
Flash Start-Up Setting Monitor Register (FSCMR)
848
Flash Access Window Start Address Monitor Register (FAWSMR)
848
Flash Access Window End Address Monitor Register (FAWEMR)
849
Unique ID Register N (Uidrn) (N = 0 to 31)
849
Start-Up Program Protection
850
Area Protection
851
Programming and Erasure
852
Sequencer Modes
852
Read Mode
852
P/E Mode
852
Mode Transitions
853
Transition from Read Mode to P/E Mode
853
Transition from P/E Mode to Read Mode
854
Software Commands
855
Software Command Usage
856
Program
856
Block Erase
857
Blank Check
858
Start-Up Area Information Program/Access Window Information Program
859
Unique ID Read
860
Forced Stop of Software Commands
861

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