Table of Contents
Advertisement
Tbeory
and Sehematics--Model
5\5*A'
Table
8-1.
Mnemonics
(Cont'd)
LEXBYTE
toltJ
El(EcutED
BYTE. If this signal is
lor
a
executed
byte will be sent to
tjhe
logic
anaLyzer
during the current
cYcle.
Lr$cIEX
toI^J
NEXT
EIGCUTED.
During the next
state
an
executed
byte
will
be
sent to the logic analyzet if this
signal
is
low.
rQSglfl(/tAtEMN
to1l1
QIJETE
STATUS
g/tow
ADDRESS
LATSH
ENABtE.
This
is
the
HQS0I'D(/HAIEMN
signal
inverted-
LS0ID(/LDENMN
tOW STATUS
O MN(/IOW DATA ENABTE
MIN. This
signal
is
SO
if
the
CPU
is in
max
model
it is
a
data
enable
bus
control
line if
the
CPU
is in
min
mode'
LS1Ifi(/HUTMN tol{
STATUS
L/
HIGH
DATA TRANSMIT.
This is
status
line S1 if the
CPU
is in
maximum
mode;
it is
data
transmit (high)/receive(fow)
direction control line
if
the
CPU
is in
min
mode.
LS2M(/HMEMMN
LOW
STATUS
2/
HTGIL
MEMORY.
This
is status Line
52
if
the
CPU
is in
max
model
it is
memory
(hiSh/IO
low)
if
the
CPU
is
an 8085
in
minimum
mode.
Tf
the
CPU
is
an 8088
in
minimum mode
the signal is high for
IO
and
low
for
memory.
tBO88
LOW
8088. If this line is low the
CPU being
monitored
is an 8088; if it is
high the
CPU
being
monitored
is
an
8086.
PTDBUSADDR
POSITI\IE IOAD
BUS
$DRESS. The
positive
edge of
this
signal
loads
the
BUS CYCLE
ADDRESS
LATCIIES.
PI,NLDQ
POSITI\IE
IINTOAD
QIIEIIE.
Ithe positive
edge
of this
signat
enables
the
INSTRUCTION
QUEIiE
to unload
a
byte.
8-10
Advertisement
Table of Contents
