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Theory and Schematics__Moaef
5h553A
8-u'
rn the
ExEctrIED
mode, bus operations that
fetch
g0g6/g0gg
instructions from
memory
are not immediitely sent to
the
loglc
anaayzer.
fnstead,
the instructions are input into tfre Instruction eueue
(UTB,U8B).
this
queue
duplicates
the
function
of the instrrrction
queue
that is inside
the
cPU'
l'lhen
the
queue
status lines from the cpu indicate that
it
is
executing
a byte from its
queue
the
corresponding
byte is pulred
from
the
rnstruction
Queue
on
the
interface
module
ani
sent
to the
artaryzer
along with
an address from the Address counter. The controlrer is
compretely
responsible for controlling the
operation
of the rnstruction
QSreue
and
the
Address
counter.
The controller identifies which
bus operations
are
cpu
instr,ction
fetches
a'd enters
them
into the rnstrtrction -Qu.,r". rt
also
monitors the
cPU
operation
and sends
instructions to the rogic
analyzer
as
they are executed.
irlhen
the
CPU
executes
a
program
transfer instructiono
the
Controller clears the Instruction
Queue
and
loads a
new
value
into
the
Address
Counter.
8-L2. I'Itrile in the
EXECIJTED
mod.e
bus operations that are not
cpu
instrrrction fetches will
immediately
be sent to the logic ana;;yzer.
This
includes
all
bus operations
that
are
performed
by a
"op"o"i""or that
may
be
sharing the bus with the
8086/8088. orre
result of this
instruction
dequeueing
is that for instrtrctions that
cause
a
bus
operation, such as
a
memory
or I/O read or write,
the
executed
instruction will be
immediatel-y
followed by the resulting bus operation. Priority
is
always
given
to
executed
instructions
if
an
instrrrction
and
a
bus
op"""tion
need
to
be sent
to
the logic
arraLyzet
at the
same
time. If a conflict
does occur
the status
will_
indicate that a
bus operation has been
lost.
This conflict
can occur
onry
with a
coprocessor and even
then
it is a
rare
event.
8-13.
There
are several
resources
that
are available
to
tne 6\6zos
user
in
the
forrn of a
wire
wrap area
at
the
upper
right
corner
of the
interface
module.
8-14. First,
there are
three signals
l-abeled STM,
AcK, and HLT. Ttre
STl,l
and HLT lines are driven by the
J-ogic
arral:yzer
through
the
preproeessor.
These lines are available to the user to assert interrupt
requests,
halt
requests,
or other similar
operations
in the
system und,er
test.
The
ACK
line is
an
acknowledge
for the
STM l-ine
when the
Preprocessor
has
been
programmed
in the
Preprocessor Specifiea,tion
to
operate
in the
handshake
mode
of operation. For further information refer to the
6t+55oe
c"""""r
Furpose Preprocessor Operation
Manual-.
STM, ACK,
and
HALT
are all
active
low signals.
STt{
and
HLT
are
open
collector
outputs
from
the
preprocessor.
8-f5.
Second,
there are
two
pins labeled
CK5
and CKT. These are
the
upper two
of
the eight analysis clock channels.
They can be used
as
additional
clock
or
cLock
qualifier
1ines.
8-f.6. Third, the
upper
six
data
channels
of
Data
Pod
3
are available in
the
wirewrap
area.
These analysis
channels
might be used
to
monitor control
signals
or
input/output
ports in the target
system.
8-3
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