Table of Contents
Advertisement
Theory and Schematics__Moaef
5lld53e
8-26,
Status Generator. (Se:rrice
Sheet
1,
U1C)
8-27'.
The pur?ose
of the
status
generator
is to
generate
status about the state
that ls
being
sent
to the analyzer.
some
status is varid
r^rith address and the
rest with
data
at the
end
of the cycle. rn addition, the kind of
status
that is available is different for
min and
max modes
of the cpLI.
There
are
arso
some
differences
between
the
8oB5
aryi the Bo8B. I1r"
status
of
an
executed
byte
has
to
be
generated
entirely
since
it is
not a
bus
cycle.
some
of
the status
is
generated
by the Contro1ler.
8-28. rnstruction
Queue
and
Address
counter. (service sheet z,
uTB,ugB,
and
ul+c,
u8A,U9B,U1oA,Ul-oB)
8*29'
The
rnstruction
Queue
loeated on
the interface
modure
duplicates
the
primary function of the
queue
that is in
the CpU.
It is
made
of
two
t6
word
X
5
bit
FrFo's (functioning
as
t5
word
x
l+
tit Frro's).
141ren
the
cpu does
a
code
fetch
cycle
the instnrctions are
entered.
into the
queue
instead
of
being
sent
to the analyzer.
I{tren
the
queue
status from the cpu
indicates
that it
has executed
a
first
byte or next byte the
corresponding
uvtl i"
purled
from the
interface
module
queue. rt is
matched
up
with its uaa*.",
from
the
address
counter and
sent to the analryzer. I,,lhen the cpu indicates through its
queue
status that it is
doing
a
program
transfer
both
queues
are
emptied
of
any
prefetched
but not
executed
instructions.
8-30'
The
addresses
of the
bytes
that are in
both
queues
are
sequenti.ar.
The
cPU
begins
fetching
code from
some
address
and continue"
fetching
from
sequential
addresses
until a
program
transfer is executed. Ttre
cpu
then
empties-
its
queue and
begins
fetching
code from
a
new
address. After
each
queue
flush the
address
of the
next
code fetch is
loaded
into the
address
counter' As elch
executed
byte is pulled from the
queue
the counter is
ineremented.
Like the
CPU's address
counter the
address counter
on
the
rnterface card
is
20
bits wide.
The
counter
is
made
up
of five L-bit
"orrrt."=
that are
synchronous,
can
be
parallel
loaded,
and have
tri-state
outputs.
8-3f. Bus Cycle Address
Latch
lJ3C,[J9C,U10C
and
U8C,U5C)
and Data Buffer.
(Serviee Sheet
Z,
8-32,
The
bus cycle
address
latch is
made
up of
u3c,u9c,and
uloc.
Ttrey
get their
information from the
cPu
bus latches on the rising
edge or
PLDBUS$DR. one
of the
extra
bits of the
address
latch is used to
capture
BHE
for the
Status Generator.
Ttre
data
buffers
alIor,r
data
to get to the
1ogic
analyzer
when
a bus cycle is being
sent.
8-5
Advertisement
Table of Contents
