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ADo-L5
AL6-]lg/s3-5
CLK
LBHE/S7
MN/LlD(
QSo/
(Ar.E)
QSL/(rrNrA)
rso/
(rDElr)
ffi1(D{r/LR)
LS2
(M/Lro)
ADDRESS/DATA
0-15.
This
is the
multiplexed
address
data bus from
the
8085/8088 system under
test.
ADDBESS 1-5-19ISTATUS
3-6. This is a
multiplexed
address/status bus from
the
system
under
test.
ct0cK. lhis is
the
cpu
crock
from the
system
under
test.
tOW
BITE
HIGH ENABLE/STAIUS
T.
This
is
a multiplexed
eontrol/status
signal. from
the
system
under
test.
MTNTMITM/IOfl
MA)(rMUM. The
cpu under
test is in
minimum
mode
if this signal is high; it is in
maximum
mode
if
this
signal
is
low.
qUEITE
SfAfUS
LINE/ADDRESS LATCH
ENABLE.
Ihis
signal
is a
queue
status line if the
CpU
under
test is
in
maximum
model
it is
an
address
1atch enable if
the
CPU
is in
minimum mode.
QI'ETIE
STATUS
LIHE/IOI'
I}ITERRI'PT ACIffOWLEDGE.
T}TiS
signal is a
queue
status
line if
the
CpU
under
test
is in
maximum
mode;
it
is an internrpt
acknowledge
data strobe
if
the
CPU
is in
minimum
mode.
tolt
STATUS OILOW DATA
ENABLE.
Ihis signal is
a
status line if
the
cPU
under
test is in
maximum
mod.e;
it is a
data enable bus
control line if
the
CpU is
in
minimum
mode.
LOW
STArUS
1(DArA
TRAI\ISMIT/LOI.,
RECEIIE).
This
signal
is a
status
line if
the
CPU
under
test is in
maximum
mode;
it is
a data transmit/reeeive
direction
eontrol
line if
the
CPU
is in
minimum mode.
row
sTAflrs
2(MEMORY/INPL'TOU?PL'T).
This signal
is
a
low
status 2
line if
the
CPU
under test is
in
maximum
model
it is
memory
high/Io low if
the
CpU
is an 8085 in
minimum model
if
the
CpU
is
an
8088
in
minimum mode
the signal
is high for IO and
1ow
for
memory.
READY.
Ttris monitors the ready input
to
the
CpU
under
test; it
indicates that the
data
transfer can
be
completed.
Theory and Schematics--Moaef
6\55Se
Table 8-1-.
l[nemonics
TOIFROM
SYSTEM
rrlIDER
TESr
READY
8-7
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