HP 64653A Manual page 36

Tbeory arrd Schematics- -Modet
6\651*
&-LT
.
BTOCK DESCRTPTTON.
8-18.
CPU
Bus
Latches. (Service
Sheet
1,
U3B,Ul+B,U?A,U5B)
}-Lg.
Ttre
majority of the
cPu
information
is
sampled
with the
Bus latch
driven by the inverted Czu clock (ICtI{A,
ICTKB
or ICLK). This unqualified
clock
sampting
allows
the interface
module
to run with a
cPU
as fast as
10
[IHz.
When
the bus flip flops hold valid
information
it is
moved
to
other
latches.
Some
of the
CeU
signats (S0, S1o 52, and
READY)
are
sampled
with
UbB,
a
transparent
latch driven by ICLIS. This
means
that
these signals
are
sampled
in the
middle
of a
CPU
state but the information
is available
during
that
state
for
the
Controller,
ULB.
8-ZO,
The
QSO/A1E
signal is
sampled
by
ULA
on the rising
edge
of the
CPU
c1ock.
This is
when
the
min
mode ALE
signal is valid; the
max mode
QSO
is
also
valid at this time. It
is then passed
through a flip flop,
U3B
that
is
clocked
by
ICIIS| so
that it will
be
synchronous
with the Controller,
UlB.
8-2]-.
State
Controller. (Senzice Sheet
1,
U1B)
8-22. The state controller, ULBo is
the master of most of
the
functional blocks
on
the interface module. It
has
as inputs all the
status
information from the
CPU
plus the output of two
manual
switches.
One
ssitch
selects
between
the
8086
or
8088 CpU
and
the other switch
deter:nines
whether executed
or fetched instmetions ate sent to the logic
anaLyzet.
The
Controller operates synchronously
with the
CPU
since
it is driven by
the
inverted
CPU
cIock.
8-23.
The
Controller provides several signals which control the
operation
of the instrlctiol q.i".,".
LENLDQ
is
inveited and
input to the
f\SZZ5
FIFO's
(UTB,U$B)
at pin 1. ltre
CPU
clock
is inverted twice
to
produce IICLK and input
io'the
FIFO's
at pin 19.
Pin 1 functions as an
active high
enable
to
the
rising
edge
of the
clock,
pin 19. fhe
PtNtDQ
signal will pull one byte of
code
from the queue on
each
rising edge.
Ttre
instruction
queue
is
emptied
when
the controller issues the
TCLRQ
command.
IENIOBYTE
and
LENHIBYTE
are
used
to direct
the
low
byte
or
the high byte
into
the
queue,
respectively.
8-2\.
The
instruction
queue address
counter receives
some
of the
same
signals
that
control-
the queue.
TEXBYTE
enables
the
counter
to
count
up on the
next
rising
edge
of
ICLKA (UlrA)
or
ICLKB
(U8A,,U99,U10A,
U1-08).
TCLRQ
instructs
the
counter
to parallel- load
a
new vaLue
from
the
CPU
bus. The cormter
outputs
are
enabled
when
TEXBYTE
is
1ow.
8-25.
Ttre
Controller partial.J-y
controls information flow
to
the
logic
analyzer.
Ttre
Controller generates
a
signalo
HSTATT,
which is
high
when
there is
a
bus
cycle
that
needs
to
be sent
to the logic analryzer. Ttris
signal is
Nored r.rith
HEXBYIE
a;1d
then
NORed
with
ICLKB
to
generate
the analysis
strobe
CtK0. If
the
executed
mode
is
selected,
the controller gives
first
priority to
the
executed
instructions.
Other bus cycles
will
normally
fit
between
the
instructions with
rlo conflict,
but there
may
be a conflict if the
CPU
is
running
with
a
coprocessor.
If
such
a confliet
oeeurs
the
bus
eycle information from
the
coprocessor
is lost and
the
exeeuted
byte
is
sent
to
the analyzer,
HSTATT
will
be high
to
indicate
that a
bus
cycle
should have been sent
but the
other
status
bits will
indicate an executed byte.
8-b