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HQSoMX/HAIEMN
HQSLtfl(/LrNTAt4N
HREADY
HSTO
H8088
ICTI(A
ICLKB
ICTTC
IICLK
LBHE85/HSSoSg
rcrRQ
TENBUSADDR
tENtDQ
TENIIIBYTE
Ttreory and
Schematics__Mo
ael
5t+653I-
Table
B-1.
Mnemonics (Cont,d)
HIGH
QT'ET]E
STATUS
LINEO/HIGII
ADDRESS
LATCH
ENABLE.
fti:
is a
queue
status
J_ine, eSO,
if
the
CpU
is
in
maximum
mode;
it is
an
ad.dress
Latch enable if
the
CPU
is in
minimum
mode.
HIGH
QI'EIIE
STATUS L/LOVT INTERRUPT
ACIO{OWIEDGE
fri:
is a
queue
status line
Qg1
if
the
CpU
is
in
maximum
mode;
it is an interrupt
acknowledge data
strobe
if
the
CpU
is in
minimum
mode.
HrGH READY.
Ttris monitors
the
ready
input
to
the
cpu;
it
indicates
that
data
transfer
can
be
completed.
HIGH
STATTS
O. Status line
produced by
the
C0NTROLLER
for bus cycles only which is
irsed
to
generate
HSTATO.
HIGIi
8088.
The
CpU
being monitored
is
g0gg
if
high,
8085 if
low.
II'IUERTED
clocK
A.
Ttre
inverted
cpu
crock,
A
output.
rI[vEnrED
clocK
B.
The
inverted
cpu
crock,
B
output.
INVERTED CLOCK
C.
The
inverted
CpU
clock,
C
output.
INVERTED INVERTED
CLOCK. The fCLKC
inverted
by
U3A,
used
to
clock
the
INSTRUCTIOI
eUEIlE.
LOW BYTE
HIGH
ENABLE
gog5/HrcH
sso gogg.
This
sigt:al is byte high
enabre
if
the
cpu
is
an
g0gd;
it is
a status
line
SS0
if
the
CpU
is
an
g0gg.
tow
ctEAR
QITEITE.
This signar clears
the
rnstruetion
queue when
it
is low, and instructs
the
address
counter
to paralleI
load a
new
value
from
the
cpu bus.
LOId
ENABIE
BUs
ADDRESS.
r]ris signar
enables
the
BUS CYCLE
ADDRESS
LATCHES
to
be latched.
tOt{
EIIABIE L0AD
errEIJE.
Ttris signal
enables
the
INSTRUCTION
QLIEUE
to
load
in
one byte.
LOW
ENABLE
HIGH
BYTE.
Ttris signal
enables
byte of data to be
presented
to
the
QIJEUE.
the
high
INSTRUCTIOI{
Lol{ EIIABIE
tol{ ByrE. This signal enables the
Iow
byte of data to be
presenied
to
the
rNSTRUcrroN
QIJEUE.
LENTOBYTE
8-g
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