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fheory
and Schematics--Mode1
6\6Sy
Tab1e
8-1.
ldnemonics
(Cont'd)
\-.
TOIrROM
THE GP
PREPROCESSoR
CLKO
clocK
o.
Ttris
signal is the qualified cLock for
the
anaLyzer generated
on
the
Dedicated
Interface
Card.
IrDO-?
High Data
0-7.
This
is
the
bus
to the
Preprocessor
for
the
Dedicated
Interface
Card
ID
number.
HADDnO-19
HIGH
ADDRESS
O-19.
Ttris
is
the address
bus to
the
Logic
Analyzer
iIDATAO-15
HIGH DATA
O-15. Ihis is the data bus to
the togic
Analyzer.
IISTASo-I-2
HIGH
STATUS
0-L2.
This
is the status bus to
the
Logic
Analyzer.
INTBA-
SCHEMATI
C
IIII.IEMONI CS
HA0-15/m0-15
HIGH
ADDRESS/HIGH
DATA
0-L5. This is the
internal
multiplexed
address/data
bus on the
8086/8o88
Dedieated Interface
Card.
HALS-L1|H53-5
HI6H
ADDRES5
L5-19lHIGH
STATUS
3-5. Ttris is
the
internal multiplexed
address/status
bus on
the
8085/8088
Dedicated
Interface
Card.
HBUSI'IODE
HIGH
BUS
MODE.
This
signal
generated
by the
MODE
SELECT
SWITCII
is in
BUS
mode when
high, in
EXECIIIIED
mode when l-ow.
IIEIILDQ
HIGH
ENABTE
tQAD QIJEUE. tENtDQ
is
inverted by
U3A
to
HENLDQ
and
then
enables
the
INSTRUCTION QUEUE
(U7B,
U8e)
to
load
one
byte.
IIEXBYTE
flIGH
EXECIIIED
BYTE. If this signal is high
an
executed
byte
urill
be sent
to
the
logic
anaLyzer
during the current
cycJ.e.
HMM
HIGH
MINIMUM. The
CPU
is in
minimum
mode when
this
signal is high, in
maximum
mode
when
it is
Iow.
8-8
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