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1-4.
Circuit Description
This unit comprises the following boards. This circuit description describes functions of each board separately.
• CN-3837 board (Refer to
• CPU-453A board (Refer to
• DIO-101 board (Refer to
• DM-155 board (Refer to
• HP-175 board (Refer to
• LED-528 board (Refer to
• MB-1217 board (Refer to
• MEC-40 board (Refer to
• RC-107 board (Refer to
• SW-1628 board (Refer to
• SY-422 board (Refer to
• HN-431 board (Refer to
• RD-41 board (Refer to
"1-4-13. RD-41 Board
• NET-23 board (Refer to
• DIF-260/261 board (Refer to
1-4-1.
SY-422 Board
The SY-422 board contains CPUs, CPU's peripheral devices, and interfaces.
This board also has a function to relay network data with a PCI Express card (standard equipment) as an external interface.
CPUs and peripheral devices
This board has two main CPUs: CPU2 (IC2) mainly controls internal devices and CPU1 (IC1) handles external interfaces.
CPU1 (IC1) runs on the program stored in the flash memory (IC604, IC607) and CPU2 (IC2) runs on the program stored
in the flash memory (IC1504, IC1507).
These programs can be upgraded using a USB memory through the USB controller (IC104).
CPU1 (IC1) contains DRAM (IC501 to IC504, and IC1401 to IC1404) and FRAM (IC610, IC1510, and IC2901 to
IC2903) to save system settings.
This board has a real-time clock (RTC) for calendar function and BT101 is the power unit for backup of the RTC.
Protocol communication
There are three types of inter-board communication.
• Serial Rapid IO: Used for 3.125 Gbps communication with endpoints on each board through the Serial Rapid IO
(SRIO) switch IC5 to control devices.
• RS232C: CPU1 (IC1) and CPU2 (IC2) have a communication port for debugging respectively.
• IIC: Used mainly for the configuration setup on each bard and for 400 kbps communication with the power supply
unit.
The SRIO-FPGA (IC3) controls internal devices of the unit and also has the following functions.
• IIC communication with each board and the power supply unit
• CPU interrupt control
• Fan rotation detection
• External input and output (25-pin GPIO) control
The SRIO-FPGA also performs communication with the BANK memory on the DM-155 board and relays network data
to CPU1 (IC1) via the SRIO endpoint.
PWS-4500
"1-4-7. CN-3837
Board")
"1-4-2. CPU-453A
Board")
"1-4-4. DIO-101
Board")
"1-4-6. DM-155
Board")
"1-4-5. HP-175
Board")
"1-4-9. LED-528
Board")
"1-4-10. MB-1217
Board")
"1-4-11. MEC-40
Board")
"1-4-3. RC-107
Board")
"1-4-8. SW-1628
Board")
"1-4-1. SY-422
Board")
"1-4-12. HN-431
Board")
(PWSK-4505)")
"1-4-14. NET-23 Board
(PWSK-4506F)")
"1-4-15. DIF-260/261 Board
(PWSK-4508)")
1-22
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