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1-4-2.
CPU-453A Board
The CPU-453A board contains a high-speed CPU IC100 (1.2GHz 2-core processor) suited for network processing, and
has the following main functions.
• Program working memory (IC101 - IC104): Four pieces of DDR2 (128 MB) accessible with 64-bit, 600MHz
• Memory to store the program (IC303): Flash ROM (32 MB)
• Communication between SY-422 board and PCI Express card: IC704 (PCI Express switch) switches four sets of
2-Gbps lanes to connect the SRIO FPGA IC3 on the SY-422 board to the PCI Express card.
• CPU communication: Communication with the SY-422 board through the connector CN703 is possible.
• PIO (Programmed I/O): LED, test pin, DIP switch
• Power supply: Voltage +12 V supplied from the SY-422 board is converted to other voltages that are supplied to
the CPU, DDR2, PCI Express switch, Ethernet PHY, and other devices.
• Clocks:
- X100: Generates 100MHz clock (for CPU).
- X700: Generates 25MHz clock (for PCI Express).
• Reset circuit: IC1105 generates a reset signal and sends it to each block.
1-4-3.
RC-107 Board
RC-107 board is a relay board that is connected to the connector CN702 on the CPU-453A board, and transmits signals
to the PCI Express socket CN102 on the RC-107 board.
1-4-4.
DIO-101 Board
The DIO-101 board inputs audio and video signals.
Video signal processing (input mode)
The DIO-101 board has 9-channel SDI inputs/outputs operating as 4-channel input, 4-channel monitor input, and 1-
channel HD SDI input to enable 4K processing.
The 4K SDI signals from the connectors (J201 to J204) are input through the equalizer (IC201 to IC204) to the baseband
FPGA (IC100). In the same way, the Networked Media Interface signal is received by the optional NET-23 board and
is converted to SDI signals. Then the SDI signals are input through the MB-1217 board to the baseband FPGA on the
DIO-101 board.
In the same way, HD SDI signals from the connector J301 are input through the equalizer IC302 to the baseband FPGA
(IC100). Then the HD SDI signals are compressed to XAVC-Intra frame data by the video encoder (IC1000 to IC1800).
The compressed signals are input to the backplane FPGA (IC200) and stored in the DRAM (IC3002, IC3003). Then the
signals are multiplexed sequentially with audio data, video data, and uncompressed meta data, and the multiplexed
signals are transferred through DMA (Direct Memory Access) to the BANK FPGA (IC0040) on the DM-155 board with
3.125 Gbps serial transmission. This DMA transfer includes 4K HD independently for each system.
Audio signal processing (input mode)
The DIO-101 board has four AES/EBU connectors (J3601 to J3602) allowing input for eight channels.
Furthermore, the HD SDI embedded audio signals for 16 channels can be input, and each channel is independently
selectable.
AES/EBU-format digital audio signals and HD SDI embedded audio signals are input to the audio FPGA (IC300) in
which processes (channel selection, gain control, etc.) are performed. The processed signals are input to the backplane
FPGA (IC200) in the same way as video signals.
After the audio signals are stored in the DRAM (IC3002, IC3003), they are multiplexed with video signals and the
multiplexed signals are DMA transferred to the BANK FPGA (IC0040) on the DM-155 board with 3.125 Gbps serial
transmission.
PWS-4500
1-23
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