Hp-175 Board - Sony PWS-4500 Service Manual

Timecode signal processing (input mode)
The timecode signal that is input from the timecode input connector (J302) is input to the baseband FPGA (IC100) in
which parallel processing is applied to the signal, and then the processed timecode signal is detected by the CPU. The
same timecode signal is output from the timecode output connector (J302) for cascade processing.
Video signal processing (output mode)
Video signal processing is performed for each different system to enable 4K processing and HD processing at the same
time.
Signals multiplexed sequentially with audio data, video data, and uncompressed meta data are transferred through DMA
(Direct Memory Access) from the BANK FPGA (IC0040) on the DM-155 board with 3.125 Gbps serial transmission.
This DMA transfer system is independent for 4K signal and HD signal.
Signals transferred from the DM-155 board through DMA are input to the backplane FPGA (IC200) and are stored in
the DRAM (IC3002, IC3003).
The XAVC-I signal separated in the backplane FPGA (IC200) is processed by the video decoder (IC1000 to IC1800)
and the processed signal is input to the baseband FPGA (IC100).
Parallel baseband signals are encoded into the SDI signals in IC100 and the encoded signals are output as SDI signals
from the connectors J201 to J204 through the SDI drivers (IC201 to IC208).
SDI signals are sent through the MB-1217 board to the NET-23 board, and are then converted to the Networked Media
Interface signal on the NET-23 board.
Audio signal processing (output mode)
The DIO-101 board has four AES/EBU connectors allowing output for eight channels. Furthermore, the HD SDI
embedded audio signals for 16 channels can be output, and each channel is independently selectable.
Signals multiplexed in the same way as video signals are input to the backplane FPGA (IC200). After the signals are
stored in the DRAM (IC3002, IC3003), only audio signals are separated and sent to the audio FPGA (IC300). IC300
performs processing such as channel selection and gain control. AES/EBU-format digital audio signals are output from
the AES/EBU connectors (J3601 to J3602).
Timecode signal processing (output mode)
The timecode signal written to the baseband FPGA (IC100) by the CPU is processed for serialization, and is then output
from the timecode output connector (J302).
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HP-175 Board

The HP-175 board mounted at the front of the unit has the following functions.
• SW-1628 board and LED-528 board LED control
• SW-1628 board switch control
• Power shutdown processing
• Storing management data
1-4-6. DM-155 Board
The DM-155 board has the following main functions.
• BANK memory function (main cache for audio/video data)
• Audio/video reference circuit
• 9-pin remote connector
• SharePlay function
• Multi Monitor function
• MONITOR function of the Networked Media Interface
PWS-4500
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