National Instruments PXI-6238 User Manual page 126

input on each rising edge of a filter clock. M Series devices use an onboard
oscillator to generate the filter clock with a 40 MHz frequency.
Note NI-DAQmx only supports filters on counter inputs.
The following is an example of low-to-high transitions of the input signal.
High-to-low transitions work similarly.
Assume that an input terminal has been low for a long time. The input
terminal then changes from low-to-high, but glitches several times. When
the filter clock has sampled the signal high on N consecutive edges, the
low-to-high transition is propagated to the rest of the circuit. The value of
N depends on the filter setting; refer to Table 10-3.
The filter setting for each input can be configured independently. On power
up, the filters are disabled. Figure 10-4 shows an example of a low-to-high
transition on an input that has its filter set to 125 ns (N = 5).
RTSI, PFI, or
PXI_STAR Terminal
1
Filter Clock
(40 MHz)
Filtered Input
Enabling filters introduces jitter on the input signal. For the 125 ns and
6.425 µs filter settings, the jitter is up to 25 ns. On the 2.55 ms setting, the
jitter is up to 10.025 µs.
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Table 10-3. Filters
N (Filter
Clocks Needed
Filter Setting to Pass Signal)
125 ns 5
6.425 µs 257
2.55 ms ~101,800
Disabled —
1 2 3 4 1 2
Figure 10-4. Filter Example
10-9
Chapter 10 Digital Routing and Clock Generation
Pulse Width Pulse Width
Guaranteed to Guaranteed to
Pass Filter Not Pass Filter
125 ns
6.425 µs 6.400 µs
2.55 ms 2.54 ms
—
Filtered input goes high
when terminal is sampled
3 4 5
high on five consecutive
filter clocks.
NI 6238/6239 User Manual
100 ns
—