TTI LD300 Service Manual page 21

300w dc electronic load
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The negative VXO subtracts from the positive VS at the input of IC23-B. For as long as VS is the
larger, D15 conducts and holds the amplifier output at -0·7V. When the magnitude of VS falls
below VXO, the output goes positive, and starts to turn on Q5 (normally R267 & R268 set SSH at
-0·75V, so the emitter of Q5 is a little below 0V). Q5 acts as a variable resistor, reducing the
demand input to the comparison amplifier by causing a voltage drop across R230. The result is
a feedback action, which reduces the load current and attempts to hold the load voltage at
VDROP. If VS falls below this, then Q5 conducts hard and the load conducts no current. Note that
this is not a latching condition – if the load voltage recovers, the load will conduct again. The
positive voltage at VLIM turns on Q12, which pulls down WARN, and makes the panel lamp show
orange by driving both RED and GRN.
When slow start is engaged, SSH is pulled to +5V by Q13, Q10 is off and Q5 has no effect on the
comparison amplifier. The threshold comparator IC46-B implements the dropout function.
Gate Drivers
Two identical circuits, IC21 and IC30, drive the gates of the two FETs. These amplifiers have two
sets of differential inputs, and act to make the voltage between the feedback pair (pins 4&5)
match the voltage across the signal pair (pins 1&8). The signal from the comparison amplifier is
reduced to 5mV per Amp to match the voltage across the 5mΩ sense resistors. The full scale
voltage is therefore 200mV, when each FET conducts 40 Amps. Typically, over most of the
working range, the FET gate voltages will be about 2·5 to 4·0 volts. D2 and D3 prevent the
outputs going more negative than 0·7V when DRIVE is negated. IC26-A and -C switch in
bandwidth limiting networks on the slowest slew rate range.
VR13 allows the offset of the LH side to be adjusted to match the RH side (this balances the heat
dissipation under high voltage and low current conditions). If either IC21 or IC30 is replaced, set
up the unit to conduct a load current of about 0·5 Amp, measure the voltages across the two 5mΩ
sense resistors and adjust VR13 until the are reasonably equal.
A portion of each gate drive signal (CHK1 & CHK2) is applied to the saturation detector
comparators IC53-A and -B. If either gate voltage exceeds about 8·3 V, the FET is assumed to be
in saturation; WARN goes low, setting the front panel lamp to the orange state, with both the red
and green diodes driven. The usual cause of this is that the user is not applying any voltage to
the load.
Current Fault
The voltage at the top of each sense resistor is monitored by comparators IC31-A & -D (-B & -C
are not used). When this voltage exceeds 270mV (corresponding to about 50 Amps) the
comparator output goes low and trips the fault latch. Note that there may be some variation in this
current value, as the connection is to one sense terminal and one end terminal of the 4-terminal
resistor. this The CR filter networks allow the current to exceed the threshold briefly before the
fault circuit is triggered.
Input Enable and Fault Logic
If slow start is not engaged, SST is low, making the output of IC52-A low and giving IEN sole
control of the drive latch. Similarly STRT is high giving IEN control of the OSCGO signal. Q13 is
off and the low-voltage drop-out circuit operates normally.
When IEN is asserted high, the output of IC57-D goes low. If the fault latch is not set, pin 11 of
IC51-D is also low, so the output of IC52-D goes high, asserting DRIVE to the comparison
amplifier and GRN to light the front panel lamp. When IEN is pulled low, by either the front panel
switch or the remote disable input through the opto-isolator IC34, this action is reversed and
DRIVE goes unconditionally low.
In Transient mode, ST is low and is gated with the inverted IEN from IC56-D in IC57-A to assert
OSCGO to start the oscillator synchronously with the enable action. This ensures that the first
cycle of the oscillator has the correct period.
When SST is asserted, the slow start logic shares control of DRIVE and OSCGO.
20

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