1.4 Motherboard Block Diagram
H13DSG-O-CPU REV 1.00
JIO1
JMC4A,B
MPLINK
VPP
MPLINK
VPP
JMC3A,B
JMC2A,B
MPLINK
MPLINK
JMC1A,B
JMC5A,B
VPP
JIO1
REAR I/O
10GLAN
VGA
USB3
COM
UID
ASM1061
JAIOM2SB1
For AIOM2
MISC
Sideband
PHY VGA UART
CPU1 USB2.0 Port (0/1)
USB
NCSI
PCIe
BMC
FAN1~10
eSPI
AST2600
BoxHDer
BMC TPM
1x4 *8
FW
XXXX
1x4 *2
SPI
BMC FW
ROM
DRAM
EMMC
SPI0
AIOM Sideband
DDR4
256M x16
EMMC
H26M41208HPR
8G
PCIE G3 BY4
USB3
USB3.Port(11)
USB3.Port(10)
Gen3 By 1
xGMI3
USB2
PE1
PE3
PE0
PE2
CPU 1 (P0)
XXXX
PE5 G3by1
PE5 G3BY1
SocketID 00
eSPI
VCCP1
USB+
M
e
64MB
JTPM1
for TPM header
2*5-1
eSPI
SPI0
EMMC
CPLD
6900C
EMMC
SPI
SPI
eSPI
CPLD FW
BIOS ROM
ROM
32MB
PLD config backup
8M
Figure 1-9. System Block Diagram
100MHz CLK
CLK Gen
CLK Gen
9QXL2001
9QXL2001
100Mhz CLK
100Mhz CLK
PE4
PE3
PE4
CPU 2 (P1)
WLAF
(0)
WLAF
WLAF
XXXX
xGMI2
1 LINK XGMI
xGMI0
SocketID 00
xGMI0
xGMI3
xGMI1
VCCP1
2 Link xGMI
xGMI2
m
C
H
A
-
L
M
e
m
C
H
A
-
L
1DPC*12
1DPC*12
DIMM DDR5
DIMM DDR5
DIMM DDR5
DIMM DDR5
19
Chapter 1: Introduction
PCIE G3 BY4
M.2 GEN3 BY4
JMC10A,B
JMC9A,B
JMC8A,B
JMC7A,B
JMC11A,B
J35,J36
xGMI1
USB2
USB2
PE2
PE1
PE0
USB
VPP
MPLINK
MPLINK
MPLINK
VPP