evertz 5700MSC-IP User Manual
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evertz 5700MSC-IP User Manual

Ip network grand master clock & video master clock system
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IP Network Grand Master Clock & Video Master Clock System
© Copyright 2018
EVERTZ MICROSYSTEMS LTD.
5292 John Lucas Drive
Burlington, Ontario
Canada L7L 5Z9
Phone:
+1 905-335-3700
Sales:
sales@evertz.com
Tech Support: service@evertz.com
Web Page:
http://www.evertz.com
Version 0.2, July 2018
The material contained in this manual consists of information that is the property of Evertz Microsystems and is intended solely for the use of
purchasers of the 5700MSC-IP series product. Evertz Microsystems expressly prohibits the use of this manual for any purpose other than the
operation of the 5700MSC-IP series product. Due to on going research and development, features and specifications in this manual are subject to
change without notice.
All rights reserved. No part of this publication may be reproduced without the express written permission of Evertz Microsystems Ltd. Copies of
this manual can be ordered from your Evertz dealer or from Evertz Microsystems.
Model 5700MSC-IP
User Manual
Fax: +1 905-335-3573
Fax: +1 905-335-7571

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  • Page 1 Version 0.2, July 2018 The material contained in this manual consists of information that is the property of Evertz Microsystems and is intended solely for the use of purchasers of the 5700MSC-IP series product. Evertz Microsystems expressly prohibits the use of this manual for any purpose other than the operation of the 5700MSC-IP series product.
  • Page 2 This page left intentionally blank...
  • Page 3 IMPORTANT SAFETY INSTRUCTIONS The lightning flash with arrowhead symbol within an equilateral triangle is intended to alert the user to the presence of uninsulated “Dangerous voltage” within the product’s enclosure that may be of sufficient magnitude to constitute a risk of electric shock to persons. The exclamation point within an equilateral triangle is intended to alert the user to the presence of important operating and maintenance (Servicing) instructions in the literature accompanying the product.
  • Page 4 WARNING Changes or Modifications not expressly approved by Evertz Microsystems Ltd. could void the user’s authority to operate the equipment. Use of unshielded plugs or cables may cause radiation interference. Properly shielded interface cables...

  • Page 5: Table Of Contents

    5700MSC-IP IP Network Grand Master Clock & Video Master Clock System TABLE OF CONTENTS OVERVIEW ........................... 1 1.1. QUICK START GUIDE......................3 1.1.1. Mounting and Power Connections ................3 1.1.2. Front Panel Installation ....................3 1.1.3. Configuring the Ethernet Ports ................... 3 1.1.4.
  • Page 6 4.1.6. AUX Connections (available with 5700MSC-IP+AUX option) ........60 4.1.7. GPIO, LTC Input, Secondary LTC Outputs .............. 60 4.1.8. Unbalanced Audio Connections AES 1, 2 and 3 (available with 5700MSC-IP+AUX option) ........................60 4.1.9. DARS OUT (available with 5700MSC-IP+AUX option) ..........61 4.1.10.
  • Page 7 5700MSC-IP IP Network Grand Master Clock & Video Master Clock System OPERATION ..........................67 5.1. FRONT PANEL CONTROLS ....................67 5.1.1. Front Panel Buttons ....................67 5.1.2. The Status Screens ....................68 5.1.3. Panel Lock Function ....................71 5.1.4. Front Panel LCD Displays ..................71 5.2.
  • Page 8 5700MSC-IP IP Network Grand Master Clock & Video Master Clock System Figures Figure 1-1: Front View of the 5700MSC-IP ..................1 Figure 1-2: Ethernet Port Configuration ..................4 Figure 1-3: PTP All Ports Menu ..................... 7 Figure 1-4: PTP GigE 1 ........................7 Figure 1-5: PCR GigE 1 Menu .......................
  • Page 9 Evertz products are for informational use only and are not warranties of future performance, either expressed or implied. The only warranty offered by Evertz in relation to this product is the Evertz standard limited warranty, stated in the sales contract or order confirmation form.
  • Page 10 5700MSC-IP IP Network Grand Master Clock & Video Master Clock System This page left intentionally blank Page - vi Revision 0.2...

  • Page 11: Overview

    GPS and GLONASS satellite constellation signals is required for PTP, AVB PCR, or 2059-2 timing protocols to be hosted by the system. The 5700MSC-IP can also produce PTP, AVB, PCR or 2059-2 timing protocols when using a PTP reference of suitable quality.
  • Page 12 5700MSC-IP IP Network Grand Master Clock & Video Master Clock System The SPG section of the 5700MSC-IP provides six independent timeable reference outputs. These six sync outputs may be configured to provide independently timed color black (black burst) outputs, independently timed HDTV tri-level sync outputs, 10MHz outputs, word clock, and various available pulses.

  • Page 13: Quick Start Guide

    Clearance of 2” (5cm) must be maintained around the fan exhausts on either side of the chassis. The power supply operates from an AC line frequency of 50Hz to 60Hz, at 100V-240V (auto-sensing). The fan module runs off of the single power supply. The power consumption of a 5700MSC-IP is 125 Watts with all options installed.

  • Page 14: Figure 1-2: Ethernet Port Configuration

    1Gb/s Ethernet ports, the frame Ethernet port and the two 10Gb/s Ethernet SFP ports on the 5700MSC-IP. The 1GigE 1, 1GigE 2, 10GigE 1 and 10GigE 2 ports are used to carry mission-critical data, such as PTP, NTP and PCR. The frame Ethernet port is used for management purposes (VistaLink Pro, syslog, firmware updates, etc.).

  • Page 15: Selecting And Connecting The Frequency References

    • GNSS Fixed – The 5700MSC-IP will look for a GNSS antenna attached to the GPS port on the back of the unit. This mode is intended for applications where the location of the GNSS antenna is fixed. Start-up time before receiving data will be longer the first time the unit is first powered up as the antenna determines the fixed location.

  • Page 16: Selecting And Connecting Time References

    5700MSC-IP IP Network Grand Master Clock & Video Master Clock System the 5700MSC-IP will be only as good as that of the reference input. The phase of the outputs will be aligned to that of the reference input. • Internal – The 5700MSC-IP will free run on its internal high stability ovenized oscillator. Select this option if no external reference is available to the unit.

  • Page 17: Figure 1-3: Ptp All Ports Menu

    1.1.6.1. PTP All Ports Menu To navigate to this menu, press the GENERAL button on the front panel of the 5700MSC-IP, then the ESC button to reach the top level of the menu. With the encoder knob, scroll down to the PTP All Ports submenu, and press the SELECT button.

  • Page 18: Configuring Pcr

    IP Network Grand Master Clock & Video Master Clock System • Set the PTP Announce Rate to the value that you wish. This should be the same as other PTP devices on the same PTP network that this 5700MSC-IP will be communicating with via this port. •...

  • Page 19: Checking The Status Of The Unit

    1.1.10. Configuring the Sync Outputs The sync outputs of the 5700MSC-IP are configured in the OUTPUT menu, accessed by pressing the OUTPUT button. All sync outputs are derived from the master oscillator and will be locked in frequency and phase. The sync outputs are all programmable to output several different sync types and can be phased independently from each other.

  • Page 20: Configuring The Test Generator Outputs

    Standard Time (CST) is UTC –6:00 hours. Mountain Standard Time (MST) is UTC –7:00 hours. Pacific Standard Time is UTC –8:00 hours. The 5700MSC-IP also supports Daylight Savings Time, which must be enabled separately for each time output. Below are descriptions of the time outputs available from the 5700MSC-IP.

  • Page 21: Final Steps Of Set Up And Securing All Connections

    Phillips mounting screw. The GPS D-Sub connector on the back of the unit should be secured to the 5700MSC-IP using mounting screws. The AC power cords can be fixed to the unit using the retaining clips provided.
  • Page 22 5700MSC-IP IP Network Grand Master Clock & Video Master Clock System This page left intentionally blank Page - 12 Revision 0.2...

  • Page 23: Technical Specifications

    5700MSC-IP IP Network Grand Master Clock & Video Master Clock System TECHNICAL SPECIFICATIONS 2.1. ANALOG SYNC OUTPUTS Output Standards: Black Burst: SMPTE ST 170 (NTSC-M), ITU-R BT.1700-1 (PAL-B) Bi-Level: Slo-Pal 625i/48, 625i/47.95, 480p/59.94 HD Tri-Level: SMPTE ST 274 (1080p/23.98, 1080p/24, 1080i/50, 1080i/59.94, 1080i/60, 1080p/23.98sF,...

  • Page 24: Sdi Test Generators (With +Sdi-Tg, Or +10G-Tg Options)

    5700MSC-IP IP Network Grand Master Clock & Video Master Clock System field pulse HD Tri-level Sync (same HD standards as sync outputs) Number of Inputs: 2 Loop thru High impedance, isolated, differential external termination required 75 Ω HD-BNC, bayonet positive locking (Amphenol)

  • Page 25: Aux Expansion Module Option (Aes & Analog Audio Test Set, Dars, Gpio, And Ltc)

    5700MSC-IP IP Network Grand Master Clock & Video Master Clock System 2.9. +AUX EXPANSION MODULE OPTION (AES & ANALOG AUDIO TEST SET, DARS, GPIO, AND LTC) 2.9.1. LTC Outputs Standard: SMPTE ST 12-2 or IRIG-B Frame Rate: 24, 25, 30 and 29.97 (drop frame and non-drop frame)
  • Page 26 5700MSC-IP IP Network Grand Master Clock & Video Master Clock System This page left intentionally blank Page - 16 Revision 0.2...

  • Page 27: Theory Of Operation

    IP Network Grand Master Clock & Video Master Clock System THEORY OF OPERATION The 5700MSC-IP is equipped with six programmable sync outputs along with a 10MHz and a Wordclock output. When equipped with a test generator option (+SDI-TG, +10G-TG, +AUX), analog/digital audio and analog/digital video outputs will be available.
  • Page 28 5700MSC-IP IP Network Grand Master Clock & Video Master Clock System HD Tri-Level Signals North American Analog tri-level sync output modes are available for a variety of HD formats. These 1080i/60 outputs are generated according to SMPTE ST 274 and SMPTE ST 296. All tri-level 1080i/59.94...
  • Page 29 5700MSC-IP IP Network Grand Master Clock & Video Master Clock System Pulse Signals The pulse output modes provide timing pulses that can be used to lock downstream equipment or can be helpful for troubleshooting purposes. These outputs cannot be phased and always remain phase-locked to the frequency reference. These signals may not be affected by any global phase offset.

  • Page 30: Test Generator Options

    NTSC-M output format. This control is located in the OUTPUT root menu. 3.1.4. Global Phase Controls The Global Phase feature of the 5700MSC-IP provides a single point of control from which all video outputs can be phased simultaneously. There are separate controls for each of the frequency lock modes (GNSS+, Video, 10MHz, and Internal) to allow different phase offsets to be applied depending on the lock source.
  • Page 31 5700MSC-IP IP Network Grand Master Clock & Video Master Clock System Affected by Minimum Phasing Output Global Phase Resolution Sync – NTSC & PAL modes 1 ns Sync – Tri-level modes 1 ns Sync – 5MHZ/10MHZ CW modes Sync – NTSC/PAL subcarrier modes Sync –...

  • Page 32: Figure 3-1: Irig-B127 Format And Alignment To Irig1 Datum Pulse

    5700MSC-IP IP Network Grand Master Clock & Video Master Clock System BGF2 BGF1 BGF0 Pol. Cor. Color Fr. Drop Fr. Page - 22 Revision 0.2...

  • Page 33: Figure 3-3: Pal Alignment To 1Hz Pulse And Pal Color Frame Pulse

    5700MSC-IP IP Network Grand Master Clock & Video Master Clock System Page - 23 Revision 0.2...

  • Page 34: Genlock

    GENLOCK 3.2.1. Frequency Locking At the heart of the 5700MSC-IP is the master oscillator circuit. Refer to the block diagram in Figure 3-5 below. For maximum versatility and reliability, two separate oscillators are employed. In narrow mode, an ovenized quartz oscillator (OCXO) is used for maximum stability. In wide mode, a voltage controlled oscillator (VCXO) provides a wide lock range and fast lock times.

  • Page 35: Selecting The Frequency Reference Type

    3.2.2. Selecting the Frequency Reference Type The frequency reference for the 5700MSC-IP is selected with the Freq Reference Src menu item in the Frequency Ref menu off the INPUT root menu. When GNSS is selected, the 5700MSC-IP will use the GNSS receiver attached to the GPS port on the rear of the unit (see section 3.2.13).

  • Page 36: Lock Type Selection

    This will activate the Hw Fail message on the front panel and can also send out an SNMP trap. If such a fault occurs, it is not advisable to power down or attempt to restart the unit. Contact Evertz customer service for further assistance at +1 905-335-7570 or see www.evertz.com/support.
  • Page 37 At any time during this Slow relock process, the operator can force the 5700MSC-IP to immediately lock to the reference by performing a frequency jam. This can be performed by selecting Jam Reference in the Jam Input menu off the INPUT root menu. It can also be performed remotely through SNMP.

  • Page 38: Video Genlock Operation

    SMPTE timing due to the delay introduced in the measurements by the DAC process. Since the outputs of the 5700MSC-IP are aligned using SMPTE timing, their phase must be advanced significantly in order to appear correct with Tektronix timing.

  • Page 39: Ntsc Genlock Operation

    IP Network Grand Master Clock & Video Master Clock System  With no phase offset applied, the SDI outputs of the 5700MSC-IP will be measured by Tektronix gear as approximately 4.7us delayed (SD) or 1.3us delayed (HD) when the Tektronix device is externally referenced to the respective analog sync Examples of equipment that perform SMPTE compliant timing measurements are the Phabrix SX/DX and OmniTek OTM-1000.
  • Page 40 Subcarrier to Horizontal (SCH) offset to assure proper lock. The approximate SCH value is shown in the Inputs status screen. If the SCH error is higher than 30º, the 5700MSC-IP will fall back to locking to the horizontal edge of the video only. If the SCH error is in excess of 50º, or the colorburst cannot be accurately measured, the 5700MSC-IP will report that the applied reference is unlockable.

  • Page 41: Ntsc Genlock With Ten-Field Reference

    When an NTSC reference is applied that carries a ten-field reference pulse in the vertical blanking interval (VBI) as specified in SMPTE ST 318, the phase locking ability of the 5700MSC-IP is enhanced. The ten-field reference provides 5 frames worth of phasing information that allows deterministic locking of 23.98Hz standards, the 6/1.001Hz pulse, and DARS/AES signals.

  • Page 42: Figure 3-8: Smpte St 318 Ten-Field Reference On Ntsc Line 15

    Note that AES/DARS Test Generator Outputs are only available on the +AUX option. When the 5700MSC-IP is locked to an NTSC reference with a ten-field pulse, the AES, DARS, and Wordclock outputs can be phase locked properly. The AES/DARS/WC lck menu item located in the AES Audio menu off the OUTPUT root menu should be set to NTSC/fractional.

  • Page 43: Pal Video Genlock Operation

    PAL reference. If the Subcarrier to Horizontal sync error is higher than 30º the 5700MSC-IP will fall back to horizontal sync edge locking only. If the SCH error is higher than 50º, or the colorburst cannot be measured, the unit will report that the reference is unlockable.
  • Page 44 PAL reference. Because the AES signal coincides with the PAL signal on every frame, the phase of the AES/DARS outputs will be the same between multiple 5700MSC-IP units that are locked to PAL. In addition, the AES block length of 192 frames is evenly divisible into a single PAL frame so the start of an AES block (identified by the Z preamble) will correctly align to line 1 of the PAL reference (as illustrated in lock diagram #3 of Figure 3-9).

  • Page 45: Hd Tri-Level Genlock

    Refer to Table 3-5 for a summary on the phase locking capability with other tri-level references. It should be noted that tri-level references do not supply enough phase information to color frame NTSC-M or PAL-B sync outputs. When multiple 5700MSC-IP units are locked to a tri-level source, the Page - 35 Revision 0.2...

  • Page 46: Slo-Pal Genlock

    24Hz film standards and 625i/47.95 for use with 23.98Hz film standards. With Slo-PAL references, the 5700MSC-IP locks its frequency to the horizontal sync edges and uses the vertical sync for phasing. See Table 3-6 for phasing ability of each reference type.

  • Page 47: Continuous Wave And Internal References

    5700MSC-IP IP Network Grand Master Clock & Video Master Clock System 3.2.12. Continuous Wave and Internal References Color Field 1 NTSC-M Output 1080i/59.94 Output 720p/59.94 Output 1080p/23.98sF Output End of Sync Word LTC 29.97Hz Output Z Preamble DARS/AES X Y X Y X Y...
  • Page 48 In order to align the output phase of two 5700MSC-IP units that are locked to a stable CW reference, the Ten MHz Global Phase controls can be used. When the Ten MHz Global Phase is enabled, the 5700MSC-IP outputs can be phased manually to align them with another source.

  • Page 49: Gnss Frequency Reference

    Figure 3-12: Lock Diagram #6 – GNSS Frequency Reference The 5700MSC-IP unit can lock in frequency and phase to the high-accuracy timing provided by the GNSS satellites. The main oscillator frequency is locked to the 1 pulse per second (PPS) timing pulse provided by the receiver.

  • Page 50: Timekeeping

    3.3. TIMEKEEPING The 5700MSC-IP contains a system clock to keep track of time and date. The stability of this clock is equal to the selected frequency reference. The accuracy of this clock is determined by the selected time reference and lock mode. The 5700MSC-IP can access time references through the GNSS receiver, PTP from another 5700MSC-IP, SNTP, or VITC read from a black burst reference.

  • Page 51: Time Lock Types

    UTC time requiring the system clock to be occasionally adjusted. The 5700MSC-IP has several timecode outputs, each of which possess their own clock that runs independently from the system clock. The LTC outputs and each sync output (including 10MHz and Wordclock) and test generator outputs have their own independent clock.

  • Page 52: Coordinated Universal Time (Utc)

    Leap seconds can cause complications with 25Hz LTC or PAL VITC. The 5700MSC-IP expects that the time reference provides UTC time. This is a requirement for the NTP server hosting using the NRC protocol.

  • Page 53: Figure 3-14: 5700Msc-Ip Time Reference Sources

    When GNSS is selected as the time reference, time and date are obtained from the GNSS receiver that is connected to the 5700MSC-IP. The GNSS time provided by the receiver is then converted to UTC time by adding leap seconds. This time reference is extremely accurate and once the system clock has been jammed to the GNSS receiver, it should remain in sync for a very long time without requiring further jams, provided the selected frequency reference is also accurate.
  • Page 54 The 5700MSC-IP will continuously compare the system clock to the incoming VITC timecode. When a difference of more than 2 milliseconds is detected the 5700MSC-IP will generate a jam event, or a jam warning depending on the Lock Type setting. When a jam event occurs, the time read from the VITC input is jammed into the system clock.

  • Page 55: Ltc And Vitc Timecode

    3.3.3.6. No Time Reference When the time reference source is set to None, the 5700MSC-IP will ignore all time reference sources and the system clock will freerun. The time and date must be set manually using the Set System Time and Set System Date menu items located in the GENERAL root menu.
  • Page 56 5700MSC-IP IP Network Grand Master Clock & Video Master Clock System Name Counting Frame Time to Time to count Number of frame Color Rate counts count one one second counts in a 24- frame per second frame worth of frames...

  • Page 57: Figure 3-16: Dropframe Timecode With Respect To Real-Time Over A 1-Hour Period

    5700MSC-IP IP Network Grand Master Clock & Video Master Clock System Figure 3-16: Dropframe Timecode with Respect to Real-time over a 1-Hour Period Figure 3-17: Dropframe Timecode with Respect to Real-time over a 24-Hour Period Page - 47 Revision 0.2...

  • Page 58: Figure 3-18: Daily Time Jam Event For 29.97Hz Dropframe Timecode

    Figure 3-18: Daily Time Jam Event for 29.97Hz Dropframe Timecode Every time the daily jam event occurs, the 5700MSC-IP will attempt to bring the dropframe timecode as close to system time as possible, while optionally maintaining color frame alignment. The amount of frames adjusted depends on the error accumulated from the previous daily time jam.

  • Page 59: Figure 3-19: Dropframe Timecode With Respect To Real-Time Over One Week

    If the frequency reference of the 5700MSC-IP is set to GNSS, the time reference will also be forced to GNSS. The system phase reference is derived from GNSS time, but the system clock is set to UTC...

  • Page 60: Irig Timecode

    UTC-locked timecode to the PAL color frame. The system clock of the 5700MSC-IP is always set to UTC time. The PAL reference phase is tied to GNSS time which is not affected by leap seconds. Whenever a leap second occurs, UTC time counts an extra second, slowing it down.

  • Page 61: Network Time Protocol (Ntp)

    IRIG signal. The 5700MSC-IP can also be configured to the IRIG-B as a time reference. The time reference source must first be set to IRIG. The Irig Mode menu item selects which IRIG format to use as a reference and can also enable auto detection.

  • Page 62: Global Navigation Satellite System

    IP Network Grand Master Clock & Video Master Clock System If the 5700MSC-IP is not locked to the selected time reference, the LI_Alarm flag in all outgoing NTP packets will be set. This informs clients that the NTP reference clock in the 5700MSC-IP is not locked to a reference.

  • Page 63: Gnss Lock Operation

    In this mode, it can operate with just one satellite and still provide accurate timing to the 5700MSC-IP.The status of the GNSS lock progress can be monitored in the Lock Status and Inputs status screens.

  • Page 64: Gnss Re-Lock In Slow Mode

    3.5.4. GNSS Position Insertion into Timecode The 5700MSC-IP can insert the current position of the GNSS antenna into the user bits of the LTC and VITC outputs. This is controlled by the VitcLtc dte fmt menu item in the GENERAL root menu.

  • Page 65: Automatic Changeover Operation

    GPIs for both 5700MSC-IP units. The LTC input to the automatic changeover unit is internally split to both Bank A and Bank B 5700MSC-IP units. Similarly, the GPI inputs are split to both units, allowing any GPI trigger to affect both units simultaneously.
  • Page 66 5700MSC-IP IP Network Grand Master Clock & Video Master Clock System This page left intentionally blank Page - 56 Revision 0.2...

  • Page 67: Installation

    IP Network Grand Master Clock & Video Master Clock System INSTALLATION 4.1. REAR PANEL Figure 4-1 provides an illustration of the 5700MSC-IP rear panel. Figure 4-1: 5700MSC-IP Rear Panel 4.1.1. Reference Loop Connections The two REF IN LOOP HD-BNC connectors provide a reference loop input for black burst, tri-level, and 5MHz/10MHz signals.

  • Page 68: Ethernet Connections

    When the network is idle, the devices also send a link test signal to one another to verify link integrity. The 5700MSC-IP rear panel is fitted with two LEDs to monitor the Ethernet connection.

  • Page 69: Serial Port Connection

    COM port. Immediately behind the LED status display and to the right is the Front Panel Emulation port (J16), which allows a serial terminal with VT220 emulation to substitute for the front control panel on the 5700MSC-IP. Communication settings are 460,800 baud, no parity, 8 data bits and 1 stop bit. Pin #...

  • Page 70: Aux Connections (Available With 5700Msc-Ip+Aux Option)

    4.1.6. AUX Connections (available with 5700MSC-IP+AUX option) 4.1.7. GPIO, LTC Input, Secondary LTC Outputs These connections are available with the 5700MSC-IP+AUX option. A 15-pin female ‘D’ connector provides two general purpose inputs, two general purpose outputs, secondary LTC1 and LTC2 outputs, and an LTC input.

  • Page 71: Dars Out (Available With 5700Msc-Ip+Aux Option)

    SDI Test Generator 4 HD-BNC is labeled TG4 4.1.12. Power Connections The 5700MSC-IP has one or two (redundant supply is optional: 5700MSC-IP+2PS) auto-ranging power supplies that operate on either 95-125 or 185-260 volts AC at 50Hz or 60Hz. Power should be applied by connecting a 3-wire grounding type power supply cord to the power entry modules on the rear panel.

  • Page 72: M4 Grounding Stud

    MOUNTING AND COOLING The 5700MSC-IP is equipped with rack mounting ears and fits into a standard 19 inch by 1 ¾ inch (483 mm x 45 mm) rack space. An optional rear support kit is available for rear mounting in a rack.

  • Page 73: Connecting Two 5700Msc-Ip Units In Syncro Mode

    (such as changing a test pattern or phase offset) will also be applied to the slave. Additionally, the master 5700MSC-IP can be used as a time reference by the slave unit, with the time and date being transmitted...

  • Page 74: Figure 4-2: Pole Mounting The Smart Antenna

    5700MSC-IP IP Network Grand Master Clock & Video Master Clock System  When mounting two or more smart antennas they must be spaced at least 3 feet (1 meter) apart to prevent interference. Consider the length of the cable run when selecting the location. A 50 foot cable is supplied; however, longer cables are available on special order from the factory.

  • Page 75: Connecting The Gnss Smart Antenna To The 5700Msc-Ip

    The other end is fitted with a 9-pin male sub-miniature D connector and should be connected to the GNSS connector on the rear panel of the 5700MSC-IP. The pinout of the cable is shown in Table 4-6. If you require a longer cable, a 100 foot (Evertz part WA-T76), 200 foot cable (Evertz part WA-T10), 400 foot cable (Evertz part WA-T11), 800 foot cable (Evertz part WA-08) or 1200 foot cable (Evertz part WA-T12) may be ordered from the factory.

  • Page 76: System Start-Up

    5700MSC-IP IP Network Grand Master Clock & Video Master Clock System 9-pin Female 9-pin Male Cable D-Sub D-Sub Description Pair TX B + TX A - RX A - RX B + 1 PPS + 1 PPS - +12 V DC...

  • Page 77: Operation

    This section of the manual is currently under development and is subject to change. Missing heading and field descriptions will be added in the upcoming revision. The model 5700MSC-IP IP Network Grand Master Clock and Video Master Clock System combines the latest LSI technology with sophisticated embedded microcontroller firmware to provide a powerful, flexible, and upgradeable system.

  • Page 78: The Status Screens

    The status screens are still accessible even when the front panel is locked. The status screen list can be used to quickly locate the source of a fault within the 5700MSC-IP. By scrolling through the status screen list, any faults can be quickly identified. The status screens are described in detail below.
  • Page 79 5700MSC-IP IP Network Grand Master Clock & Video Master Clock System be replaced with a period ‘ ’. The fourth line, prefixed with “ ", shows the current timecode being read from VITC on the reference input. If the VITC input is lost, the time shown here will be replaced with “...
  • Page 80 ” and “ ” to (SCH>35) H-lock indicate that the 5700MSC-IP has fallen back to locking to horizontal sync only. If the burst phase cannot be measured reliably, it will display “ ”. unlockable The second line displays the detection of a 10MHz or 5MHz continuous wave 1080i ref with GPS (CW) frequency on the reference loop input.

  • Page 81: Panel Lock Function

    The Options Firmware status screen displays information about the installed Image will be options in the 5700MSC-IP as well as the current firmware version. added in upcoming The last line shows the current firmware version and build number that is installed...

  • Page 82: Front Panel Menu System

    In the bottom-right corner of the left LCD the frequency reference status is shown. When Ref Ok is displayed this means the currently selected frequency reference is present and the 5700MSC-IP has locked to it properly. This will be Ref unlk with a yellow background if the frequency reference is missing or the 5700MSC-IP is unable to lock to the supplied reference.

  • Page 83: Configuring The Input References

    5.3. CONFIGURING THE INPUT REFERENCES The INPUT menu is used to set up various items related to the input references of the 5700MSC-IP. The chart below shows the items available in the INPUT SETUP menu. Frequency Ref...

  • Page 84: Configuring The Frequency Reference

    5700MSC-IP units locked to 5MHz or 10MHz will not be the same. When set to Video the 5700MSC-IP will lock to a valid black burst or tri-level video signal applied to the reference loop inputs. The Genlock Range menu item is used to select the tolerance of the master oscillator lock range.
  • Page 85 Genlock Range is set to Narrow. If a large shift in the reference occurs while Slow lock mode is enabled, the outputs of the 5700MSC-IP may be out of phase for a long time while relocking. The ...

  • Page 86: Configuring The Time Inputs

    PTP domain assumes the role of active PTP Master, while all other potential masters enter into a passive state. The network interface on this 5700MSC-IP that is used to lock to a PTP Master will enter into Slave state. 5.3.2.2. Setting the VITC Reader Line...
  • Page 87 IP Network Grand Master Clock & Video Master Clock System 5.3.2.3. Setting the VITC Date This menu item is used to select how the 5700MSC-IP will decode date INPUT information from the user bits of the VITC inputs. It is only valid when the Time time reference source is set to VITC.

  • Page 88: Configuring The Jam Input

    5.3.2.6. Setting the Daily Jam Time for the Time Reference When the Lock Type is set to Daily, the 5700MSC-IP system time will run INPUT independently from the time reference and jam to it once a day. This menu Time item is ignored if the Lock Type is set to anything other than Daily.
  • Page 89 Performing a manual jam of the time reference will only be required when INPUT the time lock type is set to User or Never. In User mode the 5700MSC-IP Jam Input will warn whenever system time does not agree with the time reference.

  • Page 90: Configuring The Outputs

    IP Network Grand Master Clock & Video Master Clock System 5.4. CONFIGURING THE OUTPUTS The OUTPUT menu is used to configure the various outputs of the 5700MSC-IP. The chart below shows the items available in the OUTPUT menu. SYNC 1...

  • Page 91: Configuring The Sync Outputs

    5700MSC-IP IP Network Grand Master Clock & Video Master Clock System 5.4.1. Configuring the Sync Outputs 5.4.1.1. Selecting the Standard of the Sync Outputs This menu item sets the format of the sync output. All sync outputs are OUTPUT fully configurable.
  • Page 92 5700MSC-IP IP Network Grand Master Clock & Video Master Clock System 5.4.1.2. Configuring the VITC Generator for the Color Black Outputs 5.4.1.2.1. Enabling VITC on the Video Output This menu item controls whether Vertical Interval Time Code will be inserted OUTPUT into the vertical blanking interval of the sync output.
  • Page 93 5700MSC-IP IP Network Grand Master Clock & Video Master Clock System 5.4.1.2.5. Selecting When the VITC Time is Synchronized to the System Time This menu item allows the user to set the time of day when the VITC on the OUTPUT sync output will be synchronized to the system time.
  • Page 94 5700MSC-IP IP Network Grand Master Clock & Video Master Clock System 5.4.1.2.7. Synchronizing all the VITC, LTC, and Burn-In Clocks to System Time Immediately This menu item allows the user to synchronize both LTC outputs and all the OUTPUT VITC output times to system time immediately. Caution: This menu item is SYNC <1,6>...
  • Page 95 5700MSC-IP IP Network Grand Master Clock & Video Master Clock System 5.4.1.2.10. Enabling Daylight Saving Time for the VITC on the Sync Output OUTPUT This menu item allows the user to control whether Daylight Saving Time (DST) compensation will be applied to the VITC time on the sync output.

  • Page 96: Figure 5-2: Video Sync Phase Alignment In 59.94Hz Field Rate Systems

    5700MSC-IP IP Network Grand Master Clock & Video Master Clock System 750/59.94/P Video signal 1125/59.94/I Video signal 1122 1123 1124 1125 525/59.94/I Video signal Figure 5-2: Video Sync Phase Alignment in 59.94Hz Field Rate Systems 1125/50/I Video signal 1122 1123...
  • Page 97 5700MSC-IP IP Network Grand Master Clock & Video Master Clock System OUTPUT There are four menu items that are used to adjust the phase of the sync output. Only the black burst (NTSC-M and PAL-B) and HD tri-level output Sync <1,6>...

  • Page 98: General Configuration Items

    5700MSC-IP IP Network Grand Master Clock & Video Master Clock System 5.5. GENERAL CONFIGURATION ITEMS Menu description to be included in upcoming manual revision. 5.6. SNMP REMOTE CONTROL WITH VISTALINK Menu description to be included in upcoming manual revision. Page - 88...

  • Page 99: Upgrading The Firmware

    6.2.2. Replacing the Battery The 5700MSC-IP is fitted with a 3V 20mm diameter Lithium battery type CR2032. This battery is used to power the clock while power is removed from the unit. If the unit is not keeping time properly when it Page - 89 Revision 0.2...
  • Page 100 5700MSC-IP IP Network Grand Master Clock & Video Master Clock System is powered down, the battery should be replaced according to the procedure outlined in section 6.2.2.1. Before attempting to change the battery remove power from the 5700MSC-IP. CAUTION Danger of explosion if battery is incorrectly replaced. Replace only with the same or equivalent type.

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