Frequency Response Of A9 Input - HP 5340A Operating And Service Manual

Model 5340A
Theory of Operation
pulse is determined by R20 and C19. The multivibrator can be retriggered at any time during the
50 psec period to establish a new 50 psec pulse output. As long as the multivibrator is retrig-
which the circuit operates. Since U2 turns on and off for each cycle of its input, U3B will be
retriggered a s long as the signal at UZ(2) is sufficient to trigger comparator U2. When lock is
achieved, U3B(10) is high.
4-166. In the phase detector portion of A8, C16 couples the 20 kHz mixer signal through a high
impedance tie point to Q2. The high impedance tie point prevents humidity from discharging
the high impedance points and C18. Q2 is a n N-channel insulated gate field-effect transistor
(IGFET) used as a sampler, U3A generates 0.8 psec
the 20 kHz reference rate. The mixer signal from A l l is sampled by QZ to produce a charge
across C18. When the mixer signal is
the voltage across c 1 8 will be dc. When the loop is out of lock, the voltage across C18 is ac. The
frequency of this ac is the difference between the instantaneous values of the reference signal
and the mixer signal.
operation until the transfer loop SEARCH line goes high. This prevents false locks on har-
monics of 20 kHz such as 10 kHz, 40 kHz, etc.
4-167. Q1A and Q1B comprise a dc stabilized FET pair. Connecting Q1A and Q1B between + and
-
15 volts reduces the dc variation on the output of pin 6. CR2 and CR3 provide *lo volts for
proper operation of Q1A and Q1B. C20 through C23 filter out noise generated in the Zener diodes.
4-168. When phase lock is achieved, the dc output of Q1A and Q1B is amplified by DC Com-
ence frequency out of A l l which is phase coherent with the 20 kHz reference signal.
I
4-169. A9 D C AMPLlFIER/COMPENSATOR NO. 2 ASSEMBLY, 05340-60007
4-170. This assembly (Figure 8-15) performs two main functions. One of the functions provides
dc amplification and compensation required for the loop gain a n d frequency response charac-
teristics. The other function is to process the search and lock signals to develop a transfer loop
lock output to "tell" the counter circuits when the transfer loop is locked.
4-171. U1 is a low-noise operational amplifier which provides dc gain combined with a lag net-
work. The dc gain is variable from approximately 1 to 25 as determined by the ratio of R8 to R4
network consists of C5, C7, R11, and R8. At higher frequencies,
of feedback to reduce the gain. Figure 4-50 shows the frequency response of amplifier U1. The
4-40
at 20
U3A is disabled when U3B(10)
No. 2 A9. A9 drives the VCO 2 (A10) frequency to maintain a 20 kHz differ-
Figure 4-50. Frequency Response of A9 Input Amplifier
G A I N
,
,
:.I
FREQ
i
psec) pulses to gate Q2 on and off a t
is low, thereby preventing sampler
C5 and C7 increase the amount