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Model 5340A
Theory of Operation
Dual
D-Type Edge-Triggered Flip-Flop 1820-0077
4-1 7.
4-18. Figure 4-6. shows the logic diagram, outline drawing, and truth table for the 1820-0077.
As the truth table shows, the input data (D) is transferred to the output on the positive edge of the
clock pulse. Clock triggering is determined by a voltage level of the clock pulse and is not
directly related to the transition time of the positive going pulse. After the clock input threshold
level has been passed, the D input is locked out. A low at pin 4 or 10 will set the respective FF_ so
is low. A low
the Q is high and
high. The set and reset inputs will override all other inputs.
Figure 4-6. Dual D-Type Edge-Triggered Flip-Flop 1820-0077
T R U T H T A B L E
I
I
O U T P U T
Q
N O T E S :
1.
bit t i m e b e f o r e c l o c k p u l s e
2. t n + l
= bit
t i m e a f t e r c l o c k p u l s e
positive logic:
4-19. Four-Bit Binary Counter 1820-0099
4-20. The binary counter (Figure 4-7) consists of four
counter and a
counter. When pin 12 is connected to pin 1, the unit is a four-bit binary counter.
The input pulses are applied at pin 14 and simultaneous divisions of 2, 4, 8, and 16 are available
at the output pins
as shown in the truth table. Thus, the counter converts the input pulses
equivalent binary output. To reset the counter to zero, both pins 2 and 3 must be high.
4-21. Monostable Multivibrator 1820-0207
4-22. This IC (Figure 4-8) contains a retriggerable monostable multivibrator. The inputs are dc
level sensitive, i.e., triggering Qccurs on the rising or trailing edges of the input waveform. For
triggering on the rising edgej the input can be applied to pins 3 and 4. For trailing edge triggering,
pin 1 or 2 is used. The lqgic diagram shows the input logic. When the multivibrator is triggered,
the external resistor and capacitor determine the output pulse width; however, successive
inputs with a period shorter than the delay time will retrigger the multivibrator.
4-6
at pin 1 or 13 will reset the flip-flop so that
Flip-Flop)
( E a c h
1
.
Low input t o p r e s e t sets 0
Low
input t o clear sets 0 t o l o g i c a l
Preset a n d clear are i n d e p e n d e n t
2
2
CLOCKPRESET
ID
I
I
CLEAR
CLOCK PRESET
t o
l o g i c a l 1
0
of
c l o c k
J-K flip-flops connected to provide a
is low and Q is
Q
20
to a n
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Troubleshooting
