ST PSD4256G6V Manual
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ST PSD4256G6V Manual

ST PSD4256G6V Manual

Flash in-system programmable (isp) peripherals for 8-bit or 16-bit mcus
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Features
■
Dual bank Flash memories
– 8 Mbits of primary Flash memory (16
uniform sectors, 64 Kbytes)
– 512 Kbits of secondary Flash memory with
4 sectors
– Concurrent operation: read from one
memory while erasing and writing the other
– 256 kbits of SRAM
– PLD with macrocells
– Over 3000 gates of PLD: CPLD and DPLD
– CPLD with 16 output macrocells (OMCs)
and 24 input macrocells (IMCs)
– DPLD - user defined internal chip select
decoding
■
Seven I/O ports with 52 I/O pins
52 individually configurable I/O port pins that
can be used for the following functions:
– MCU I/Os
– PLD I/Os
– Latched MCU address output
– Special function I/Os
– l/O ports may be configured as open-drain
outputs
■
In-system programming (ISP) with JTAG
– Built-in JTAG compliant serial port allows
full-chip in-system programmability
– Efficient manufacturing allow easy product
testing and programming
– Use low cost FlashLINK™ cable with PC
■
Page register
– Internal page register that can be used to
expand the microcontroller address space
by a factor of 256
February 2009
Flash in-system programmable (ISP) peripherals
Rev 5
for 8-bit or 16-bit MCUs
80-lead Thin,
■
Programmable power management
■
High endurance
– 100,000 erase/write cycles of Flash
memory
– 1,000 erase/write cycles of PLD
– 15 year data retention
■
Single supply voltage
– 3 V (+20%/–10%)
■
Memory speed
– 100 ns Flash memory and SRAM access
time for V
= 3 V (+20%/–10%)
CC
– 90 ns Flash memory and SRAM access
time for V
= 3.3 V (+/–10%)
CC
■
Packages are ECOPACK
PSD4256G6V
LQFP80 (U)
Quad Flat
®
www.st.com
1/127
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Summary of Contents for ST PSD4256G6V

  • Page 1 PSD4256G6V Flash in-system programmable (ISP) peripherals for 8-bit or 16-bit MCUs Features ■ Dual bank Flash memories – 8 Mbits of primary Flash memory (16 uniform sectors, 64 Kbytes) – 512 Kbits of secondary Flash memory with 4 sectors – Concurrent operation: read from one memory while erasing and writing the other –...

  • Page 2: Table Of Contents

    Contents PSD4256G6V Contents Description ..........11 In-system programming (ISP) via JTAG .
  • Page 3 PSD4256G6V Contents 6.2.3 Memory operation ......... 33 Instructions .
  • Page 4 Contents PSD4256G6V 12.2 Memory select configuration for MCUs with separate program and data spaces 48 12.3 Configuration modes for MCUs with separate program and data spaces 49 12.3.1 Separate space modes ........49 12.3.2...
  • Page 5 PSD4256G6V Contents 18.12 80C31 ........... . 74 18.13 80C251 .
  • Page 6 Contents PSD4256G6V Power management ......... 92 20.1...
  • Page 7 PSD4256G6V List of tables List of tables Table 1. Pin names ............. . 13 Table 2.
  • Page 8 List of tables PSD4256G6V Table 49. Port data registers ............87 Table 50.
  • Page 9 PSD4256G6V List of figures List of figures Figure 1. Logic diagram ............13 Figure 2.
  • Page 10 List of figures PSD4256G6V Figure 49. WRITE timing diagram ........... 116 Figure 50.

  • Page 11: Description

    PSD4256G6V Description Description The PSD family of memory systems for microcontrollers (MCUs) brings in-system- programmability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of the peripheral functions found in MCU-based applications (8-bit or 16-bit), such as configurable memories, PLD logic, and I/O.

  • Page 12: In-Application Programming

    IAP, then back to program space when complete. PSDsoft™ PSDsoft, a software development tool from ST, guides you through the design process step- by-step making it possible to complete an embedded MCU design capable of ISP/IAP in just hours.

  • Page 13: Table 1. Pin Names

    PSD4256G6V Description Figure 1. Logic diagram V CC PA0-PA7 PB0-PB7 CNTL0- PC0-PC7 CNTL2 PD0-PD3 PSD4xxxGx AD0-AD15 PE0-PE7 PF0-PF7 RESET PG0-PG7 V SS AI04916 Table 1. Pin names Signal names Function PA0-PA7 Port-A PB0-PB7 Port-B PC0-PC7 Port-C PD0-PD3 Port-D PE0-PE7 Port-E...

  • Page 14: Figure 2. Lqfp80 Connections

    Description PSD4256G6V Table 1. Pin names (continued) Signal names Function Supply voltage Ground Figure 2. LQFP80 connections 60 CNTL1 59 CNTL0 58 PA7 57 PA6 56 PA5 55 PA4 54 PA3 53 PA2 V CC 52 PA1 51 PA0 50 GND...
  • Page 15 PSD4256G6V Description Table 2. LQFP80 pin description Type Description name This is the lower Address/Data port. Connect your MCU address or address/data bus according to the following rules: – If your MCU has a multiplexed address/data bus where the data is multiplexed with the lower address bits, connect AD0-AD7 to this port;...

  • Page 16: Table 2. Lqfp80 Pin Description

    Description PSD4256G6V Table 2. LQFP80 pin description (continued) Type Description name Active Low input. Resets I/O ports, PLD macrocells and some of the Configuration RESET registers and JTAG registers. Must be Low at Power-up. RESET also aborts any Flash memory program or erase cycle that is currently in progress.
  • Page 17 PSD4256G6V Description Table 2. LQFP80 pin description (continued) Type Description name PE0 pin of Port E. This port pin can be configured to have the following functions: CMOS – MCU I/O – standard output or input port; – Latched address output; and Open –...
  • Page 18 Description PSD4256G6V Table 2. LQFP80 pin description (continued) Type Description name These pins make up Port F. These port pins are configurable and can have the following functions: – MCU I/O – standard output or input port; – External Chip Select (ECS0-ECS7) outputs, or inputs to CPLD;...

  • Page 19: Figure 3. Psd Block Diagram

    PSD4256G6V Description Figure 3. PSD block diagram AI04917c 1. Additional address lines can be brought in to the device via Port A, B, C, D, or F. 19/127...

  • Page 20: Psd Architectural Overview

    PSD architectural overview PSD4256G6V PSD architectural overview PSD devices contain several major functional blocks. Figure 3: PSD block diagram shows the architecture of the PSD device family. The functions of each block are described briefly in the following sections. Many of the blocks perform multiple functions and are user configurable.

  • Page 21: Mcu Bus Interface

    PSD4256G6V PSD architectural overview MCU bus interface The PSD easily interfaces with most 8-bit or 16-bit MCUs, either with multiplexed or non- multiplexed address/data buses. The device is configured to respond to the MCU’s control pins, which are also used as inputs to the PLDs.

  • Page 22: Page Register

    PSD architectural overview PSD4256G6V Page register The 8-bit Page register expands the address range of the MCU by up to 256 times. The paged address can be used as part of the address space to access external memory and peripherals, or internal memory and I/O. The Page register can also be used to change the address mapping of the Flash memory blocks into different memory spaces for IAP.

  • Page 23: Development System

    (the address is given on the back page of this data sheet) or other distribution channels. PSDsoft directly supports two low cost device programmers form ST: PSDpro and FlashLINK (JTAG). Both of these programmers may be purchased through your local distributor/representative, or directly from our web site using a credit card.

  • Page 24: Figure 4. Psdsoft Development Tool

    Development system PSD4256G6V Figure 4. PSDsoft development tool Choose MCU and PSD Automatically configures MCU bus interface and other PSD attributes Define PSD Pin and Node Functions Point and click definition of PSD pin functions, internal nodes, and MCU system memory map...

  • Page 25: Psd Register Description And Address Offsets

    PSD4256G6V PSD register description and address offsets PSD register description and address offsets Table 6: Register address offset shows the offset addresses to the PSD registers relative to the CSIOP base address. The CSIOP space is the 256 bytes of address that is allocated by the user to the internal PSD registers.
  • Page 26 PSD register description and address offsets PSD4256G6V Table 6. Register address offset (continued) Port Port Port Port Port Port Port Register name Other Description Read-only – SRAM and primary memory Memory_ID0 size Read-only – Secondary memory type and Memory_ID1 size 1.

  • Page 27: Register Bit Definition

    PSD4256G6V Register bit definition Register bit definition All the registers of the PSD are included here for reference. Detailed descriptions of these registers can be found in the following sections. Table 7. Data-In registers - Ports A, B, C, D, E, F, and G...

  • Page 28: Table 14. Output Macrocells A Register

    Register bit definition PSD4256G6V Table 14. Output Macrocells A register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mcella 7 Mcella 6 Mcella 5 Mcella 4 Mcella 3 Mcella 2 Mcella 1 Mcella 0 1.

  • Page 29: Table 21. Jtag Enable Register

    PSD4256G6V Register bit definition Table 21. JTAG Enable register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 JTAGEnab not used not used not used not used not used not used not used 1.

  • Page 30: Table 25. Vm Register

    Register bit definition PSD4256G6V Table 25. VM register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 not used not used Peripheral FL_data Boot_data FL_code Boot_code SR_code mode (set to 0) (set to 0) 1.

  • Page 31: Detailed Operation

    PSD4256G6V Detailed operation Detailed operation As shown in Figure 3: PSD block diagram, the PSD consists of six major types of functional blocks: ● Memory blocks ● MCU Bus Interface ● I/O ports ● Power Management Unit (PMU) ● JTAG-ISP interface ●...

  • Page 32: Primary Flash Memory And Secondary Flash Memory Description

    Detailed operation PSD4256G6V Table 28. Memory block size and organization (continued) Primary Flash memory Secondary Flash memory SRAM Sector Sector Sector SRAM Sector size Sector size SRAM size number Select Select Select (Kbytes) (Kbytes) (bytes) signal signal signal FS13 FS14...

  • Page 33: Memory Operation

    PSD4256G6V Detailed operation 6.2.3 Memory operation The primary Flash memory and secondary Flash memory are addressed through the MCU Bus Interface. The MCU can access these memories in one of two ways: ● The MCU can execute a typical bus WRITE or READ operation just as it would if accessing a RAM or ROM device using standard bus cycles.
  • Page 34 Detailed operation PSD4256G6V (1)(2)(3)(4) Table 29. 16-bit instructions FS0-FS15 or Instruction CSBOOT0- Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 CSBOOT3 Unlock Bypass A0h@ PD@ PA (13) Program XXXXh Unlock Bypass 90h@ 00h@ (14)

  • Page 35: Table 29. 16-Bit Instructions

    PSD4256G6V Detailed operation Table 30. 8-bit instructions FS0-FS7 or Instruction CSBOOT0- Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 CSBOOT3 “Read” READ RD @ RA READ Main Flash AAh@ 55h@ 90h@ READ (3)(4) 555h...

  • Page 36: Instructions

    Instructions PSD4256G6V Instructions An instruction consists of a sequence of specific operations. Each received byte is sequentially decoded by the PSD and not executed as a standard WRITE operation. The instruction is executed when the correct number of bytes are properly received and the time between two consecutive bytes is shorter than the timeout period.

  • Page 37: Read

    PSD4256G6V Instructions READ Under typical conditions, the MCU may read the primary Flash memory, or secondary Flash memory, using READ operations just as it would a ROM or RAM device. Alternately, the MCU may use READ operations to obtain status information about a Program or Erase cycle that is currently in progress.

  • Page 38: Data Polling (Dq7) - Dq15 For Motorola

    Instructions PSD4256G6V Table 31. Status bits Data Toggle Erase Error Flag Polling Flag Time-out Status bits for Motorola 16-bit MCU DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 Data Toggle Erase Error Flag Polling Flag Time-out 1. X = Not guaranteed value, can be read either '1' or '0.' DQ15-DQ0 represent the Data Bus bits, D15-D0.

  • Page 39: Error Flag (Dq5) - Dq13 For Motorola

    PSD4256G6V Instructions The cycle is finished when two successive READs yield the same output data. ● The Toggle Flag bit (DQ6/DQ14) is effective after the fourth WRITE pulse (for a Program instruction) or after the sixth WRITE pulse (for an Erase instruction).

  • Page 40: Programming Flash Memory

    Programming Flash memory PSD4256G6V Programming Flash memory Flash memory must be erased prior to being programmed. The MCU may erase Flash memory all at once or by-sector. Although erasing Flash memory occurs on a sector or device basis, programming Flash memory occurs on a word basis.

  • Page 41: Data Toggle

    PSD4256G6V Programming Flash memory Figure 5. Data polling flowchart START READ DQ5 and DQ7 (DQ13 and DQ15) at Valid Even Address (DQ15) Data7 (Data15) (DQ13) READ DQ7 (DQ15) (DQ15) Data7 (Data15) Program Program or Erase or Erase Cycle failed Cycle is...

  • Page 42: Unlock Bypass

    Programming Flash memory PSD4256G6V since the Toggle Flag bit (DQ6/DQ14) may have changed simultaneously with the Error Flag bit (DQ5/DQ13) (see Figure The Error Flag bit (DQ5/DQ13) is set if either an internal timeout occurred while the embedded algorithm attempted to program, or if the MCU attempted to program a '1' to a bit that was not erased (not erased is logic '0').

  • Page 43: Figure 6. Data Toggle Flowchart

    PSD4256G6V Programming Flash memory Figure 6. Data toggle flowchart START READ DQ5 and DQ6 (DQ13 and DQ14) at Valid Even Address (DQ14) Toggle (DQ13) READ DQ6 (DQ14) (DQ14) Toggle Program Program or Erase or Erase Cycle failed Cycle is complete...

  • Page 44: Erasing Flash Memory

    Erasing Flash memory PSD4256G6V Erasing Flash memory Flash Bulk Erase The Flash Bulk Erase instruction uses six WRITE operations followed by a READ operation of the status register, as described in Table 29: 16-bit instructions Table 30: 8-bit instructions. If any byte of the Bulk Erase instruction is wrong, the Bulk Erase instruction aborts and the device is reset to the READ memory mode.

  • Page 45: Suspend Sector Erase

    PSD4256G6V Erasing Flash memory Suspend Sector Erase When a Sector Erase cycle is in progress, the Suspend Sector Erase instruction can be used to suspend the cycle by writing 0B0h to any even address when an appropriate Sector Select (FS0-FS15 or CSBOOT0-CSBOOT3) is High. (See...

  • Page 46: Specific Features

    Specific features PSD4256G6V Specific features 10.1 Flash Memory Sector Protect Each sector of primary or secondary Flash memory can be separately protected against Program and Erase cycles. Sector Protection provides additional data security because it disables all Program or Erase cycles. This mode can be activated (or deactivated) through the JTAG-ISP port or a device programmer.

  • Page 47: Sram

    PSD4256G6V SRAM SRAM The SRAM is enabled when SRAM Select (RS0) from the DPLD is High. SRAM Select (RS0) can contain up to three product terms, allowing flexible memory mapping. SRAM Select (RS0) is configured using PSDsoft. 47/127...

  • Page 48: Memory Select Signals

    Memory select signals PSD4256G6V Memory select signals The primary Flash Memory Sector Select (FS0-FS15), secondary Flash Memory Sector Select (CSBOOT0-CSBOOT3) and SRAM Select (RS0) signals are all outputs of the DPLD. They are defined using PSDsoft. The following rules apply to the equations for these signals: ●...

  • Page 49: Configuration Modes For Mcus With Separate Program And Data Spaces

    PSD4256G6V Memory select signals register by using PSDsoft to configure it for Boot-up and having the MCU change it when desired. Table 25 describes the VM register. Figure 7. Priority level of memory and I/O components Highest Priority Level 1...

  • Page 50: Figure 8. 8031 Memory Modules - Separate Space

    Memory select signals PSD4256G6V Figure 8. 8031 memory modules – separate space Primary Secondary SRAM DPLD Flash Flash Memory Memory CSBOOT0-3 FS0-FS15 PSEN AI04922 Figure 9. 8031 memory modules – combined space Primary Secondary SRAM DPLD Flash Flash Memory Memory...

  • Page 51: Page Register

    PSD4256G6V Page register Page register The 8-bit Page register increases the addressing capability of the MCU by a factor of up to 256. The contents of the register can also be read by the MCU. The outputs of the Page register (PGR0-PGR7) are inputs to the DPLD decoder and can be included in the Sector Select (FS0-FS15, CSBOOT0-CSBOOT3), and SRAM Select (RS0) equations.

  • Page 52: Memory Id Registers

    Memory ID registers PSD4256G6V Memory ID registers The 8-bit “read-only” memory status registers are included in the CSIOP space. The user can determine the memory configuration of the PSD device by reading the Memory ID0 and Memory ID1 registers. The content of the registers is defined as shown in...

  • Page 53: Plds

    PSD4256G6V PLDs PLDs The PLDs bring programmable logic functionality to the PSD. After specifying the logic for the PLDs using PSDsoft, the logic is programmed into the device and available upon Power- The PSD contains two PLDs: the Decode PLD (DPLD), and the Complex PLD (CPLD). The PLDs are briefly discussed in the next few paragraphs, and in more detail in the following sections.

  • Page 54: Figure 11. Pld Diagram

    PLDs PSD4256G6V Table 32. DPLD and CPLD Inputs (continued) Number of Input source Input name signals Page register PGR7-PGR0 Macrocell A feedback MCELLA.FB7-FB0 Macrocell B feedback MCELLB.FB7-FB0 Flash memory Program Status bit Ready/Busy 1. The address inputs are A19-A4 in 80C51XA mode.

  • Page 55: Decode Pld (Dpld)

    PSD4256G6V Decode PLD (DPLD) Decode PLD (DPLD) The DPLD, shown in Figure 12: DPLD logic array, is used for decoding the address for internal and external components. The DPLD can be used to generate the following decode signals: ● 8 Sector Select (FS0-FS15) signals for the primary Flash memory (three product terms each) ●...

  • Page 56: Complex Pld (Cpld)

    Complex PLD (CPLD) PSD4256G6V Complex PLD (CPLD) The CPLD can be used to implement system logic functions, such as loadable counters and shift registers, system mailboxes, handshaking protocols, state machines, and random logic. The CPLD can also be used to generate eight External Chip Select (ECS0-ECS7), routed to Port C or Port F.

  • Page 57: Output Macrocell (Omc)

    PSD4256G6V Complex PLD (CPLD) Figure 13. Macrocell and I/O port PRODUCT TERMS MCU ADDRESS / DATA BUS FROM OTHER MACROCELLS CPLD MACROCELLS I/O PORTS DATA LOAD LATCHED PT PRESET CONTROL MCU DATA IN ADDRESS OUT PRODUCT TERM I/O PIN ALLOCATOR...

  • Page 58: Product Term Allocator

    Complex PLD (CPLD) PSD4256G6V Table 33. Output macrocell port and data bit assignments Motorola 16- Maximum 16-bit MCU Output Port Native bit MCU for borrowed loading or macrocell assignment product terms loading or product terms reading reading McellA0 Port A0...

  • Page 59: Loading And Reading The Output Macrocells (Omc)

    PSD4256G6V Complex PLD (CPLD) 17.3 Loading and reading the output macrocells (OMC) The output macrocells (OMC) block occupies a memory location in the MCU address space, as defined by the CSIOP (see Figure 20 Figure 30 for examples of the basic connections between the PSD and some popular MCUs).

  • Page 60: Input Macrocells (Imc)

    Complex PLD (CPLD) PSD4256G6V Figure 14. CPLD output macrocell MASK REG. MACROCELL CS INTERNAL DATA BUS DIRECTION ALLOCATOR REGISTER ENABLE ( .OE ) PRESET ( .PR ) COMB/REG SELECT I/O PIN POLARITY SELECT PORT DRIVER CLEAR ( .RE ) PROGRAMMABLE...

  • Page 61: External Chip Select

    PSD4256G6V Complex PLD (CPLD) Input macrocells (IMC) can use Address Strobe (ALE/AS, PD0) to latch address bits higher than A15. Any latched addresses are routed to the PLDs as inputs. Input macrocells (IMC) are particularly useful with handshaking communication applications where two processors pass data back and forth through a common mailbox.

  • Page 62: Figure 16. External Chip Select Signal

    Complex PLD (CPLD) PSD4256G6V Figure 16. External Chip Select signal Port C or Port F ENABLE (.OE) PT DIRECTION REGISTER PORT PIN ECS PT To Port C or F POLARITY AI04927 Figure 17. Handshaking communication using input macrocells SLAVE– CS SLAVE–READ...

  • Page 63: Mcu Bus Interface

    PSD4256G6V MCU bus interface MCU bus interface The “no-glue logic” MCU bus interface block can be directly connected to most popular 8-bit and 16-bit MCUs and their control signals. Key MCUs, with their bus types and control signals, are shown in...

  • Page 64: Psd Interface To A Multiplexed Bus

    MCU with a multiplexed bus and a PSD4256G6V. The ADIO port on the PSD is connected directly to the MCU address/data bus. Address Strobe (ALE/AS, PD0) latches the address signals internally. Latched addresses can be brought out to Port E, F or G.

  • Page 65: Psd Interface To A Non-Multiplexed, 16-Bit Bus

    MCU with a 16-bit, non-multiplexed bus and a PSD4256G6V. The address bus is connected to the ADIO port, and the data bus is connected to Ports F and G. Ports F and G are in tri-state mode when the PSD is not accessed by the MCU.

  • Page 66: 16-Bit Mcu Bus Interface Examples

    MCU bus interface PSD4256G6V 18.4 16-bit MCU bus interface examples Figure 20 Figure 25 show examples of the basic connections between the µPSD3200 Family and some popular MCUs. The µPSD3200 Family Control input pins are labeled as to the MCU function for which they are configured. The MCU bus interface is specified using PSDsoft.

  • Page 67: 80C196 And 80C186

    PSD4256G6V MCU bus interface 18.5 80C196 and 80C186 Figure 20, the Intel 80C196 MCU, which has a 16-bit multiplexed address/data bus, is shown connected to a µPSD3200 Family. The READ Strobe (RD, CNTL1), and WRITE Strobe (WR/WRL, CNTL0) signals are connected to the CNTL pins.

  • Page 68: Mc683Xx And Mc68Hc16

    MCU bus interface PSD4256G6V 18.6 MC683xx and MC68HC16 Figure 21 shows a MC68331 with a 16-bit non-multiplexed data bus and 24-bit address bus. The data bus from the MC68331 is connected to Port F (D0-D7) and Port G (D8-D15). The SIZ0 and A0 inputs determine the high/low byte selection.

  • Page 69: 80C51Xa

    PSD4256G6V MCU bus interface 18.7 80C51XA The Philips 80C51XA MCU has a 16-bit multiplexed bus with burst cycles. Address bits (A3- A1) are not multiplexed, while (A19-A4) are multiplexed with data bits (D15-D0). The µPSD3200 Family supports the 80C51XA burst mode. The WRH signal is connected to PD3, and WHL is connected to CNTL0.

  • Page 70: Figure 23. Interfacing The Psd With An H83/2350

    MCU bus interface PSD4256G6V 18.8 H8/300 Figure 23 shows an Hitachi H8/2350 with a 16-bit non-multiplexed data bus, and a 24-bit address bus. The H8 data bus is connected to Port F (D0-D7) and Port G (D8-D15). The WRH signal is connected to PD3, and WHL is connected to CNTL0. The RD signal is connected to CNTL1.

  • Page 71: Mmc2001

    PSD4256G6V MCU bus interface 18.9 MMC2001 The Motorola MCORE MMC2001 MCU has a MOD input pin that selects internal or external boot ROM. The PSD can be configured as the external Flash boot ROM or as extension to the internal ROM (see Figure 24).

  • Page 72: Figure 24. Interfacing The Psd With An Mmc2001

    MCU bus interface PSD4256G6V Figure 24. Interfacing the PSD with an MMC2001 A[19:16] A[19:16] AD[15:0] VCC_BAR VCC_BAR ADIO[15:0] Infineon C167CR ADIO0 XTAL1 ADIO1 ADIO2 ADIO3 CRYSTAL ADIO4 XTAL2 ADIO5 ADIO6 P3.0/T0IN ADIO7 P3.1/T6OUT P3.2/CAPIN ADIO8 P3.3/T3OUT ADIO9 AD10 P3.4/T3EUD AD10...

  • Page 73: C16X Family

    PSD4256G6V MCU bus interface 18.10 C16x family The PSD supports Infineon’s C16X family of MCUs (C161-C167) in both the multiplexed and non-multiplexed bus configuration. In Figure 25, the C167CR is shown connected to the PSD in a multiplexed bus configuration. The control signals from the MCU are WR, RD, BHE and ALE, and are routed to the corresponding PSD pins.

  • Page 74: 8-Bit Mcu Bus Interface Examples

    MCU bus interface PSD4256G6V 18.11 8-bit MCU bus interface examples Figure 26 Figure 30 show examples of the basic connections between the PSD and some popular MCUs. The PSD Control input pins are labeled as to the MCU function for which they are configured.

  • Page 75: 80C251

    PSD4256G6V MCU bus interface 18.13 80C251 The Intel 80C251 MCU features a user-configurable bus interface with four possible bus configurations, as shown in Table 40. The first configuration is 80C31-compatible, and the bus interface to the PSD is identical to that shown in Figure 26.

  • Page 76: Figure 27. Interfacing The Psd With The 80C251, With One Read Input

    MCU bus interface PSD4256G6V Figure 27. Interfacing the PSD with the 80C251, with one READ Input 80C251SB P0.0 ADIO0 A16 1 P1.0 P0.1 ADIO1 P1.1 P0.2 ADIO2 P1.2 A17 1 P0.3 ADIO3 P1.3 P0.4 ADIO4 P1.4 ADIO5 P0.5 P1.5 P0.6 ADIO6 P1.6...

  • Page 77: 80C51Xa

    PSD4256G6V MCU bus interface 18.14 80C51XA The Philips 80C51XA MCU family supports an 8- or 16-bit, multiplexed bus that can have burst cycles. Address bits (A3-A0) are not multiplexed, while (A19-A4) are multiplexed with data bits (D15-D0) in 16-bit mode. In 8-bit mode, (A11-A4) are multiplexed with data bits (D7-D0).

  • Page 78: 68Hc11

    MCU bus interface PSD4256G6V 18.15 68HC11 Figure Figure 30 shows a bus interface to a 68HC11 where the PSD is configured in 8-bit, multiplexed mode with E and R/W settings. The DPLD can be used to generate the READ and WR signals for external devices.

  • Page 79: I/O Ports

    PSD4256G6V I/O ports I/O ports There are seven programmable I/O ports: Ports A, B, C, D, E, F and G. Each port pin is individually user configurable, thus allowing multiple functions per port. The ports are configured using PSDsoft or by the MCU writing to on-chip registers in the CSIOP space.

  • Page 80: Port Operating Modes

    I/O ports PSD4256G6V 19.2 Port operating modes The I/O ports have several modes of operation. Some modes can be defined using PSDsoft, some by the MCU writing to the registers in CSIOP space, and some by both. The modes that can only be defined using PSDsoft must be programmed into the device and cannot be changed unless the device is reprogrammed.

  • Page 81: Mcu I/O Mode

    PSD4256G6V I/O ports 19.3 MCU I/O mode In the MCU I/O mode, the MCU uses the PSD ports to expand its own I/O ports. By setting up the CSIOP space, the ports on the PSD are mapped into the MCU address space. The...

  • Page 82: Table 41. Port Operating Modes

    I/O ports PSD4256G6V Table 41. Port operating modes Port mode Port A Port B Port C Port D Port E Port F Port G MCU I/O PLD I/O McellA output McellB outputs Additional Ext. CS outputs PLD Inputs Yes (A7 – 0) Address Out Yes (A7 –...

  • Page 83: Address In Mode

    PSD4256G6V I/O ports Table 43. I/O port latched address output assignments Port E Port E Port F Port F Port G Port G (PE3-PE0) (PE7-PE4) (PF3-PF0) (PF7-PF4) (PG3-PG0) (PG7-PG4) Address Address Address Address 80C51XA a7-a4 a7-a4 a11-a8 a15-a12 Address Address...

  • Page 84: Jtag In-System Programming (Isp)

    I/O ports PSD4256G6V Figure 32. Peripheral I/O mode PSEL0 PSEL PSEL1 D0 - D7 VM REGISTER BIT 7 PA0 - PA7 DATA BUS AI02886 19.9 JTAG in-system programming (ISP) Port E is JTAG compliant, and can be used for in-system programming (ISP). You can multiplex JTAG operations with other functions on Port E because in-system programming (ISP) is not performed during normal system operation.

  • Page 85: Control Register

    PSD4256G6V I/O ports Configuration registers (PCR), shown in Table 44, are used for setting the port configurations. The default Power-up state for each register in Table 44 is 00h. 19.12 Control register Any bit reset to '0' in the Control register sets the corresponding port pin to MCU I/O mode, and a 1 sets it to Address Out mode.

  • Page 86: Port Data Registers

    I/O ports PSD4256G6V Table 46. Port pin Direction Control, Output Enable P.T. Defined Direction register bit Output Enable P.T. Port pin mode Input Output Output Output Table 47. Port direction assignment example Bit 7 Bit 6 Bit 5 Bit 4...

  • Page 87: Output Macrocells (Omc)

    PSD4256G6V I/O ports 19.18 Output macrocells (OMC) The CPLD output macrocells (OMC) occupy a location in the MCU’s address space. The MCU can read the output of the output macrocells (OMC). If the Mask Macrocell register bits are not set, writing to the macrocell loads data to the macrocell flip-flops. See Section 19: ports.

  • Page 88: Ports A, B And C - Functionality And Structure

    I/O ports PSD4256G6V 19.22 Ports A, B and C – Functionality and Structure Ports A, B, and C have similar functionality and structure, as shown in Figure 33. The ports can be configured to perform one or more of the following functions: ●...

  • Page 89: Port D - Functionality And Structure

    PSD4256G6V I/O ports 19.23 Port D – functionality and structure Port D has four I/O pins. See Figure 34. Port D can be configured to perform one or more of the following functions: ● MCU I/O mode ● CPLD Input – direct input to the CPLD, no input macrocells (IMC) ●...

  • Page 90: Port E - Functionality And Structure

    I/O ports PSD4256G6V 19.24 Port E – functionality and structure Port E can be configured to perform one or more of the following functions (see Figure 35): ● MCU I/O mode ● In-system programming (ISP) – JTAG port can be enabled for programming/erase of the PSD device.

  • Page 91: Figure 35. Port E, F, And G Structure

    PSD4256G6V I/O ports Figure 35. Port E, F, and G structure DATA OUT Register DATA OUT ADDRESS ADDRESS PORT Pin A [ 7:0 ] OR A [ 15:8 ] OUTPUT Ext. CS (Port F) READ MUX OUTPUT SELECT DATA IN...

  • Page 92: Power Management

    Power management PSD4256G6V Power management The PSD device offers configurable power saving options. These options may be used individually or in combinations, as follows: ● All memory blocks in a PSD (primary Flash memory, secondary Flash memory, and SRAM) are built with power management technology. In addition to using special silicon design methodology, power management technology puts the memories into Standby mode when address/data inputs are not changing (zero DC current).

  • Page 93: Automatic Power-Down (Apd) Unit And Power-Down Mode

    PSD4256G6V Power management 20.1 Automatic power-down (APD) Unit and Power-down mode The APD Unit, shown in Figure 36, puts the PSD into Power-down mode by monitoring the activity of Address Strobe (ALE/AS, PD0). If the APD Unit is enabled, as soon as activity on Address Strobe (ALE/AS, PD0) stops, a four bit counter starts counting.

  • Page 94: Other Power Saving Options

    Power management PSD4256G6V Figure 36. APD unit APD EN PMMR0 BIT 1=1 TRANSITION DETECTION DISABLE BUS INTERFACE Secondary Flash Memory Select COUNTER Primary Flash RESET Memory Select EDGE DETECT SRAM Select CLKIN POWER DOWN (PDN) Select DISABLE Primary and Secondary...

  • Page 95: Psd Chip Select Input (Csi, Pd2)

    PSD4256G6V Power management 20.5 PSD Chip Select Input (CSI, PD2) PD2 of Port D can be configured in PSDsoft as PSD Chip Select Input (CSI). When Low, the signal selects and enables the internal primary Flash memory, secondary Flash memory, SRAM, and I/O blocks for READ or WRITE operations involving the PSD.

  • Page 96: Input Control Signals

    Power management PSD4256G6V 20.7 Input control signals The PSD provides the option to turn off the address input (A7-A0) and input control signals (CNTL0, CNTL1, CNTL2, Address Strobe (ALE/AS, PD0) and WRITE-Enable High-byte (WRH/DBE, PD3)) to the PLD to save AC power consumption. These signals are inputs to the PLD AND Array.

  • Page 97: Reset Timing And Device Status At Reset

    PSD4256G6V RESET timing and device status at RESET RESET timing and device status at RESET 21.1 Power-on RESET Upon Power-up, the PSD requires a Reset (RESET) pulse of duration t (minimum NLNH-PO 1ms) after V is steady. During this period, the device loads internal configurations, clears some of the registers and sets the Flash memory into Operating mode.

  • Page 98: Table 53. Status During Power-On Reset, Warm Reset, And Power-Down Mode

    RESET timing and device status at RESET PSD4256G6V Table 53. Status during Power-on RESET, Warm RESET, and Power-down mode Port configuration Power-on RESET Warm Reset Power-down mode MCU I/O Input mode Input mode Unchanged Valid after internal PSD Depends on inputs to PLD...

  • Page 99: In-Circuit Programming Using The Serial Interface

    PSD4256G6V In-circuit programming using the serial interface In-circuit programming using the serial interface The JTAG serial interface on the PSD can be enabled on Port E (see Table 54). All memory blocks (primary Flash memory and secondary Flash memory), PLD logic, and PSD Configuration bits may be programmed through the JTAG-ISC Serial Interface.

  • Page 100: Jtag Extensions

    (RESET) will prevent or interrupt JTAG operations if the JTAG Enable register (as shown in Table 21) is used to enable the JTAG pins. The PSD supports JTAG In-System-Programmability (ISP) commands, but not Boundary Scan. ST’s PSDsoft software tool and FlashLINK JTAG programming cable implement the JTAG In-System-Programmability (ISP) commands. 22.2 JTAG extensions TSTAT and TERR are two JTAG extension signals enabled by a JTAG command received over the four standard JTAG pins (TMS, TCK, TDI, and TDO).
  • Page 101 PSD4256G6V In-circuit programming using the serial interface Table 54. JTAG port signals Port E pin JTAG signals Description mode Select Clock Serial Data In Serial Data Out TSTAT Status TERR Error Flag 101/127...

  • Page 102: Initial Delivery State

    PSD4256G6V Initial delivery state When delivered from ST, the PSD device has all bits in the memory and PLDs set to 1. The PSD Configuration register bits are set to 0. The code, configuration, and PLD logic are loaded using the programming procedure. Information for programming the device is available directly from ST.

  • Page 103: Maximum Rating

    PSD4256G6V Maximum rating Maximum rating Stressing the device above the rating listed in the Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied.

  • Page 104: Dc And Ac Parameters

    DC and AC parameters PSD4256G6V DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device: ● DC electrical specification ● AC timing specification – PLD timing Combinatorial timing Synchronous Clock mode...

  • Page 105: Cc = 3.0 V (With Turbo Mode On)

    PSD4256G6V DC and AC parameters Table 56. Example of PSD typical power calculation at V = 3.0 V (with Turbo mode On) Conditions Highest composite PLD input frequency (Freq PLD) = 8MHz MCU ALE frequency (Freq ALE) = 4MHz % Flash memory Access...

  • Page 106: Cc = 3.0V (With Turbo Mode Off)

    DC and AC parameters PSD4256G6V Table 57. Example of PSD typical power calculation at V = 3.0V (with Turbo mode Off) Conditions Highest composite PLD input frequency (Freq PLD) = 8MHz MCU ALE frequency (Freq ALE) = 4MHz % Flash memory Access...

  • Page 107: Table 58. Operating Conditions

    PSD4256G6V DC and AC parameters Table 58. Operating conditions Symbol Parameter Min. Max. Unit Supply voltage Ambient operating temperature (industrial) –40 °C Ambient operating temperature (commercial) °C Table 59. AC signal letters for PLD timing Symbol Signal Address input CEout output...

  • Page 108: Table 62. Capacitance

    DC and AC parameters PSD4256G6V Table 62. Capacitance Symbol Parameter Test condition Typ. Max. Unit Input capacitance (for input pins) = 0 V Output capacitance (for input/output pins) = 0 V Capacitance (for CNTL2/V = 0 V 1. Sampled only, not 100% tested.

  • Page 109: Table 63. Dc Characteristics

    PSD4256G6V DC and AC parameters Table 63. DC characteristics Symbol Parameter Conditions Min. Typ. Max. Unit High level input voltage 2.7 V < V < 3.6 V 0.7V +0.5 Low level input voltage 2.7 V < V < 3.6 V –0.5...

  • Page 110: Table 64. Cpld Combinatorial Timing

    DC and AC parameters PSD4256G6V Figure 43. Input to Output Disable / Enable INPUT INPUT TO OUTPUT ENABLE/DISABLE AI02863 Figure 44. Asynchronous RESET / Preset tARPW RESET/PRESET INPUT tARP REGISTER OUTPUT AI02864 Table 64. CPLD combinatorial timing Turbo Symbol Parameter...

  • Page 111: Table 65. Cpld Macrocell Synchronous Clock Mode Timing

    PSD4256G6V DC and AC parameters Table 65. CPLD macrocell synchronous Clock mode timing Turbo Symbol Parameter Conditions Unit aloc Maximum frequency external feedback 1/(t 22.7 Maximum frequency internal feedback 1/(t –10) 29.4 Maximum frequency pipelined data 1/(t 45.0 Input setup time...
  • Page 112 DC and AC parameters PSD4256G6V Table 66. CPLD macrocell asynchronous Clock mode timing (continued) Turbo Symbol Parameter Conditions Unit aloc Clock to output delay + 20 CPLD array delay Any macrocell Minimum clock period MINA CNTA 112/127...

  • Page 113: Table 67. Input Macrocell Timing

    PSD4256G6V DC and AC parameters Figure 47. Input macrocell timing (Product Term Clock) PT CLOCK INPUT OUTPUT AI03101 Table 67. Input macrocell timing Turbo Symbol Parameter Conditions Unit aloc Input setup time Input hold time + 20 NIB input high time...

  • Page 114: Table 68. Read Timing

    DC and AC parameters PSD4256G6V Figure 48. READ timing diagram t AVLX t LXAX ALE/AS t LVLX A /D ADDRESS DATA MULTIPLEXED VALID VALID t AVQV ADDRESS ADDRESS NON-MULTIPLEXED VALID DATA DATA NON-MULTIPLEXED VALID t SLQV t RLQV t RHQX...
  • Page 115 PSD4256G6V DC and AC parameters Table 68. READ timing (continued) Turbo Symbol Parameter Conditions Unit R/W setup time to enable THEH R/W hold time after enable ELTL Address input valid to address output delay AVPV 1. Any input used to select an internal PSD function.

  • Page 116: Table 69. Write Timing

    DC and AC parameters PSD4256G6V Figure 49. WRITE timing diagram t AVLX t LXAX ALE / AS t LVLX A /D ADDRESS DATA MULTIPLEXED VALID VALID t AVWL ADDRESS ADDRESS NON-MULTIPLEXED VALID DATA DATA NON-MULTIPLEXED VALID t SLWL t DVWH...
  • Page 117 PSD4256G6V DC and AC parameters Table 69. WRITE timing (continued) Symbol Parameter Conditions Unit Data valid to port output valid using macrocell register (2)(5) DVMV preset/clear Address input valid to address output delay AVPV WR valid to port output valid using macrocell register...

  • Page 118: Table 70. Port F Peripheral Data Mode Read Timing

    DC and AC parameters PSD4256G6V Figure 50. Peripheral I/O READ timing diagram ALE/AS A /D BUS ADDRESS DATA VALID t AVQV (PF) t SLQV ( PF) t RLQV (PF) t QXRH ( PF) t RHQZ ( PF) t RLRH (PF)

  • Page 119: Table 71. Port F Peripheral Data Mode Write Timing

    PSD4256G6V DC and AC parameters Figure 51. Peripheral I/O WRITE timing diagram ALE /AS ADDRESS DATA OUT A / D BUS tWHQZ (PF) tWLQV (PF) tDVQV (PF) PORT F DATA OUT AI05741 Table 71. Port F peripheral data mode WRITE timing...

  • Page 120: Table 73. Reset (Reset) Timing

    DC and AC parameters PSD4256G6V Figure 52. Reset (RESET) timing diagram (min) t NLNH t NLNH-PO t OPR t NLNH-A t OPR Power-On Reset Warm Reset RESET AI02866b Table 73. Reset (RESET) timing Symbol Parameter Conditions Unit RESET active low time...

  • Page 121: Table 75. Isc Timing

    PSD4256G6V DC and AC parameters Figure 53. ISC timing diagram ISCCH ISCCL ISCPSU ISCPH TDI/TMS ISCPZV ISCPCO ISC OUTPUTS/TDO ISCPVZ ISC OUTPUTS/TDO AI02865 Table 75. ISC timing Symbol Parameter Conditions Unit Clock (TCK, PC1) frequency (except for PLD) ISCCF Clock (TCK, PC1) high time (except for PLD)

  • Page 122: Package Mechanical Information

    Package mechanical information PSD4256G6V Package mechanical information In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com.

  • Page 123: Table 76. Lqfp80 - 80-Lead Plastic Thin, Quad, Flat Package Mechanical Data

    PSD4256G6V Package mechanical information Table 76. LQFP80 – 80-lead plastic thin, quad, flat package mechanical data (continued) inches Symb 0.600 0.45 0.750 0.0240 0.0180 0.0300 1.000 – – 0.0390 – – 0° 7° 0° 7° – – 0.080 – –...

  • Page 124: Part Numbering

    I = –40 to 85°C (Industrial) Option T = Tape & Reel Packing For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. 124/127...

  • Page 125: Appendix A Pin Assignments

    PSD4256G6V PIn assignments Appendix A PIn assignments Table 78. LQFP80 pin connections num. assignments num. assignments num. assignments num. assignments AD10 AD11 AD12 AD13 AD14 RESET CNTL0 AD15 CNTL2 CNTL1 125/127...

  • Page 126: Revision History

    Revision history PSD4256G6V Revision history Table 79. Document revision history Date Revision Changes 06-Aug-2001 Document written 13-Sep-01 Package mechanical data updated Added 100 ns specification; removed 90 and 120 ns specifications. 14-Dec-01 Updated AC specification and Port C and F functions...
  • Page 127 No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.

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