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9-6. TC51128AFL-80 CMOS
PSEUDO-STATIC RAM (131,072
WORDS X 8 BITS)
General
The TC518128AFL is a single 5Voperated 131,072 words x 8 bits
pseudo-static RAM. It realized a large capacity, high speed, and low
power dissipation by a combination of single transistor type dynamic
memory cell
and peripheral CMOS static circuit
With the
TC518128AFL,
auto
refresh and self-refresh can ea§ily be achieved
with -RFSH input, and, similar as an asyne static RAM, the R/W input
is accepted at a low to high transition of RNI, which enhances easier
interface
with
microcomputer.
The TC518128AFL is pin compatible with 1 MB static RAM (JEDEC
standard) and a package of 0.3" wide, 32-pin SOP minHlat static
package is used.
Refresh can be done by selecting 512 address (AO-A8) within 8ms.
Features
tCEA
Access time
tOEA
OE
access time
tRC
Cycle time
PD
Operating power dissipation
Self~refresh
current
Large capacity:, 131 ,072 words x 8 bits
High speed, low power dissipation
Single 5V supply: 5V±10%
Auto refresh possible
by
the internal counter
Self-refresh possible by the internal counter
All
input/output are
TTL compatible
512 refresh cycle/8ms
Adoption of the auto refresh power down function
Pin compatible with 1 M static RAM (JEDEC standard)
• 32-pin mini-flat package
Pin configuration
32
VDD
3i
A15
A14
30
CE2
29
RIW
28
A13
A6
27
A8
AS
26
A9
25
All
OE
A2
Al0
Al
CEl
AD
Iloa
1101
1107
1102
1106
1103
1/05
GND
1104
~--
Fig. 9-10
80ns
35n5
130ns
385mW
1mAl220~A
-73-
Pin name
AO-A16
R!W
OE
RFSH
CIT,
CE2
1/01-1/08
VDD
GND
Block diagram
CIT
CE2
RIW
-
P C-6220
Address input
Read/write input
Output enable input
Refresh input
Chip enable input
Data input/output
Power supply
GND
8
Column decoder
€
~
8
Sense amp
8 8
~
1/0
gate
~
.~
~
1101
0
-I/OB
512
Memory array
€
512x256x8
Jg
B
~
8
~
0
~
0
Fig. 9-11
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