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9-4. 82C455 VGA FLAT PANEL/CRT
CONTROLLER DATA SHEET
•
VGA~Compatible
flat panel controller optimized for laptop
com~
puter applications.
•
Supports CRT, LCD, Plasma and Electro-Luminescent displays of
varying resolutions.
•
Single chip implementation tightly couples to the CHIPS/250 and
CHIPS/2aD and interiaces with 8 and 16 bit PC bus and MeA (an
interface compatible with the MicroChanneI™).
•
Up
to
40 MHz dot clock speed for graphics and text modes.
•
Can utilize an external palette OAC with up to 16 million colors.
•
Provides intelligent backward compatibility to the EGA,
eGA,
Hercules
TM,
and MDA on Flat Panel displays.
The 82C455 Graphics Controller provides a complete solution for
implementing a Video Graphics Array-compatible controller. The
82C455 is supplied in a 144-pin PFP package.
It
can
be
used in 8
and 16-bit PC bus and in 16-bit MCA bus environments.
Display Types Supported
CGA, EGA, MDA, Multifrequency, IBM PS/2™ and other monitors
can be used. The choice of fiat panel displays includes EL, plasma,
as well as single panel/single drive, dual panel/single drive and dual
panel/double drive LCDs. Both gray scale and monochrome panels
are supported; a proprietary frame rate control algorithm provides
gray scale capability on monochrome panels.
CHIPS/250 and CHIPS/280 Interface
The 82C455 interfaces directly to the CHIPS/250 and CHIPS/280,
providing a simple, cost-effective solution for PS/2 compatible sys-
tems, When used with one of these CHIPSets®, the 82C455 can
execute FAST memory cycles at a speed greater than that normally
available on the MCA bus.
Backward Compatibility
The 82C455 is compatible with IBM's EGA, CGA and MDA, in addi-
tion to offering a Hercules monochrome-graphics-compatible mode.
On-chip compensation registers permit software designed for low
resolution displays to utilize the entire screen area on a flat panel with
higher resolution.
Hardware Support for Context Switching
Multitasking and windowing environments can be implemented easily
since all internal registers of the 82C455 can be read and written.
DATA
82C455
ADDRESS
CONTROL
L-~-'1Jl'
Fig. 9-7 82C455 System Implementation
82C455 Functional Description
TO
CRT
TO
FLAT
PANEL
The 82C455 offers a complete solution for implementing a
VGAlMCGAlEGAlCGAlMDAlHercules-compatible display system. By
-
P C-6220
flat panel used in an implementation. Mode initialization is supported
at the BIOS and register levels. ensuring compatibility with all applica-
tion software. The 256 Kbytes of display memory size is comprised of
8 64K*4 DRAMs. Display memory refresh is controlled by the
82C455; it is transparent to the CPU.
For support of multitasking environments and context switching, the
entire state of the 82C455 (internal registers and latches) is readable
and writeable. This feature is 100% compatible to IBM's VGA.
The 82C455 directly interfaces to 8-bit PC and PCIXT, 16-bit PC/AT
and 8 or 16-bit MCA buses. All operations necessary to ensure proper
operation in these various environments are handled in a fashion
transparent to the CPU. These include internal decoding of all
memory and
1/0
addresses, bus width translations and generation of
the necessary control signals.
The 82C455 contains 16 color palette registers. It also interfaces
directly to an external Inmos G171 (or compatible) color palette and
D/A
converter. Like the VGA,
it is capable of display resolutions of
640*480 with 16 on-screen colors (internal palette) and 320*200 with
256 on-screen colors from an external palette of 256 thousand (or 16
million) colors. The 82C455 can also be programmed for higher
resolutions up to 800*600 in 16 colors.
The 82C455 integrates four different modules as follows:
Graphics Controller
The Graphics Controller interfaces the 8 or 16-bit CPU data bus to
the 32-bit data bus used by the four planes (Maps) of display
memory. It also latches and supplies to the Attribute Controller display
memory data for use in refreshing the screen image. For text modes
this data is supplied in parallel form (character generator data and an
attribute code); for graphics modes it is converted to serial form (one
bit from each of four bytes form a single pixel). The Graphics Control-
ler also performs anyone of several types of logical operations on
data while reading it from or writing it to display memory or the CPU
data bus.
Sequencer
The Sequencer generates all CPU and display memory timing sig-
nals. It controls CPU access of display memory by inserting cycles
dedicated to CPU access and contains mask registers which can
prevent writes of individual display memory planes.
Attribute Controller
The Attribute Controller generates the 4-bit-wide video data stream
used to refresh the display. This is created in text modes from a font
pattern and an attribute code which pass through a parallel to serial
conversion. In graphics modes. the display memory contains the 4-bit
pixel data. In text and graphic modes the 4-bit pixel data acts as an
index into a set of internal palette registers which generate a 6-bit
stream. Two additional bits of color data are added if 256-color mode
is enabled. Text blink, underline and cursor are also the responsibility
of the Attribute Controller.
CRT Controller
The CRT Controller generates all the sync and timing signals for the
display and also generates the multiplexed row and column addres-
ses used for both display isfissh and CPU access of display memory.
-- integrating-all
ileeessary-~e§ie-t-Ae---tleviG8--eR8uf-eS----that-total--ChiJl---COl1f1L-
___ _
for a VGA-compatible solution can be as low as 14 chips (includes
82C455, display memory, buffers and drivers).
Anyone of a variety of CRT monitors or fiat panel displays can be
driven. Internal compensation registers ensure that industry-standard
software designed for different displays can be executed on the single
-67-
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